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Searched refs:tile (Results 1 – 124 of 124) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dnv20.c31 u32 flags, struct nvkm_fb_tile *tile) in nv20_fb_tile_init() argument
33 tile->addr = 0x00000001 | addr; in nv20_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv20_fb_tile_init()
35 tile->pitch = pitch; in nv20_fb_tile_init()
37 fb->func->tile.comp(fb, i, size, flags, tile); in nv20_fb_tile_init()
38 tile->addr |= 2; in nv20_fb_tile_init()
44 struct nvkm_fb_tile *tile) in nv20_fb_tile_comp() argument
48 if (!nvkm_mm_head(&fb->ram->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv20_fb_tile_comp()
49 if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ in nv20_fb_tile_comp()
50 else tile->zcomp = 0x04000000; /* Z24S8 */ in nv20_fb_tile_comp()
[all …]
Dnv30.c31 u32 flags, struct nvkm_fb_tile *tile) in nv30_fb_tile_init() argument
35 tile->addr = (0 << 4); in nv30_fb_tile_init()
37 if (fb->func->tile.comp) /* z compression */ in nv30_fb_tile_init()
38 fb->func->tile.comp(fb, i, size, flags, tile); in nv30_fb_tile_init()
39 tile->addr = (1 << 4); in nv30_fb_tile_init()
42 tile->addr |= 0x00000001; /* enable */ in nv30_fb_tile_init()
43 tile->addr |= addr; in nv30_fb_tile_init()
44 tile->limit = max(1u, addr + size) - 1; in nv30_fb_tile_init()
45 tile->pitch = pitch; in nv30_fb_tile_init()
50 struct nvkm_fb_tile *tile) in nv30_fb_tile_comp() argument
[all …]
Dnv10.c31 u32 flags, struct nvkm_fb_tile *tile) in nv10_fb_tile_init() argument
33 tile->addr = 0x80000000 | addr; in nv10_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv10_fb_tile_init()
35 tile->pitch = pitch; in nv10_fb_tile_init()
39 nv10_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_fini() argument
41 tile->addr = 0; in nv10_fb_tile_fini()
42 tile->limit = 0; in nv10_fb_tile_fini()
43 tile->pitch = 0; in nv10_fb_tile_fini()
44 tile->zcomp = 0; in nv10_fb_tile_fini()
48 nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_prog() argument
[all …]
Dnv35.c31 struct nvkm_fb_tile *tile) in nv35_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->ram->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv35_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ in nv35_fb_tile_comp()
37 else tile->zcomp |= 0x08000000; /* Z24S8 */ in nv35_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv35_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13; in nv35_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv35_fb_tile_comp()
49 .tile.regions = 8,
50 .tile.init = nv30_fb_tile_init,
51 .tile.comp = nv35_fb_tile_comp,
[all …]
Dnv36.c31 struct nvkm_fb_tile *tile) in nv36_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->ram->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv36_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ in nv36_fb_tile_comp()
37 else tile->zcomp |= 0x20000000; /* Z24S8 */ in nv36_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv36_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14; in nv36_fb_tile_comp()
41 tile->zcomp |= 0x80000000; in nv36_fb_tile_comp()
49 .tile.regions = 8,
50 .tile.init = nv30_fb_tile_init,
51 .tile.comp = nv36_fb_tile_comp,
[all …]
Dnv40.c31 struct nvkm_fb_tile *tile) in nv40_fb_tile_comp() argument
36 !nvkm_mm_head(&fb->ram->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv40_fb_tile_comp()
37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ in nv40_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 8); in nv40_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; in nv40_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv40_fb_tile_comp()
55 .tile.regions = 8,
56 .tile.init = nv30_fb_tile_init,
57 .tile.comp = nv40_fb_tile_comp,
58 .tile.fini = nv20_fb_tile_fini,
[all …]
Dnv25.c31 struct nvkm_fb_tile *tile) in nv25_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->ram->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv25_fb_tile_comp()
36 if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ in nv25_fb_tile_comp()
37 else tile->zcomp = 0x00200000; /* Z24S8 */ in nv25_fb_tile_comp()
38 tile->zcomp |= tile->tag->offset; in nv25_fb_tile_comp()
40 tile->zcomp |= 0x01000000; in nv25_fb_tile_comp()
47 .tile.regions = 8,
48 .tile.init = nv20_fb_tile_init,
49 .tile.comp = nv25_fb_tile_comp,
50 .tile.fini = nv20_fb_tile_fini,
[all …]
Dnv44.c31 u32 flags, struct nvkm_fb_tile *tile) in nv44_fb_tile_init() argument
33 tile->addr = 0x00000001; /* mode = vram */ in nv44_fb_tile_init()
34 tile->addr |= addr; in nv44_fb_tile_init()
35 tile->limit = max(1u, addr + size) - 1; in nv44_fb_tile_init()
36 tile->pitch = pitch; in nv44_fb_tile_init()
40 nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv44_fb_tile_prog() argument
43 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv44_fb_tile_prog()
44 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv44_fb_tile_prog()
45 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv44_fb_tile_prog()
60 .tile.regions = 12,
[all …]
Dnv46.c31 u32 flags, struct nvkm_fb_tile *tile) in nv46_fb_tile_init() argument
34 if (!(flags & 4)) tile->addr = (0 << 3); in nv46_fb_tile_init()
35 else tile->addr = (1 << 3); in nv46_fb_tile_init()
37 tile->addr |= 0x00000001; /* mode = vram */ in nv46_fb_tile_init()
38 tile->addr |= addr; in nv46_fb_tile_init()
39 tile->limit = max(1u, addr + size) - 1; in nv46_fb_tile_init()
40 tile->pitch = pitch; in nv46_fb_tile_init()
46 .tile.regions = 15,
47 .tile.init = nv46_fb_tile_init,
48 .tile.fini = nv20_fb_tile_fini,
[all …]
Dbase.c39 nvkm_fb_tile_fini(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_fini() argument
41 fb->func->tile.fini(fb, region, tile); in nvkm_fb_tile_fini()
46 u32 pitch, u32 flags, struct nvkm_fb_tile *tile) in nvkm_fb_tile_init() argument
48 fb->func->tile.init(fb, region, addr, size, pitch, flags, tile); in nvkm_fb_tile_init()
52 nvkm_fb_tile_prog(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_prog() argument
55 if (fb->func->tile.prog) { in nvkm_fb_tile_prog()
56 fb->func->tile.prog(fb, region, tile); in nvkm_fb_tile_prog()
123 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_init()
124 fb->func->tile.prog(fb, i, &fb->tile.region[i]); in nvkm_fb_init()
137 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_dtor()
[all …]
Dnv41.c30 nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv41_fb_tile_prog() argument
33 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv41_fb_tile_prog()
34 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv41_fb_tile_prog()
35 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv41_fb_tile_prog()
37 nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp); in nv41_fb_tile_prog()
49 .tile.regions = 12,
50 .tile.init = nv30_fb_tile_init,
51 .tile.comp = nv40_fb_tile_comp,
52 .tile.fini = nv20_fb_tile_fini,
53 .tile.prog = nv41_fb_tile_prog,
Dnv47.c32 .tile.regions = 15,
33 .tile.init = nv30_fb_tile_init,
34 .tile.comp = nv40_fb_tile_comp,
35 .tile.fini = nv20_fb_tile_fini,
36 .tile.prog = nv41_fb_tile_prog,
Dnv49.c32 .tile.regions = 15,
33 .tile.init = nv30_fb_tile_init,
34 .tile.comp = nv40_fb_tile_comp,
35 .tile.fini = nv20_fb_tile_fini,
36 .tile.prog = nv41_fb_tile_prog,
Dnv1a.c31 .tile.regions = 8,
32 .tile.init = nv10_fb_tile_init,
33 .tile.fini = nv10_fb_tile_fini,
34 .tile.prog = nv10_fb_tile_prog,
Dnv4e.c32 .tile.regions = 12,
33 .tile.init = nv46_fb_tile_init,
34 .tile.fini = nv20_fb_tile_fini,
35 .tile.prog = nv44_fb_tile_prog,
Dpriv.h20 } tile; member
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dnv44.c31 nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) in nv44_gr_tile() argument
44 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
45 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
46 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
53 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
54 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
55 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
56 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv44_gr_tile()
57 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv44_gr_tile()
58 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv44_gr_tile()
[all …]
Dnv40.c173 nv40_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) in nv40_gr_tile() argument
189 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile()
190 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile()
191 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile()
192 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv40_gr_tile()
193 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv40_gr_tile()
194 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_gr_tile()
198 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv40_gr_tile()
199 nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile()
204 nvkm_wr32(device, NV41_PGRAPH_ZCOMP0(i), tile->zcomp); in nv40_gr_tile()
[all …]
Dbase.c29 nvkm_gr_tile(struct nvkm_engine *engine, int region, struct nvkm_fb_tile *tile) in nvkm_gr_tile() argument
32 if (gr->func->tile) in nvkm_gr_tile()
33 gr->func->tile(gr, region, tile); in nvkm_gr_tile()
124 .tile = nvkm_gr_tile,
Dnv20.c148 nv20_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) in nv20_gr_tile() argument
158 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv20_gr_tile()
159 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv20_gr_tile()
160 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv20_gr_tile()
163 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit); in nv20_gr_tile()
165 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch); in nv20_gr_tile()
167 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr); in nv20_gr_tile()
170 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv20_gr_tile()
172 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp); in nv20_gr_tile()
349 .tile = nv20_gr_tile,
Dnv15.c30 .tile = nv10_gr_tile,
Dnv17.c30 .tile = nv10_gr_tile,
Dpriv.h20 void (*tile)(struct nvkm_gr *, int region, struct nvkm_fb_tile *); member
Dnv10.c1049 nv10_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) in nv10_gr_tile() argument
1059 nvkm_wr32(device, NV10_PGRAPH_TLIMIT(i), tile->limit); in nv10_gr_tile()
1060 nvkm_wr32(device, NV10_PGRAPH_TSIZE(i), tile->pitch); in nv10_gr_tile()
1061 nvkm_wr32(device, NV10_PGRAPH_TILE(i), tile->addr); in nv10_gr_tile()
1192 .tile = nv10_gr_tile,
Dnv2a.c99 .tile = nv20_gr_tile,
Dnv34.c107 .tile = nv20_gr_tile,
Dnv35.c107 .tile = nv20_gr_tile,
Dnv25.c108 .tile = nv20_gr_tile,
Dnv30.c170 .tile = nv20_gr_tile,
/linux-4.4.14/arch/tile/
DMakefile17 CROSS_COMPILE := $(TILERA_ROOT)/bin/tile-
38 ifeq ($(ARCH),tile)
54 head-y := arch/tile/kernel/head_$(BITS).o
56 libs-y += arch/tile/lib/
60 core-y += arch/tile/
62 core-$(CONFIG_TILE_GXIO) += arch/tile/gxio/
65 INSTALL_PATH ?= $(TILERA_ROOT)/tile/boot
DKconfig.debug22 defined in arch/tile/kernel/hvglue.S. This allows tracing
DKconfig132 # Building with ARCH=tilegx (or ARCH=tile) implies using the
155 default "arch/tile/configs/tilepro_defconfig" if !TILEGX
156 default "arch/tile/configs/tilegx_defconfig" if TILEGX
421 source "arch/tile/gxio/Kconfig"
488 source "arch/tile/Kconfig.debug"
496 source "arch/tile/kvm/Kconfig"
/linux-4.4.14/Documentation/devicetree/bindings/arm/
Dvexpress.txt8 The motherboard and each core tile should be described by a separate
9 Device Tree source file, with the tile's description including
21 where <model> is the full tile model name (as used in the tile's
27 If a tile comes in several variants or can be used in more then one
40 - tile model name (use name from the tile's Technical Reference
43 - tile's HBI number (unique ARM's board model ID, visible on the
106 0xf means "master" site (site containing main CPU tile)
123 between the motherboard and the tile. The first cell defines the Chip
125 All interrupt lines between the motherboard and the tile are active
140 can be used to obtain required phandle in the tile's "aliases" node:
[all …]
Dvexpress-scc.txt16 where <model> is the full tile model name (as used
17 in the tile's Technical Reference Manual),
/linux-4.4.14/drivers/hid/
Dhid-picolcd_fb.c101 int chip, int tile) in picolcd_fb_send_tile() argument
124 hid_set_field(report1->field[0], 4, 0xb8 | tile); in picolcd_fb_send_tile()
137 tdata = vbitmap + (tile * 4 + chip) * 64; in picolcd_fb_send_tile()
152 int chip, int tile) in picolcd_fb_update_tile() argument
156 u8 *vdata = vbitmap + (tile * 4 + chip) * 64; in picolcd_fb_update_tile()
160 const u8 *bdata = bitmap + tile * 256 + chip * 8 + b * 32; in picolcd_fb_update_tile()
168 const u8 *bdata = bitmap + (tile * 256 + chip * 8 + b * 32) * 8; in picolcd_fb_update_tile()
237 int chip, tile, n; in picolcd_fb_update() local
258 for (tile = 0; tile < 8; tile++) { in picolcd_fb_update()
261 fbdata->bpp, chip, tile)) in picolcd_fb_update()
[all …]
/linux-4.4.14/drivers/gpu/drm/nouveau/
Dnouveau_bo.c50 int i = reg - drm->tile.reg; in nv10_bo_update_tile_region()
53 struct nvkm_fb_tile *tile = &fb->tile.region[i]; in nv10_bo_update_tile_region() local
57 if (tile->pitch) in nv10_bo_update_tile_region()
58 nvkm_fb_tile_fini(fb, i, tile); in nv10_bo_update_tile_region()
61 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); in nv10_bo_update_tile_region()
63 nvkm_fb_tile_prog(fb, i, tile); in nv10_bo_update_tile_region()
70 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; in nv10_bo_get_tile_region() local
72 spin_lock(&drm->tile.lock); in nv10_bo_get_tile_region()
74 if (!tile->used && in nv10_bo_get_tile_region()
75 (!tile->fence || nouveau_fence_done(tile->fence))) in nv10_bo_get_tile_region()
[all …]
Dnouveau_bo.h31 struct nouveau_drm_tile *tile; member
Dnouveau_drm.h158 } tile; member
Dnv50_display.c2416 u8 tile = nvbo->tile_mode; in nv50_fb_ctor() local
2419 tile >>= 4; /* yep.. */ in nv50_fb_ctor()
2434 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : in nv50_fb_ctor()
2439 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : in nv50_fb_ctor()
2442 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : in nv50_fb_ctor()
Dnouveau_drm.c401 spin_lock_init(&drm->tile.lock); in nouveau_drm_load()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/core/
Dengine.c65 if (engine->func->tile) in nvkm_engine_tile()
66 engine->func->tile(engine, region, &fb->tile.region[region]); in nvkm_engine_tile()
116 for (i = 0; fb && i < fb->tile.regions; i++) in nvkm_engine_init()
/linux-4.4.14/arch/tile/kernel/
Dsmp.c240 HV_Coord tile; in ipi_init() local
244 tile.x = cpu_x(cpu); in ipi_init()
245 tile.y = cpu_y(cpu); in ipi_init()
246 if (hv_get_ipi_pte(tile, KERNEL_PL, &pte) != 0) in ipi_init()
Dprocess.c625 HV_Coord tile; in arch_trigger_all_cpu_backtrace() local
655 tile.x = cpu_x(cpu); in arch_trigger_all_cpu_backtrace()
656 tile.y = cpu_y(cpu); in arch_trigger_all_cpu_backtrace()
657 info[cpu] = hv_send_nmi(tile, TILE_NMI_DUMP_STACK, 0); in arch_trigger_all_cpu_backtrace()
Dvmlinux.lds.S10 OUTPUT_ARCH(tile)
Dhvglue_trace.c194 HV_WRAP3(int, hv_get_ipi_pte, HV_Coord, tile, int, pl, HV_PTE*, pte)
201 HV_WRAP2(HV_Errno, hv_trigger_ipi, HV_Coord, tile, int, interrupt)
269 HV_WRAP3(HV_NMI_Info, hv_send_nmi, HV_Coord, tile, unsigned long, info,
DMakefile10 intvec_$(BITS).o regs_$(BITS).o tile-desc_$(BITS).o
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv31.c114 nv31_mpeg_tile(struct nvkm_engine *engine, int i, struct nvkm_fb_tile *tile) in nv31_mpeg_tile() argument
119 nvkm_wr32(device, 0x00b008 + (i * 0x10), tile->pitch); in nv31_mpeg_tile()
120 nvkm_wr32(device, 0x00b004 + (i * 0x10), tile->limit); in nv31_mpeg_tile()
121 nvkm_wr32(device, 0x00b000 + (i * 0x10), tile->addr); in nv31_mpeg_tile()
262 .tile = nv31_mpeg_tile,
Dnv44.c197 .tile = nv31_mpeg_tile,
/linux-4.4.14/tools/perf/config/
DMakefile.arch11 -e s/tile.*/tile/ )
/linux-4.4.14/arch/arm/mach-vexpress/
DKconfig52 tile support or Flattened Device Tree based support options.
67 The TC2 (A15x2 A7x3) versatile express core tile integrates a logic
80 with a TC2 (A15x2 A7x3) big.LITTLE core tile.
/linux-4.4.14/arch/arm/mach-realview/
DKconfig33 Enable support for the Cortex-A9MPCore tile fitted to the
46 Enable support for the ARM11MPCore tile fitted to the Realview(R)
53 Enable support for the ARM11MPCore Revision B tile on the
56 not compatible with other revisions of the ARM11MPCore tile.
/linux-4.4.14/arch/frv/kernel/
Dhead.S549 # split a tile off of the region defined by GR8-GR9
552 # GR4 - IAMPR value representing tile
553 # GR5 - DAMPR value representing tile
554 # GR6 - IAMLR value representing tile
555 # GR7 - DAMLR value representing tile
557 # GR9 region top pointer updated to exclude new tile
Dhead-uc-fr451.S64 movgs gr5,dampr11 ; General I/O tile
67 # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
Dhead-uc-fr401.S250 movgs gr5,dampr7 ; General I/O tile
252 # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
Dhead-mmu-fr451.S248 movgs gr5,damlr11 ; General I/O tile
Dhead-uc-fr555.S240 # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
/linux-4.4.14/drivers/gpu/drm/
Ddrm_edid.c4057 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; in drm_parse_display_id() local
4064 w = tile->tile_size[0] | tile->tile_size[1] << 8; in drm_parse_display_id()
4065 h = tile->tile_size[2] | tile->tile_size[3] << 8; in drm_parse_display_id()
4067 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); in drm_parse_display_id()
4068 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); in drm_parse_display_id()
4069 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); in drm_parse_display_id()
4070 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); in drm_parse_display_id()
4073 if (tile->tile_cap & 0x80) in drm_parse_display_id()
4083 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); in drm_parse_display_id()
4087 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); in drm_parse_display_id()
[all …]
Ddrm_crtc.c4649 char tile[256]; in drm_mode_connector_set_tile_property() local
4662 snprintf(tile, 256, "%d:%d:%d:%d:%d:%d:%d:%d", in drm_mode_connector_set_tile_property()
4670 strlen(tile) + 1, in drm_mode_connector_set_tile_property()
4671 tile, in drm_mode_connector_set_tile_property()
/linux-4.4.14/Documentation/features/sched/numa-balancing/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/vm/numa-memblock/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/vm/THP/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/time/irq-time-acct/
Darch-support.txt35 | tile: | .. |
/linux-4.4.14/Documentation/features/seccomp/seccomp-filter/
Darch-support.txt35 | tile: | ok |
/linux-4.4.14/Documentation/features/locking/queued-spinlocks/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/drivers/gpu/drm/nouveau/include/nvkm/core/
Dengine.h22 void (*tile)(struct nvkm_engine *, int region, struct nvkm_fb_tile *); member
/linux-4.4.14/Documentation/features/vm/ioremap_prot/
Darch-support.txt35 | tile: | ok |
/linux-4.4.14/Documentation/features/vm/TLB/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/debug/optprobes/
Darch-support.txt35 | tile: | ok |
/linux-4.4.14/Documentation/features/time/clockevents/
Darch-support.txt35 | tile: | ok |
/linux-4.4.14/Documentation/features/time/arch-tick-broadcast/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/locking/queued-rwlocks/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/time/context-tracking/
Darch-support.txt35 | tile: | ok |
/linux-4.4.14/Documentation/features/core/BPF-JIT/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/perf/kprobes-event/
Darch-support.txt35 | tile: | ok |
/linux-4.4.14/Documentation/features/io/dma_map_attrs/
Darch-support.txt35 | tile: | ok |
/linux-4.4.14/Documentation/features/locking/rwsem-optimized/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/vm/pmdp_splitting_flush/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/locking/lockdep/
Darch-support.txt35 | tile: | ok |
/linux-4.4.14/Documentation/features/io/sg-chain/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/vm/PG_uncached/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/debug/uprobes/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/lib/strncasecmp/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/debug/kgdb/
Darch-support.txt35 | tile: | ok |
/linux-4.4.14/Documentation/features/debug/stackprotector/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/debug/kretprobes/
Darch-support.txt35 | tile: | ok |
/linux-4.4.14/Documentation/features/time/virt-cpuacct/
Darch-support.txt35 | tile: | ok |
/linux-4.4.14/Documentation/features/debug/kprobes/
Darch-support.txt35 | tile: | ok |
/linux-4.4.14/Documentation/features/io/dma-contiguous/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/debug/KASAN/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/io/dma-api-debug/
Darch-support.txt35 | tile: | ok |
/linux-4.4.14/Documentation/features/core/tracehook/
Darch-support.txt35 | tile: | ok |
/linux-4.4.14/Documentation/features/vm/pte_special/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/perf/perf-regs/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/perf/perf-stackdump/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/vm/huge-vmap/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/time/modern-timekeeping/
Darch-support.txt35 | tile: | ok |
/linux-4.4.14/Documentation/features/core/jump-labels/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/locking/cmpxchg-local/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/debug/kprobes-on-ftrace/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/debug/user-ret-profiler/
Darch-support.txt35 | tile: | ok |
/linux-4.4.14/Documentation/features/debug/gcov-profile-all/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/core/generic-idle-thread/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/Documentation/features/vm/ELF-ASLR/
Darch-support.txt35 | tile: | TODO |
/linux-4.4.14/arch/tile/kernel/vdso/
Dvdso.lds.S18 OUTPUT_ARCH(tile)
/linux-4.4.14/arch/arm/include/debug/
Dvexpress.S29 @ - the original A9 core tile (based on ARM Cortex-A9 r0p1)
/linux-4.4.14/drivers/char/
DMakefile61 obj-$(CONFIG_TILE_SROM) += tile-srom.o
/linux-4.4.14/Documentation/devicetree/bindings/interrupt-controller/
Darm,versatile-fpga-irq.txt5 controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
/linux-4.4.14/arch/tile/include/hv/
Dhypervisor.h597 int hv_get_ipi_pte(HV_Coord tile, int pl, HV_PTE* pte);
664 HV_Errno hv_trigger_ipi(HV_Coord tile, int interrupt);
1838 HV_NMI_Info hv_send_nmi(HV_Coord tile, unsigned long info, __hv64 flags);
/linux-4.4.14/drivers/gpu/drm/nouveau/include/nvkm/subdev/
Dfb.h57 } tile; member
/linux-4.4.14/drivers/net/ethernet/
DMakefile83 obj-$(CONFIG_TILE_NET) += tile/
DKconfig173 source "drivers/net/ethernet/tile/Kconfig"
/linux-4.4.14/drivers/video/fbdev/
Dgbefb.c1009 u16 *tile; in gbefb_mmap() local
1027 tile = &gbe_tiles.cpu[offset >> TILE_SHIFT]; in gbefb_mmap()
1033 phys_addr = (((unsigned long) (*tile)) << TILE_SHIFT) + offset; in gbefb_mmap()
1046 tile++; in gbefb_mmap()
Dcirrusfb.c867 unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407); in cirrusfb_set_par_foo() local
877 fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407); in cirrusfb_set_par_foo()
DKconfig211 This enables tile blitting. Tile blitting is a drawing technique
214 default drawing element is a tile, drawing functions will be passed
/linux-4.4.14/tools/perf/
DMANIFEST12 tools/arch/tile/include/asm/barrier.h
/linux-4.4.14/drivers/rtc/
DMakefile150 obj-$(CONFIG_RTC_DRV_TILE) += rtc-tile.o
/linux-4.4.14/Documentation/DocBook/
Dgpu.xml.db194 API-drm-mode-connector-set-tile-property
208 API-drm-mode-get-tile-group
209 API-drm-mode-create-tile-group
/linux-4.4.14/
DMakefile281 SRCARCH := tile
284 SRCARCH := tile
DMAINTAINERS10747 F: arch/tile/
10748 F: drivers/char/tile-srom.c
10750 F: drivers/net/ethernet/tile/
10751 F: drivers/rtc/rtc-tile.c
/linux-4.4.14/Documentation/
Dkmemleak.txt14 Kmemleak is supported on x86, arm, powerpc, sparc, sh, microblaze, ppc, mips, s390, metag and tile.
/linux-4.4.14/Documentation/frv/
Dfeatures.txt120 (1) The core kernel image is covered by as small a tile as possible
/linux-4.4.14/Documentation/ioctl/
Dioctl-number.txt306 0xA2 00-0F arch/tile/include/asm/hardwall.h
/linux-4.4.14/mm/
DKconfig287 # On the 'tile' arch, USB OHCI needs the bounce pool since tilegx will often
/linux-4.4.14/arch/arm/
DKconfig.debug1133 bool "Use PL011 UART0 at 0x10009000 (V2P-CA9 core tile)"
1138 this applies only to the V2P-CA9 tile.