| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| D | uvd_v1_0.c | 265 uint32_t rb_bufsz; in uvd_v1_0_start() local
376 rb_bufsz = order_base_2(ring->ring_size); in uvd_v1_0_start()
377 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v1_0_start()
378 WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v1_0_start()
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| D | ni_dma.c | 191 u32 rb_bufsz; in cayman_dma_resume() local
210 rb_bufsz = order_base_2(ring->ring_size / 4); in cayman_dma_resume()
211 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
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| D | r600_dma.c | 124 u32 rb_bufsz; in r600_dma_resume() local
131 rb_bufsz = order_base_2(ring->ring_size / 4); in r600_dma_resume()
132 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
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| D | cik_sdma.c | 369 u32 rb_bufsz; in cik_sdma_gfx_resume() local
388 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
389 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
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| D | r600.c | 2717 u32 rb_bufsz; in r600_cp_resume() local
2727 rb_bufsz = order_base_2(ring->ring_size / 8); in r600_cp_resume()
2728 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in r600_cp_resume()
2779 u32 rb_bufsz; in r600_ring_init() local
2783 rb_bufsz = order_base_2(ring_size / 8); in r600_ring_init()
2784 ring_size = (1 << (rb_bufsz + 1)) * 4; in r600_ring_init()
3422 u32 rb_bufsz; in r600_ih_ring_init() local
3425 rb_bufsz = order_base_2(ring_size / 4); in r600_ih_ring_init()
3426 ring_size = (1 << rb_bufsz) * 4; in r600_ih_ring_init()
3628 int rb_bufsz; in r600_irq_init() local
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| D | si.c | 3649 u32 rb_bufsz; in si_cp_resume() local
3666 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3667 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()
3697 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3698 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()
3721 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3722 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()
5997 int rb_bufsz; in si_irq_init() local
6028 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in si_irq_init()
6032 (rb_bufsz << 1)); in si_irq_init()
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| D | r100.c | 1112 unsigned rb_bufsz; in r100_cp_init() local
1134 rb_bufsz = order_base_2(ring_size / 8); in r100_cp_init()
1135 ring_size = (1 << (rb_bufsz + 1)) * 4; in r100_cp_init()
1168 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | in r100_cp_init()
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| D | cik.c | 4465 u32 rb_bufsz; in cik_cp_gfx_resume() local
4484 rb_bufsz = order_base_2(ring->ring_size / 8); in cik_cp_gfx_resume()
4485 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in cik_cp_gfx_resume()
7383 int rb_bufsz; in cik_irq_init() local
7414 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in cik_irq_init()
7418 (rb_bufsz << 1)); in cik_irq_init()
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| D | evergreen.c | 3156 u32 rb_bufsz; in evergreen_cp_resume() local
3172 rb_bufsz = order_base_2(ring->ring_size / 8); in evergreen_cp_resume()
3173 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in evergreen_cp_resume()
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| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_ih.c | 85 u32 rb_bufsz; in amdgpu_ih_ring_init() local
89 rb_bufsz = order_base_2(ring_size / 4); in amdgpu_ih_ring_init()
90 ring_size = (1 << rb_bufsz) * 4; in amdgpu_ih_ring_init()
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| D | cik_ih.c | 107 int rb_bufsz; in cik_ih_irq_init() local
126 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cik_ih_irq_init()
130 (rb_bufsz << 1)); in cik_ih_irq_init()
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| D | cz_ih.c | 107 int rb_bufsz; in cz_ih_irq_init() local
128 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cz_ih_irq_init()
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
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| D | iceland_ih.c | 107 int rb_bufsz; in iceland_ih_irq_init() local
128 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in iceland_ih_irq_init()
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
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| D | uvd_v4_2.c | 264 uint32_t rb_bufsz; in uvd_v4_2_start() local
377 rb_bufsz = order_base_2(ring->ring_size); in uvd_v4_2_start()
378 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v4_2_start()
379 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v4_2_start()
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| D | tonga_ih.c | 103 int rb_bufsz; in tonga_ih_irq_init() local
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in tonga_ih_irq_init()
129 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in tonga_ih_irq_init()
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| D | amdgpu_ring.c | 308 u32 rb_bufsz; in amdgpu_ring_init() local
357 rb_bufsz = order_base_2(ring_size / 8); in amdgpu_ring_init()
358 ring_size = (1 << (rb_bufsz + 1)) * 4; in amdgpu_ring_init()
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| D | uvd_v6_0.c | 292 uint32_t rb_bufsz, tmp; in uvd_v6_0_start() local
394 rb_bufsz = order_base_2(ring->ring_size); in uvd_v6_0_start()
396 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v6_0_start()
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| D | uvd_v5_0.c | 294 uint32_t rb_bufsz, tmp; in uvd_v5_0_start() local
394 rb_bufsz = order_base_2(ring->ring_size); in uvd_v5_0_start()
396 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v5_0_start()
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| D | cik_sdma.c | 401 u32 rb_bufsz; in cik_sdma_gfx_resume() local
424 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
425 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
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| D | sdma_v2_4.c | 444 u32 rb_bufsz; in sdma_v2_4_gfx_resume() local
465 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v2_4_gfx_resume()
467 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v2_4_gfx_resume()
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| D | sdma_v3_0.c | 580 u32 rb_bufsz; in sdma_v3_0_gfx_resume() local
602 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v3_0_gfx_resume()
604 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v3_0_gfx_resume()
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| D | gfx_v8_0.c | 3300 u32 rb_bufsz; in gfx_v8_0_cp_gfx_resume() local
3312 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v8_0_cp_gfx_resume()
3313 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v8_0_cp_gfx_resume()
3314 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v8_0_cp_gfx_resume()
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| D | gfx_v7_0.c | 2932 u32 rb_bufsz; in gfx_v7_0_cp_gfx_resume() local
2951 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v7_0_cp_gfx_resume()
2952 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v7_0_cp_gfx_resume()
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