Searched refs:pm8001_cw32 (Results 1 - 3 of 3) sorted by relevance

/linux-4.4.14/drivers/scsi/pm8001/
H A Dpm8001_hwi.c388 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); pm8001_bar4_shift()
437 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); mpi_set_phys_g3_with_ssc()
447 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); mpi_set_phys_g3_with_ssc()
465 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016); mpi_set_phys_g3_with_ssc()
502 pm8001_cw32(pm8001_ha, 2, offset, value); mpi_set_open_retry_interval_reg()
512 pm8001_cw32(pm8001_ha, 2, offset, value); mpi_set_open_retry_interval_reg()
531 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); mpi_init_check()
692 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1); pm8001_chip_init()
693 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0); pm8001_chip_init()
715 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); mpi_uninit_check()
781 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, soft_reset_ready_check()
783 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST); soft_reset_ready_check()
843 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); pm8001_chip_soft_rst()
855 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); pm8001_chip_soft_rst()
860 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); pm8001_chip_soft_rst()
865 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal); pm8001_chip_soft_rst()
870 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); pm8001_chip_soft_rst()
875 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal); pm8001_chip_soft_rst()
884 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature); pm8001_chip_soft_rst()
912 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); pm8001_chip_soft_rst()
924 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0); pm8001_chip_soft_rst()
935 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); pm8001_chip_soft_rst()
946 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); pm8001_chip_soft_rst()
968 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); pm8001_chip_soft_rst()
984 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); pm8001_chip_soft_rst()
992 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); pm8001_chip_soft_rst()
1003 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); pm8001_chip_soft_rst()
1030 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); pm8001_chip_soft_rst()
1042 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1); pm8001_chip_soft_rst()
1049 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); pm8001_chip_soft_rst()
1056 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); pm8001_chip_soft_rst()
1073 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); pm8001_chip_soft_rst()
1112 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); pm8001_chip_soft_rst()
1113 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); pm8001_chip_soft_rst()
1159 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); pm8001_hw_chip_rst()
1167 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); pm8001_hw_chip_rst()
1214 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); pm8001_chip_intx_interrupt_enable()
1215 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); pm8001_chip_intx_interrupt_enable()
1225 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL); pm8001_chip_intx_interrupt_disable()
1240 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE); pm8001_chip_msix_interrupt_enable()
1242 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value); pm8001_chip_msix_interrupt_enable()
1257 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE); pm8001_chip_msix_interrupt_disable()
1363 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar, pm8001_mpi_build_cmd()
1400 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset, pm8001_mpi_msg_free_set()
1461 pm8001_cw32(pm8001_ha, pm8001_mpi_msg_consume()
1474 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, pm8001_mpi_msg_consume()
H A Dpm8001_chips.h60 static inline void pm8001_cw32(struct pm8001_hba_info *pm8001_ha, u32 bar, pm8001_cw32() function
H A Dpm80xx_hwi.c54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value); pm80xx_bar4_shift()
119 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, pm80xx_get_fatal_dump()
209 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, pm80xx_get_fatal_dump()
218 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, pm80xx_get_fatal_dump()
655 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE); mpi_init_check()
1155 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET); mpi_uninit_check()
1222 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE); pm80xx_chip_soft_rst()
1304 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11); pm80xx_hw_chip_rst()
1329 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); pm80xx_chip_intx_interrupt_enable()
1330 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); pm80xx_chip_intx_interrupt_enable()
1340 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL); pm80xx_chip_intx_interrupt_disable()
1354 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF)); pm80xx_chip_interrupt_enable()
1374 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF)); pm80xx_chip_interrupt_disable()

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