Lines Matching refs:pm8001_cw32
388 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); in pm8001_bar4_shift()
437 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); in mpi_set_phys_g3_with_ssc()
447 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); in mpi_set_phys_g3_with_ssc()
465 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016); in mpi_set_phys_g3_with_ssc()
502 pm8001_cw32(pm8001_ha, 2, offset, value); in mpi_set_open_retry_interval_reg()
512 pm8001_cw32(pm8001_ha, 2, offset, value); in mpi_set_open_retry_interval_reg()
531 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); in mpi_init_check()
692 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1); in pm8001_chip_init()
693 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0); in pm8001_chip_init()
715 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); in mpi_uninit_check()
781 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, in soft_reset_ready_check()
783 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST); in soft_reset_ready_check()
843 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); in pm8001_chip_soft_rst()
855 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); in pm8001_chip_soft_rst()
860 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); in pm8001_chip_soft_rst()
865 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal); in pm8001_chip_soft_rst()
870 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); in pm8001_chip_soft_rst()
875 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal); in pm8001_chip_soft_rst()
884 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature); in pm8001_chip_soft_rst()
912 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); in pm8001_chip_soft_rst()
924 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0); in pm8001_chip_soft_rst()
935 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); in pm8001_chip_soft_rst()
946 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); in pm8001_chip_soft_rst()
968 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); in pm8001_chip_soft_rst()
984 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
992 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
1003 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
1030 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); in pm8001_chip_soft_rst()
1042 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1); in pm8001_chip_soft_rst()
1049 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); in pm8001_chip_soft_rst()
1056 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); in pm8001_chip_soft_rst()
1073 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
1112 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); in pm8001_chip_soft_rst()
1113 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); in pm8001_chip_soft_rst()
1159 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); in pm8001_hw_chip_rst()
1167 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); in pm8001_hw_chip_rst()
1214 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); in pm8001_chip_intx_interrupt_enable()
1215 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); in pm8001_chip_intx_interrupt_enable()
1225 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL); in pm8001_chip_intx_interrupt_disable()
1240 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE); in pm8001_chip_msix_interrupt_enable()
1242 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value); in pm8001_chip_msix_interrupt_enable()
1257 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE); in pm8001_chip_msix_interrupt_disable()
1363 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar, in pm8001_mpi_build_cmd()
1400 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset, in pm8001_mpi_msg_free_set()
1461 pm8001_cw32(pm8001_ha, in pm8001_mpi_msg_consume()
1474 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, in pm8001_mpi_msg_consume()