Lines Matching refs:pm8001_cw32
54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value); in pm80xx_bar4_shift()
119 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, in pm80xx_get_fatal_dump()
209 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, in pm80xx_get_fatal_dump()
218 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, in pm80xx_get_fatal_dump()
655 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE); in mpi_init_check()
1155 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET); in mpi_uninit_check()
1222 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE); in pm80xx_chip_soft_rst()
1304 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11); in pm80xx_hw_chip_rst()
1329 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); in pm80xx_chip_intx_interrupt_enable()
1330 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); in pm80xx_chip_intx_interrupt_enable()
1340 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL); in pm80xx_chip_intx_interrupt_disable()
1354 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF)); in pm80xx_chip_interrupt_enable()
1374 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF)); in pm80xx_chip_interrupt_disable()