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/linux-4.4.14/arch/powerpc/boot/dts/fsl/
Dqoriq-clockgen1.dtsi56 pll1: pll1@820 { label
61 clock-output-names = "pll1", "pll1-div2";
67 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
68 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
75 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
76 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dt1040si-post.dtsi432 <&pll1 0>, <&pll1 1>, <&pll1 2>;
433 clock-names = "pll0", "pll0-div2", "pll1-div4",
434 "pll1", "pll1-div2", "pll1-div4";
443 <&pll1 0>, <&pll1 1>, <&pll1 2>;
444 clock-names = "pll0", "pll0-div2", "pll1-div4",
445 "pll1", "pll1-div2", "pll1-div4";
454 <&pll1 0>, <&pll1 1>, <&pll1 2>;
455 clock-names = "pll0", "pll0-div2", "pll1-div4",
456 "pll1", "pll1-div2", "pll1-div4";
465 <&pll1 0>, <&pll1 1>, <&pll1 2>;
Dqoriq-clockgen2.dtsi55 pll1: pll1@820 { label
60 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
Dt2081si-post.dtsi544 <&pll1 0>, <&pll1 1>, <&pll1 2>;
546 "pll1", "pll1-div2", "pll1-div4";
555 <&pll1 0>, <&pll1 1>, <&pll1 2>;
557 "pll1", "pll1-div2", "pll1-div4";
Dp2041si-post.dtsi335 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
336 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
344 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
345 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp3041si-post.dtsi362 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
363 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
371 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
372 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp5040si-post.dtsi327 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
328 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
336 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
337 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp4080si-post.dtsi398 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
399 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
407 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
408 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Db4si-post.dtsi410 <&pll1 0>, <&pll1 1>, <&pll1 2>;
412 "pll1", "pll1-div2", "pll1-div4";
Dt4240si-post.dtsi983 <&pll1 0>, <&pll1 1>, <&pll1 2>,
986 "pll1", "pll1-div2", "pll1-div4",
996 <&pll1 0>, <&pll1 1>, <&pll1 2>,
999 "pll1", "pll1-div2", "pll1-div4",
/linux-4.4.14/arch/avr32/boards/favr-32/
Dsetup.c277 struct clk *pll1; in set_abdac_rate() local
289 pll1 = clk_get(NULL, "pll1"); in set_abdac_rate()
290 if (IS_ERR(pll1)) { in set_abdac_rate()
291 retval = PTR_ERR(pll1); in set_abdac_rate()
301 retval = clk_set_parent(pll1, osc1); in set_abdac_rate()
311 retval = clk_round_rate(pll1, in set_abdac_rate()
318 retval = clk_set_rate(pll1, retval); in set_abdac_rate()
322 retval = clk_set_parent(abdac, pll1); in set_abdac_rate()
329 clk_put(pll1); in set_abdac_rate()
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Dqoriq-clock.txt148 pll1: pll1@820 {
153 clock-output-names = "pll1", "pll1-div2";
160 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
161 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
169 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
170 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Drenesas,r8a73a4-cpg-clocks.txt17 "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
29 clock-output-names = "main", "pll0", "pll1", "pll2",
Drenesas,sh73a0-cpg-clocks.txt19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
31 clock-output-names = "main", "pll0", "pll1", "pll2",
Dsunxi.txt10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
128 pll1: clk@01c20000 {
130 compatible = "allwinner,sun4i-a10-pll1-clk";
133 clock-output-names = "pll1";
156 clocks = <&osc32k>, <&osc24M>, <&pll1>;
Dsilabs,si5351.txt77 /* connect xtal input as source of pll0 and pll1 */
100 * - pll1 as clock source of multisynth1
102 * - multisynth1 can change pll1
Drenesas,rcar-gen2-cpg-clocks.txt23 "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
44 clock-output-names = "main", "pll0, "pll1", "pll3",
Dprima2-clock.txt17 pll1 2
Dimx28-clock.txt16 pll1 2
/linux-4.4.14/arch/arm/boot/dts/
Dstih415-clock.dtsi40 "clk-s-a0-pll1";
98 "clk-s-a1-pll1";
165 clk_m_a0_pll1: clk-m-a0-pll1 {
171 clock-output-names = "clk-m-a0-pll1-phi0",
172 "clk-m-a0-pll1-phi1",
173 "clk-m-a0-pll1-phi2",
174 "clk-m-a0-pll1-phi3";
279 clk_m_a1_pll1: clk-m-a1-pll1 {
285 clock-output-names = "clk-m-a1-pll1-phi0",
286 "clk-m-a1-pll1-phi1",
[all …]
Dstih416-clock.dtsi41 "clk-s-a0-pll1";
99 "clk-s-a1-pll1";
167 clk_m_a0_pll1: clk-m-a0-pll1 {
173 clock-output-names = "clk-m-a0-pll1-phi0",
174 "clk-m-a0-pll1-phi1",
175 "clk-m-a0-pll1-phi2",
176 "clk-m-a0-pll1-phi3";
281 clk_m_a1_pll1: clk-m-a1-pll1 {
287 clock-output-names = "clk-m-a1-pll1-phi0",
288 "clk-m-a1-pll1-phi1",
[all …]
Ddra72x.dtsi42 reg-names = "dss", "pll1_clkctrl", "pll1";
Dsun8i-a23-a33.dtsi115 pll1: clk@01c20000 { label
117 compatible = "allwinner,sun8i-a23-pll1-clk";
120 clock-output-names = "pll1";
150 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
Dsun5i.dtsi98 pll1: clk@01c20000 { label
100 compatible = "allwinner,sun4i-a10-pll1-clk";
103 clock-output-names = "pll1";
117 compatible = "allwinner,sun4i-a10-pll1-clk";
144 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
Ddove-cubox.dts92 /* connect xtal input as source of pll0 and pll1 */
Dstih407-clock.dtsi144 clk_s_c0_pll1: clk-s-c0-pll1 {
150 clock-output-names = "clk-s-c0-pll1-odf-0";
Ddra74x.dtsi113 reg-names = "dss", "pll1_clkctrl", "pll1",
Dstih410-clock.dtsi147 clk_s_c0_pll1: clk-s-c0-pll1 {
153 clock-output-names = "clk-s-c0-pll1-odf-0";
Dstih418-clock.dtsi147 clk_s_c0_pll1: clk-s-c0-pll1 {
153 clock-output-names = "clk-s-c0-pll1-odf-0";
Dls1021a.dtsi207 clock-output-names = "cga-pll1", "cga-pll1-div2",
208 "cga-pll1-div4";
Dsun4i-a10.dtsi191 pll1: clk@01c20000 { label
193 compatible = "allwinner,sun4i-a10-pll1-clk";
196 clock-output-names = "pll1";
210 compatible = "allwinner,sun4i-a10-pll1-clk";
237 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
Dsun6i-a31.dtsi195 pll1: clk@01c20000 { label
197 compatible = "allwinner,sun6i-a31-pll1-clk";
200 clock-output-names = "pll1";
222 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
Dste-nomadik-stn8815.dtsi200 pll1: pll1@0 { label
211 clocks = <&pll1>;
Dsun7i-a20.dtsi195 pll1: clk@01c20000 { label
197 compatible = "allwinner,sun4i-a10-pll1-clk";
200 clock-output-names = "pll1";
249 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
Dr8a7793.dtsi170 clock-output-names = "main", "pll0", "pll1", "pll3",
Dimx6ul.dtsi80 "pll1_sys", "pll1_bypass", "pll1",
Dr8a73a4.dtsi511 clock-output-names = "main", "pll0", "pll1", "pll2",
Dsh73a0.dtsi588 clock-output-names = "main", "pll0", "pll1", "pll2",
Dr8a7794.dtsi774 clock-output-names = "main", "pll0", "pll1", "pll3",
Dr8a7791.dtsi1042 clock-output-names = "main", "pll0", "pll1", "pll3",
Dr8a7790.dtsi1010 clock-output-names = "main", "pll0", "pll1", "pll3",
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
231 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
/linux-4.4.14/drivers/gpu/drm/tegra/
Dhdmi.c28 u32 pll1; member
173 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
188 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
206 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
220 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
234 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
251 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
269 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
288 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
307 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
[all …]
/linux-4.4.14/drivers/gpu/drm/nouveau/dispnv04/
Dhw.c132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
146 if (!(pll1 & 0x1100)) in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
156 pllvals->N2 = ((pll1 >> 21) & 0x18) | in nouveau_hw_decode_pll()
157 ((pll1 >> 19) & 0x7); in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/clock/st/
Dst,clkgen.txt72 "clk-s-a0-pll1";
92 <&clk-s_a0_pll 2>; /* pll1 */
Dst,clkgen-pll.txt50 "clk-s-a0-pll1";
/linux-4.4.14/drivers/clk/sirf/
Dclk-prima2.c61 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
137 for (i = pll1; i < maxclk; i++) { in prima2_clk_init()
Dclk-atlas6.c62 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
138 for (i = pll1; i < maxclk; i++) { in atlas6_clk_init()
/linux-4.4.14/drivers/clk/mxs/
Dclk-imx28.c139 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
175 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
/linux-4.4.14/Documentation/devicetree/bindings/display/ti/
Dti,dra7-dss.txt24 'pll1', 'pll2_clkctrl', 'pll2'
/linux-4.4.14/arch/avr32/mach-at32ap/
Dat32ap700x.c316 static struct clk pll1 = { variable
572 if (parent == &osc1 || parent == &pll1) in genclk_set_parent()
579 if (parent == &pll0 || parent == &pll1) in genclk_set_parent()
599 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1; in genclk_init_parent()
2201 &pll1,
2277 pll1.parent = &osc1; in setup_platform()
/linux-4.4.14/Documentation/
Dprintk-formats.txt274 %pC pll1
275 %pCn pll1
/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_ddi.c1169 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; in bxt_calc_pll_link()
1740 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n); in bxt_ddi_pll_select()
2840 temp |= pll->config.hw_state.pll1; in bxt_ddi_pll_enable()
2944 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); in bxt_ddi_pll_get_hw_state()
2945 hw_state->pll1 &= PORT_PLL_N_MASK; in bxt_ddi_pll_get_hw_state()
Di915_drv.h387 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, member
Dintel_display.c12069 pipe_config->dpll_hw_state.pll1, in intel_dump_pipe_config()