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Searched refs:pll0 (Results 1 – 42 of 42) sorted by relevance

/linux-4.4.14/arch/powerpc/boot/dts/fsl/
Dqoriq-clockgen1.dtsi49 pll0: pll0@800 { label
54 clock-output-names = "pll0", "pll0-div2";
67 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
68 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
75 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
76 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dt1040si-post.dtsi431 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
433 clock-names = "pll0", "pll0-div2", "pll1-div4",
442 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
444 clock-names = "pll0", "pll0-div2", "pll1-div4",
453 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
455 clock-names = "pll0", "pll0-div2", "pll1-div4",
464 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
Dqoriq-clockgen2.dtsi48 pll0: pll0@800 { label
53 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
Dt2081si-post.dtsi543 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
545 clock-names = "pll0", "pll0-div2", "pll0-div4",
554 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
556 clock-names = "pll0", "pll0-div2", "pll0-div4",
Dp2041si-post.dtsi335 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
336 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
344 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
345 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp3041si-post.dtsi362 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
363 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
371 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
372 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp5040si-post.dtsi327 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
328 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
336 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
337 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp4080si-post.dtsi398 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
399 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
407 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
408 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Db4si-post.dtsi409 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
411 clock-names = "pll0", "pll0-div2", "pll0-div4",
Dt4240si-post.dtsi982 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
985 clock-names = "pll0", "pll0-div2", "pll0-div4",
995 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
998 clock-names = "pll0", "pll0-div2", "pll0-div4",
Dt1023si-post.dtsi249 clocks = <&pll0 0>, <&pll0 1>;
257 clocks = <&pll0 0>, <&pll0 1>;
/linux-4.4.14/arch/arm/boot/dts/
Dstih415-clock.dtsi38 clock-output-names = "clk-s-a0-pll0-hs",
39 "clk-s-a0-pll0-ls",
96 clock-output-names = "clk-s-a1-pll0-hs",
97 "clk-s-a1-pll0-ls",
153 clk_m_a0_pll0: clk-m-a0-pll0 {
159 clock-output-names = "clk-m-a0-pll0-phi0",
160 "clk-m-a0-pll0-phi1",
161 "clk-m-a0-pll0-phi2",
162 "clk-m-a0-pll0-phi3";
267 clk_m_a1_pll0: clk-m-a1-pll0 {
[all …]
Dstih416-clock.dtsi39 clock-output-names = "clk-s-a0-pll0-hs",
40 "clk-s-a0-pll0-ls",
97 clock-output-names = "clk-s-a1-pll0-hs",
98 "clk-s-a1-pll0-ls",
155 clk_m_a0_pll0: clk-m-a0-pll0 {
161 clock-output-names = "clk-m-a0-pll0-phi0",
162 "clk-m-a0-pll0-phi1",
163 "clk-m-a0-pll0-phi2",
164 "clk-m-a0-pll0-phi3";
269 clk_m_a1_pll0: clk-m-a1-pll0 {
[all …]
Ddove-cubox.dts92 /* connect xtal input as source of pll0 and pll1 */
Dstih407-clock.dtsi135 clk_s_c0_pll0: clk-s-c0-pll0 {
141 clock-output-names = "clk-s-c0-pll0-odf-0";
Dstih410-clock.dtsi138 clk_s_c0_pll0: clk-s-c0-pll0 {
144 clock-output-names = "clk-s-c0-pll0-odf-0";
Dstih418-clock.dtsi138 clk_s_c0_pll0: clk-s-c0-pll0 {
144 clock-output-names = "clk-s-c0-pll0-odf-0";
Dr8a7793.dtsi170 clock-output-names = "main", "pll0", "pll1", "pll3",
Dr8a73a4.dtsi511 clock-output-names = "main", "pll0", "pll1", "pll2",
Dsh73a0.dtsi588 clock-output-names = "main", "pll0", "pll1", "pll2",
Dr8a7794.dtsi774 clock-output-names = "main", "pll0", "pll1", "pll3",
Dr8a7791.dtsi1042 clock-output-names = "main", "pll0", "pll1", "pll3",
Dr8a7790.dtsi1010 clock-output-names = "main", "pll0", "pll1", "pll3",
/linux-4.4.14/drivers/bcma/
Ddriver_chipcommon_pmu.c84 u32 pll0, mask; in bcma_pmu2_pll_init0() local
115 pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); in bcma_pmu2_pll_init0()
116 freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> in bcma_pmu2_pll_init0()
137 pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; in bcma_pmu2_pll_init0()
138 pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; in bcma_pmu2_pll_init0()
139 bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); in bcma_pmu2_pll_init0()
339 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) in bcma_pmu_pll_clock() argument
344 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); in bcma_pmu_pll_clock()
356 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); in bcma_pmu_pll_clock()
360 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF); in bcma_pmu_pll_clock()
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Dqoriq-clock.txt140 pll0: pll0@800 {
145 clock-output-names = "pll0", "pll0-div2";
160 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
161 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
169 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
170 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Drenesas,r8a73a4-cpg-clocks.txt17 "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
29 clock-output-names = "main", "pll0", "pll1", "pll2",
Drenesas,sh73a0-cpg-clocks.txt19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
31 clock-output-names = "main", "pll0", "pll1", "pll2",
Dsilabs,si5351.txt77 /* connect xtal input as source of pll0 and pll1 */
83 * - pll0 as clock source of multisynth0
85 * - multisynth0 can change pll0
Drenesas,rcar-gen2-cpg-clocks.txt23 "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
44 clock-output-names = "main", "pll0, "pll1", "pll3",
Dimx28-clock.txt15 pll0 1
/linux-4.4.14/Documentation/devicetree/bindings/clock/st/
Dst,clkgen.txt70 clock-output-names = "clk-s-a0-pll0-hs",
71 "clk-s-a0-pll0-ls",
91 <&clk-s_a0_pll 0>, /* pll0 hs */
Dst,clkgen-pll.txt48 clock-output-names = "clk-s-a0-pll0-hs",
49 "clk-s-a0-pll0-ls",
/linux-4.4.14/drivers/gpu/drm/tegra/
Dhdmi.c27 u32 pll0; member
170 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
185 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
203 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
217 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
231 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
249 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
267 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
286 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
305 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
[all …]
/linux-4.4.14/arch/arc/boot/dts/
Dabilis_tb10x.dtsi46 pll0: oscillator { label
49 clock-output-names = "pll0";
54 clocks = <&pll0>;
60 clocks = <&pll0>;
Dabilis_tb101.dtsi31 pll0: oscillator { label
Dabilis_tb100.dtsi31 pll0: oscillator { label
/linux-4.4.14/arch/avr32/mach-at32ap/
Dat32ap700x.c311 static struct clk pll0 = { variable
574 else if (parent == &osc0 || parent == &pll0) in genclk_set_parent()
579 if (parent == &pll0 || parent == &pll1) in genclk_set_parent()
601 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0; in genclk_init_parent()
1510 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0); in at32_add_device_lcdc()
1511 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0)); in at32_add_device_lcdc()
2200 &pll0,
2267 main_clock = &pll0; in setup_platform()
2268 cpu_clk.parent = &pll0; in setup_platform()
2275 pll0.parent = &osc1; in setup_platform()
/linux-4.4.14/drivers/clk/mxs/
Dclk-imx28.c139 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
174 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_ddi.c1166 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; in bxt_calc_pll_link()
1739 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; in bxt_ddi_pll_select()
2834 temp |= pll->config.hw_state.pll0; in bxt_ddi_pll_enable()
2941 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); in bxt_ddi_pll_get_hw_state()
2942 hw_state->pll0 &= PORT_PLL_M2_MASK; in bxt_ddi_pll_get_hw_state()
Di915_drv.h387 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, member
Dintel_display.c12068 pipe_config->dpll_hw_state.pll0, in intel_dump_pipe_config()
/linux-4.4.14/drivers/clk/qcom/
Dgcc-ipq806x.c35 static struct clk_pll pll0 = { variable
2723 [PLL0] = &pll0.clkr,