| /linux-4.4.14/drivers/clk/mxs/ |
| H A D | clk-imx28.c | 133 static const char *const sel_pll0[] __initconst = { "pll0", "ref_xtal", };
136 static const char *const ptp_sels[] __initconst = { "ref_xtal", "pll0", };
139 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator in enum:imx28_clk
174 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); mx28_clocks_init()
177 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); mx28_clocks_init()
178 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); mx28_clocks_init()
179 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); mx28_clocks_init()
180 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); mx28_clocks_init()
181 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); mx28_clocks_init()
182 clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1); mx28_clocks_init()
183 clks[ref_gpmi] = mxs_clk_ref("ref_gpmi", "pll0", FRAC1, 2); mx28_clocks_init()
215 clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll0", 1, 4); mx28_clocks_init()
235 clks[usb0_phy] = clk_register_gate(NULL, "usb0_phy", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock); mx28_clocks_init()
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| /linux-4.4.14/drivers/bcma/ |
| H A D | driver_chipcommon_pmu.c | 84 u32 pll0, mask; bcma_pmu2_pll_init0() local
115 pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); bcma_pmu2_pll_init0()
116 freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> bcma_pmu2_pll_init0()
137 pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; bcma_pmu2_pll_init0()
138 pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; bcma_pmu2_pll_init0()
139 bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); bcma_pmu2_pll_init0()
337 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
339 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) bcma_pmu_pll_clock() argument
344 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); bcma_pmu_pll_clock()
356 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); bcma_pmu_pll_clock()
360 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF); bcma_pmu_pll_clock()
364 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF); bcma_pmu_pll_clock()
375 static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m) bcma_pmu_pll_clock_bcm4706() argument
383 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF); bcma_pmu_pll_clock_bcm4706()
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| /linux-4.4.14/arch/avr32/boards/atstk1000/ |
| H A D | atstk1004.c | 94 pll = clk_get(NULL, "pll0"); atstk1004_setup_extdac()
99 pr_debug("STK1000: failed to set pll0 as parent for DAC clock\n"); atstk1004_setup_extdac()
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| H A D | atstk1003.c | 89 pll = clk_get(NULL, "pll0"); atstk1003_setup_extdac()
94 pr_debug("STK1000: failed to set pll0 as parent for DAC clock\n"); atstk1003_setup_extdac()
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| H A D | atstk1002.c | 222 pll = clk_get(NULL, "pll0"); atstk1002_setup_extdac()
227 pr_debug("STK1000: failed to set pll0 as parent for DAC clock\n"); atstk1002_setup_extdac()
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| /linux-4.4.14/arch/arm/mach-w90x900/ |
| H A D | clksel.c | 77 if (strcmp(src, "pll0") == 0) nuc900_clock_source()
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| H A D | cpu.c | 195 nuc900_clock_source(NULL, "pll0"); nuc900_set_cpufreq()
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| /linux-4.4.14/drivers/gpu/drm/tegra/ |
| H A D | hdmi.c | 27 u32 pll0; member in struct:tmds_config
170 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
185 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
203 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
217 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
231 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
249 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
267 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
286 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
305 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
328 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
346 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
365 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
384 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
747 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0); tegra_hdmi_setup_tmds()
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| /linux-4.4.14/drivers/clk/shmobile/ |
| H A D | clk-r8a73a4.c | 92 } else if (!strcmp(name, "pll0")) { r8a73a4_cpg_register_clock()
158 parent_name = "pll0"; r8a73a4_cpg_register_clock()
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| H A D | clk-sh73a0.c | 50 { "zg", "pll0", CPG_FRQCRA, 16 },
132 parent_name = "pll0"; sh73a0_cpg_register_clock()
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| H A D | clk-rcar-gen2.c | 140 static const char *parent_name = "pll0"; cpg_z_clk_register()
314 } else if (!strcmp(name, "pll0")) { rcar_gen2_cpg_register_clock()
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| /linux-4.4.14/arch/avr32/mach-at32ap/ |
| H A D | at32ap700x.c | 311 static struct clk pll0 = { variable in typeref:struct:clk
312 .name = "pll0",
326 * The main clock can be either osc0 or pll0. The boot loader may
574 else if (parent == &osc0 || parent == &pll0) genclk_set_parent()
579 if (parent == &pll0 || parent == &pll1) genclk_set_parent()
601 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0; genclk_init_parent()
1510 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0); at32_add_device_lcdc()
1511 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0)); at32_add_device_lcdc()
2200 &pll0,
2267 main_clock = &pll0; setup_platform()
2268 cpu_clk.parent = &pll0; setup_platform()
2275 pll0.parent = &osc1; setup_platform()
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| /linux-4.4.14/drivers/clk/berlin/ |
| H A D | berlin2-div.c | 34 * pll0 --------------->| 0 | +---+
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| /linux-4.4.14/drivers/clk/qcom/ |
| H A D | gcc-ipq806x.c | 35 static struct clk_pll pll0 = { variable in typeref:struct:clk_pll
44 .name = "pll0",
56 .parent_names = (const char *[]){ "pll0" },
2723 [PLL0] = &pll0.clkr,
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| /linux-4.4.14/arch/arm/mach-davinci/ |
| H A D | da830.c | 52 .name = "pll0",
378 CLK(NULL, "pll0", &pll0_clk),
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| H A D | da850.c | 67 .name = "pll0",
432 CLK(NULL, "pll0", &pll0_clk),
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| /linux-4.4.14/drivers/gpu/drm/i915/ |
| H A D | intel_ddi.c | 1166 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; bxt_calc_pll_link()
1739 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; bxt_ddi_pll_select()
2834 temp |= pll->config.hw_state.pll0; bxt_ddi_pll_enable()
2941 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); bxt_ddi_pll_get_hw_state()
2942 hw_state->pll0 &= PORT_PLL_M2_MASK; bxt_ddi_pll_get_hw_state()
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| H A D | i915_drv.h | 387 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, member in struct:intel_dpll_hw_state
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| H A D | intel_display.c | 12063 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " intel_dump_pipe_config()
12068 pipe_config->dpll_hw_state.pll0, intel_dump_pipe_config()
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