Searched refs:phb (Results 1 - 48 of 48) sorted by relevance

/linux-4.4.14/arch/powerpc/platforms/powernv/
H A Dpci-p5ioc2.c44 static int pnv_pci_p5ioc2_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, pnv_pci_p5ioc2_msi_setup() argument
50 msg->data = hwirq - phb->msi_base; pnv_pci_p5ioc2_msi_setup()
57 static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb) pnv_pci_init_p5ioc2_msis() argument
60 const __be32 *prop = of_get_property(phb->hose->dn, pnv_pci_init_p5ioc2_msis()
68 if (of_device_is_compatible(phb->hose->dn, "ibm,p5ioc2-pcix")) pnv_pci_init_p5ioc2_msis()
70 phb->msi_base = be32_to_cpup(prop); pnv_pci_init_p5ioc2_msis()
72 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { pnv_pci_init_p5ioc2_msis()
74 phb->hose->global_number); pnv_pci_init_p5ioc2_msis()
77 phb->msi_setup = pnv_pci_p5ioc2_msi_setup; pnv_pci_init_p5ioc2_msis()
78 phb->msi32_support = 0; pnv_pci_init_p5ioc2_msis()
80 count, phb->msi_base); pnv_pci_init_p5ioc2_msis()
83 static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb) { } pnv_pci_init_p5ioc2_msis() argument
95 static void pnv_pci_p5ioc2_dma_dev_setup(struct pnv_phb *phb, pnv_pci_p5ioc2_dma_dev_setup() argument
98 struct iommu_table *tbl = phb->p5ioc2.table_group.tables[0]; pnv_pci_p5ioc2_dma_dev_setup()
102 iommu_init_table(tbl, phb->hose->node); pnv_pci_p5ioc2_dma_dev_setup()
103 iommu_register_group(&phb->p5ioc2.table_group, pnv_pci_p5ioc2_dma_dev_setup()
104 pci_domain_nr(phb->hose->bus), phb->opal_id); pnv_pci_p5ioc2_dma_dev_setup()
106 pnv_pci_link_table_and_group(phb->hose->node, 0, pnv_pci_p5ioc2_dma_dev_setup()
107 tbl, &phb->p5ioc2.table_group); pnv_pci_p5ioc2_dma_dev_setup()
125 struct pnv_phb *phb; pnv_pci_init_p5ioc2_phb() local
151 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); pnv_pci_init_p5ioc2_phb()
152 phb->hose = pcibios_alloc_controller(np); pnv_pci_init_p5ioc2_phb()
153 if (!phb->hose) { pnv_pci_init_p5ioc2_phb()
158 spin_lock_init(&phb->lock); pnv_pci_init_p5ioc2_phb()
159 phb->hose->first_busno = 0; pnv_pci_init_p5ioc2_phb()
160 phb->hose->last_busno = 0xff; pnv_pci_init_p5ioc2_phb()
161 phb->hose->private_data = phb; pnv_pci_init_p5ioc2_phb()
162 phb->hose->controller_ops = pnv_pci_p5ioc2_controller_ops; pnv_pci_init_p5ioc2_phb()
163 phb->hub_id = hub_id; pnv_pci_init_p5ioc2_phb()
164 phb->opal_id = phb_id; pnv_pci_init_p5ioc2_phb()
165 phb->type = PNV_PHB_P5IOC2; pnv_pci_init_p5ioc2_phb()
166 phb->model = PNV_PHB_MODEL_P5IOC2; pnv_pci_init_p5ioc2_phb()
168 phb->regs = of_iomap(np, 0); pnv_pci_init_p5ioc2_phb()
170 if (phb->regs == NULL) pnv_pci_init_p5ioc2_phb()
173 pr_devel(" P_BUID = 0x%08x\n", in_be32(phb->regs + 0x100)); pnv_pci_init_p5ioc2_phb()
174 pr_devel(" P_IOSZ = 0x%08x\n", in_be32(phb->regs + 0x1b0)); pnv_pci_init_p5ioc2_phb()
175 pr_devel(" P_IO_ST = 0x%08x\n", in_be32(phb->regs + 0x1e0)); pnv_pci_init_p5ioc2_phb()
176 pr_devel(" P_MEM1_H = 0x%08x\n", in_be32(phb->regs + 0x1a0)); pnv_pci_init_p5ioc2_phb()
177 pr_devel(" P_MEM1_L = 0x%08x\n", in_be32(phb->regs + 0x190)); pnv_pci_init_p5ioc2_phb()
178 pr_devel(" P_MSZ1_L = 0x%08x\n", in_be32(phb->regs + 0x1c0)); pnv_pci_init_p5ioc2_phb()
179 pr_devel(" P_MEM_ST = 0x%08x\n", in_be32(phb->regs + 0x1d0)); pnv_pci_init_p5ioc2_phb()
180 pr_devel(" P_MEM2_H = 0x%08x\n", in_be32(phb->regs + 0x2c0)); pnv_pci_init_p5ioc2_phb()
181 pr_devel(" P_MEM2_L = 0x%08x\n", in_be32(phb->regs + 0x2b0)); pnv_pci_init_p5ioc2_phb()
182 pr_devel(" P_MSZ2_H = 0x%08x\n", in_be32(phb->regs + 0x2d0)); pnv_pci_init_p5ioc2_phb()
183 pr_devel(" P_MSZ2_L = 0x%08x\n", in_be32(phb->regs + 0x2e0)); pnv_pci_init_p5ioc2_phb()
188 pci_process_bridge_OF_ranges(phb->hose, np, primary); pnv_pci_init_p5ioc2_phb()
191 phb->hose->ops = &pnv_pci_ops; pnv_pci_init_p5ioc2_phb()
194 pnv_pci_init_p5ioc2_msis(phb); pnv_pci_init_p5ioc2_phb()
197 phb->dma_dev_setup = pnv_pci_p5ioc2_dma_dev_setup; pnv_pci_init_p5ioc2_phb()
198 pnv_pci_setup_iommu_table(&phb->p5ioc2.iommu_table, pnv_pci_init_p5ioc2_phb()
204 * should not be called for phb->p5ioc2.table_group.tables[0] ever. pnv_pci_init_p5ioc2_phb()
206 tbl = phb->p5ioc2.table_group.tables[0] = &phb->p5ioc2.iommu_table; pnv_pci_init_p5ioc2_phb()
207 table_group = &phb->p5ioc2.table_group; pnv_pci_init_p5ioc2_phb()
H A Dpci-ioda.c135 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) pnv_ioda_reserve_pe() argument
137 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) { pnv_ioda_reserve_pe()
139 __func__, pe_no, phb->hose->global_number); pnv_ioda_reserve_pe()
143 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) pnv_ioda_reserve_pe()
145 __func__, pe_no, phb->hose->global_number); pnv_ioda_reserve_pe()
147 phb->ioda.pe_array[pe_no].phb = phb; pnv_ioda_reserve_pe()
148 phb->ioda.pe_array[pe_no].pe_number = pe_no; pnv_ioda_reserve_pe()
151 static int pnv_ioda_alloc_pe(struct pnv_phb *phb) pnv_ioda_alloc_pe() argument
156 pe = find_next_zero_bit(phb->ioda.pe_alloc, pnv_ioda_alloc_pe()
157 phb->ioda.total_pe, 0); pnv_ioda_alloc_pe()
158 if (pe >= phb->ioda.total_pe) pnv_ioda_alloc_pe()
160 } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); pnv_ioda_alloc_pe()
162 phb->ioda.pe_array[pe].phb = phb; pnv_ioda_alloc_pe()
163 phb->ioda.pe_array[pe].pe_number = pe; pnv_ioda_alloc_pe()
167 static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) pnv_ioda_free_pe() argument
169 WARN_ON(phb->ioda.pe_array[pe].pdev); pnv_ioda_free_pe()
171 memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); pnv_ioda_free_pe()
172 clear_bit(pe, phb->ioda.pe_alloc); pnv_ioda_free_pe()
176 static int pnv_ioda2_init_m64(struct pnv_phb *phb) pnv_ioda2_init_m64() argument
183 rc = opal_pci_set_phb_mem_window(phb->opal_id, pnv_ioda2_init_m64()
185 phb->ioda.m64_bar_idx, pnv_ioda2_init_m64()
186 phb->ioda.m64_base, pnv_ioda2_init_m64()
188 phb->ioda.m64_size); pnv_ioda2_init_m64()
195 rc = opal_pci_phb_mmio_enable(phb->opal_id, pnv_ioda2_init_m64()
197 phb->ioda.m64_bar_idx, pnv_ioda2_init_m64()
205 set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); pnv_ioda2_init_m64()
211 r = &phb->hose->mem_resources[1]; pnv_ioda2_init_m64()
212 if (phb->ioda.reserved_pe == 0) pnv_ioda2_init_m64()
213 r->start += phb->ioda.m64_segsize; pnv_ioda2_init_m64()
214 else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1)) pnv_ioda2_init_m64()
215 r->end -= phb->ioda.m64_segsize; pnv_ioda2_init_m64()
218 phb->ioda.reserved_pe); pnv_ioda2_init_m64()
224 rc, desc, phb->ioda.m64_bar_idx); pnv_ioda2_init_m64()
225 opal_pci_phb_mmio_enable(phb->opal_id, pnv_ioda2_init_m64()
227 phb->ioda.m64_bar_idx, pnv_ioda2_init_m64()
236 struct pnv_phb *phb = hose->private_data; pnv_ioda2_reserve_dev_m64_pe() local
241 base = phb->ioda.m64_base; pnv_ioda2_reserve_dev_m64_pe()
242 sgsz = phb->ioda.m64_segsize; pnv_ioda2_reserve_dev_m64_pe()
254 pnv_ioda_reserve_pe(phb, segno); pnv_ioda2_reserve_dev_m64_pe()
277 struct pnv_phb *phb = hose->private_data; pnv_ioda2_pick_m64_pe() local
287 size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); pnv_ioda2_pick_m64_pe()
303 if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) { pnv_ioda2_pick_m64_pe()
314 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) < pnv_ioda2_pick_m64_pe()
315 phb->ioda.total_pe) { pnv_ioda2_pick_m64_pe()
316 pe = &phb->ioda.pe_array[i]; pnv_ioda2_pick_m64_pe()
333 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) pnv_ioda_parse_m64_window() argument
335 struct pci_controller *hose = phb->hose; pnv_ioda_parse_m64_window()
342 if (phb->type != PNV_PHB_IODA2) { pnv_ioda_parse_m64_window()
366 phb->ioda.m64_size = resource_size(res); pnv_ioda_parse_m64_window()
367 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe; pnv_ioda_parse_m64_window()
368 phb->ioda.m64_base = pci_addr; pnv_ioda_parse_m64_window()
374 phb->ioda.m64_bar_idx = 15; pnv_ioda_parse_m64_window()
375 phb->init_m64 = pnv_ioda2_init_m64; pnv_ioda_parse_m64_window()
376 phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe; pnv_ioda_parse_m64_window()
377 phb->pick_m64_pe = pnv_ioda2_pick_m64_pe; pnv_ioda_parse_m64_window()
380 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) pnv_ioda_freeze_pe() argument
382 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; pnv_ioda_freeze_pe()
396 rc = opal_pci_eeh_freeze_set(phb->opal_id, pnv_ioda_freeze_pe()
401 __func__, rc, phb->hose->global_number, pe_no); pnv_ioda_freeze_pe()
410 rc = opal_pci_eeh_freeze_set(phb->opal_id, pnv_ioda_freeze_pe()
415 __func__, rc, phb->hose->global_number, pnv_ioda_freeze_pe()
420 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) pnv_ioda_unfreeze_pe() argument
426 pe = &phb->ioda.pe_array[pe_no]; pnv_ioda_unfreeze_pe()
434 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); pnv_ioda_unfreeze_pe()
437 __func__, rc, opt, phb->hose->global_number, pe_no); pnv_ioda_unfreeze_pe()
446 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pnv_ioda_unfreeze_pe()
451 __func__, rc, opt, phb->hose->global_number, pnv_ioda_unfreeze_pe()
460 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) pnv_ioda_get_pe_state() argument
468 if (pe_no < 0 || pe_no >= phb->ioda.total_pe) pnv_ioda_get_pe_state()
475 pe = &phb->ioda.pe_array[pe_no]; pnv_ioda_get_pe_state()
483 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, pnv_ioda_get_pe_state()
489 phb->hose->global_number, pe_no); pnv_ioda_get_pe_state()
498 rc = opal_pci_eeh_freeze_status(phb->opal_id, pnv_ioda_get_pe_state()
507 phb->hose->global_number, slave->pe_number); pnv_ioda_get_pe_state()
529 struct pnv_phb *phb = hose->private_data; pnv_ioda_get_pe() local
536 return &phb->ioda.pe_array[pdn->pe_number]; pnv_ioda_get_pe()
540 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, pnv_ioda_set_one_peltv() argument
552 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, pnv_ioda_set_one_peltv()
565 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, pnv_ioda_set_one_peltv()
577 static int pnv_ioda_set_peltv(struct pnv_phb *phb, pnv_ioda_set_peltv() argument
590 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, pnv_ioda_set_peltv()
594 opal_pci_eeh_freeze_clear(phb->opal_id, pnv_ioda_set_peltv()
606 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); pnv_ioda_set_peltv()
613 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); pnv_ioda_set_peltv()
632 parent = &phb->ioda.pe_array[pdn->pe_number]; pnv_ioda_set_peltv()
633 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); pnv_ioda_set_peltv()
645 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) pnv_ioda_deconfigure_pe() argument
691 phb->ioda.pe_rmap[rid] = 0; pnv_ioda_deconfigure_pe()
697 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, pnv_ioda_deconfigure_pe()
704 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, pnv_ioda_deconfigure_pe()
708 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, pnv_ioda_deconfigure_pe()
712 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, pnv_ioda_deconfigure_pe()
725 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) pnv_ioda_configure_pe() argument
776 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, pnv_ioda_configure_pe()
784 pnv_ioda_set_peltv(phb, pe, true); pnv_ioda_configure_pe()
788 phb->ioda.pe_rmap[rid] = pe->pe_number; pnv_ioda_configure_pe()
791 if (phb->type != PNV_PHB_IODA1) { pnv_ioda_configure_pe()
797 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); pnv_ioda_configure_pe()
803 rc = opal_pci_set_mve_enable(phb->opal_id, pnv_ioda_configure_pe()
816 static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, pnv_ioda_link_pe_by_weight() argument
821 list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { pnv_ioda_link_pe_by_weight()
827 list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); pnv_ioda_link_pe_by_weight()
931 struct pnv_phb *phb = hose->private_data;
948 pe_num = pnv_ioda_alloc_pe(phb);
962 pe = &phb->ioda.pe_array[pe_num];
974 if (pnv_ioda_configure_pe(phb, pe)) {
977 pnv_ioda_free_pe(phb, pe_num);
987 phb->ioda.dma_weight += pe->dma_weight;
988 phb->ioda.dma_pe_count++;
992 pnv_ioda_link_pe_by_weight(phb, pe);
1026 struct pnv_phb *phb = hose->private_data; pnv_ioda_setup_bus_PE() local
1031 if (phb->pick_m64_pe) pnv_ioda_setup_bus_PE()
1032 pe_num = phb->pick_m64_pe(bus, all); pnv_ioda_setup_bus_PE()
1036 pe_num = pnv_ioda_alloc_pe(phb); pnv_ioda_setup_bus_PE()
1044 pe = &phb->ioda.pe_array[pe_num]; pnv_ioda_setup_bus_PE()
1060 if (pnv_ioda_configure_pe(phb, pe)) { pnv_ioda_setup_bus_PE()
1063 pnv_ioda_free_pe(phb, pe_num); pnv_ioda_setup_bus_PE()
1072 list_add_tail(&pe->list, &phb->ioda.pe_list); pnv_ioda_setup_bus_PE()
1078 phb->ioda.dma_weight += pe->dma_weight; pnv_ioda_setup_bus_PE()
1079 phb->ioda.dma_pe_count++; pnv_ioda_setup_bus_PE()
1083 pnv_ioda_link_pe_by_weight(phb, pe); pnv_ioda_setup_bus_PE()
1113 struct pnv_phb *phb; pnv_pci_ioda_setup_PEs() local
1116 phb = hose->private_data; pnv_pci_ioda_setup_PEs()
1119 if (phb->reserve_m64_pe) pnv_pci_ioda_setup_PEs()
1120 phb->reserve_m64_pe(hose->bus, NULL, true); pnv_pci_ioda_setup_PEs()
1131 struct pnv_phb *phb; pnv_pci_vf_release_m64() local
1137 phb = hose->private_data; pnv_pci_vf_release_m64()
1144 opal_pci_phb_mmio_enable(phb->opal_id, pnv_pci_vf_release_m64()
1146 clear_bit(pdn->m64_wins[i][j], &phb->ioda.m64_bar_alloc); pnv_pci_vf_release_m64()
1157 struct pnv_phb *phb; pnv_pci_vf_assign_m64() local
1171 phb = hose->private_data; pnv_pci_vf_assign_m64()
1199 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, pnv_pci_vf_assign_m64()
1200 phb->ioda.m64_bar_idx + 1, 0); pnv_pci_vf_assign_m64()
1202 if (win >= phb->ioda.m64_bar_idx + 1) pnv_pci_vf_assign_m64()
1204 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); pnv_pci_vf_assign_m64()
1221 rc = opal_pci_map_pe_mmio_window(phb->opal_id, pnv_pci_vf_assign_m64()
1226 rc = opal_pci_set_phb_mem_window(phb->opal_id, pnv_pci_vf_assign_m64()
1241 rc = opal_pci_phb_mmio_enable(phb->opal_id, pnv_pci_vf_assign_m64()
1244 rc = opal_pci_phb_mmio_enable(phb->opal_id, pnv_pci_vf_assign_m64()
1288 struct pnv_phb *phb; pnv_ioda_release_vf_PE() local
1296 phb = hose->private_data; pnv_ioda_release_vf_PE()
1319 rc = opal_pci_set_peltv(phb->opal_id, pnv_ioda_release_vf_PE()
1331 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { pnv_ioda_release_vf_PE()
1338 mutex_lock(&phb->ioda.pe_list_mutex); pnv_ioda_release_vf_PE()
1340 mutex_unlock(&phb->ioda.pe_list_mutex); pnv_ioda_release_vf_PE()
1342 pnv_ioda_deconfigure_pe(phb, pe); pnv_ioda_release_vf_PE()
1344 pnv_ioda_free_pe(phb, pe->pe_number); pnv_ioda_release_vf_PE()
1352 struct pnv_phb *phb; pnv_pci_sriov_disable() local
1359 phb = hose->private_data; pnv_pci_sriov_disable()
1367 if (phb->type == PNV_PHB_IODA2) { pnv_pci_sriov_disable()
1375 bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs); pnv_pci_sriov_disable()
1380 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1386 struct pnv_phb *phb; pnv_ioda_setup_vf_PE() local
1395 phb = hose->private_data; pnv_ioda_setup_vf_PE()
1405 pe = &phb->ioda.pe_array[pe_num]; pnv_ioda_setup_vf_PE()
1407 pe->phb = phb; pnv_ioda_setup_vf_PE()
1421 if (pnv_ioda_configure_pe(phb, pe)) { pnv_ioda_setup_vf_PE()
1424 pnv_ioda_free_pe(phb, pe_num); pnv_ioda_setup_vf_PE()
1430 mutex_lock(&phb->ioda.pe_list_mutex); pnv_ioda_setup_vf_PE()
1431 list_add_tail(&pe->list, &phb->ioda.pe_list); pnv_ioda_setup_vf_PE()
1432 mutex_unlock(&phb->ioda.pe_list_mutex); pnv_ioda_setup_vf_PE()
1434 pnv_pci_ioda2_setup_dma_pe(phb, pe); pnv_ioda_setup_vf_PE()
1454 rc = opal_pci_set_peltv(phb->opal_id, pnv_ioda_setup_vf_PE()
1473 struct pnv_phb *phb; pnv_pci_sriov_enable() local
1479 phb = hose->private_data; pnv_pci_sriov_enable()
1482 if (phb->type == PNV_PHB_IODA2) { pnv_pci_sriov_enable()
1484 mutex_lock(&phb->ioda.pe_alloc_mutex); pnv_pci_sriov_enable()
1486 phb->ioda.pe_alloc, phb->ioda.total_pe, pnv_pci_sriov_enable()
1488 if (pdn->offset >= phb->ioda.total_pe) { pnv_pci_sriov_enable()
1489 mutex_unlock(&phb->ioda.pe_alloc_mutex); pnv_pci_sriov_enable()
1494 bitmap_set(phb->ioda.pe_alloc, pdn->offset, num_vfs); pnv_pci_sriov_enable()
1496 mutex_unlock(&phb->ioda.pe_alloc_mutex); pnv_pci_sriov_enable()
1523 bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs); pnv_pci_sriov_enable()
1548 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) pnv_pci_ioda_dma_dev_setup() argument
1561 pe = &phb->ioda.pe_array[pdn->pe_number]; pnv_pci_ioda_dma_dev_setup()
1576 struct pnv_phb *phb = hose->private_data; pnv_pci_ioda_dma_set_mask() local
1585 pe = &phb->ioda.pe_array[pdn->pe_number]; pnv_pci_ioda_dma_set_mask()
1605 struct pnv_phb *phb = hose->private_data; pnv_pci_ioda_dma_get_required_mask() local
1613 pe = &phb->ioda.pe_array[pdn->pe_number]; pnv_pci_ioda_dma_get_required_mask()
1649 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : pnv_pci_ioda1_tce_invalidate()
1650 pe->phb->ioda.tce_inval_reg; pnv_pci_ioda1_tce_invalidate()
1742 struct pnv_phb *phb = pe->phb; pnv_pci_ioda2_tce_invalidate_entire() local
1744 if (!phb->ioda.tce_inval_reg) pnv_pci_ioda2_tce_invalidate_entire()
1748 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); pnv_pci_ioda2_tce_invalidate_entire()
1786 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : pnv_pci_ioda2_tce_invalidate()
1787 pe->phb->ioda.tce_inval_reg; pnv_pci_ioda2_tce_invalidate()
1848 static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, pnv_pci_ioda_setup_dma_pe() argument
1867 tbl = pnv_pci_table_alloc(phb->hose->node); pnv_pci_ioda_setup_dma_pe()
1868 iommu_register_group(&pe->table_group, phb->hose->global_number, pnv_pci_ioda_setup_dma_pe()
1870 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); pnv_pci_ioda_setup_dma_pe()
1882 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, pnv_pci_ioda_setup_dma_pe()
1893 rc = opal_pci_map_pe_dma_window(phb->opal_id, pnv_pci_ioda_setup_dma_pe()
1910 if (phb->ioda.tce_inval_reg) pnv_pci_ioda_setup_dma_pe()
1918 iommu_init_table(tbl, phb->hose->node); pnv_pci_ioda_setup_dma_pe()
1949 struct pnv_phb *phb = pe->phb; pnv_pci_ioda2_set_window() local
1964 rc = opal_pci_map_pe_dma_window(phb->opal_id, pnv_pci_ioda2_set_window()
1976 pnv_pci_link_table_and_group(phb->hose->node, num, pnv_pci_ioda2_set_window()
1993 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, pnv_pci_ioda2_set_bypass()
1999 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, pnv_pci_ioda2_set_bypass()
2021 int nid = pe->phb->hose->node; pnv_pci_ioda2_create_table()
2039 if (pe->phb->ioda.tce_inval_reg) pnv_pci_ioda2_create_table()
2076 iommu_init_table(tbl, pe->phb->hose->node); pnv_pci_ioda2_setup_default_config()
2090 if (pe->phb->ioda.tce_inval_reg) pnv_pci_ioda2_setup_default_config()
2110 struct pnv_phb *phb = pe->phb; pnv_pci_ioda2_unset_window() local
2115 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, pnv_pci_ioda2_unset_window()
2193 static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb) pnv_pci_ioda_setup_opal_tce_kill() argument
2198 swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); pnv_pci_ioda_setup_opal_tce_kill()
2202 phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp); pnv_pci_ioda_setup_opal_tce_kill()
2203 phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8); pnv_pci_ioda_setup_opal_tce_kill()
2341 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, pnv_pci_ioda2_setup_dma_pe() argument
2353 iommu_register_group(&pe->table_group, phb->hose->global_number, pnv_pci_ioda2_setup_dma_pe()
2359 phb->ioda.m32_pci_base); pnv_pci_ioda2_setup_dma_pe()
2363 pe->table_group.tce32_size = phb->ioda.m32_pci_base; pnv_pci_ioda2_setup_dma_pe()
2385 static void pnv_ioda_setup_dma(struct pnv_phb *phb) pnv_ioda_setup_dma() argument
2387 struct pci_controller *hose = phb->hose; pnv_ioda_setup_dma()
2396 if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) pnv_ioda_setup_dma()
2399 residual = phb->ioda.tce32_count - pnv_ioda_setup_dma()
2400 phb->ioda.dma_pe_count; pnv_ioda_setup_dma()
2403 hose->global_number, phb->ioda.tce32_count); pnv_ioda_setup_dma()
2405 phb->ioda.dma_pe_count, phb->ioda.dma_weight); pnv_ioda_setup_dma()
2407 pnv_pci_ioda_setup_opal_tce_kill(phb); pnv_ioda_setup_dma()
2413 remaining = phb->ioda.tce32_count; pnv_ioda_setup_dma()
2414 tw = phb->ioda.dma_weight; pnv_ioda_setup_dma()
2416 list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { pnv_ioda_setup_dma()
2435 if (phb->type == PNV_PHB_IODA1) { pnv_ioda_setup_dma()
2438 pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); pnv_ioda_setup_dma()
2442 pnv_pci_ioda2_setup_dma_pe(phb, pe); pnv_ioda_setup_dma()
2455 struct pnv_phb *phb = container_of(chip, struct pnv_phb, pnv_ioda2_msi_eoi() local
2459 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); pnv_ioda2_msi_eoi()
2466 static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) set_msi_irq_chip() argument
2471 if (phb->type != PNV_PHB_IODA2) set_msi_irq_chip()
2474 if (!phb->ioda.irq_chip_init) { set_msi_irq_chip()
2481 phb->ioda.irq_chip_init = 1; set_msi_irq_chip()
2482 phb->ioda.irq_chip = *ichip; set_msi_irq_chip()
2483 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; set_msi_irq_chip()
2485 irq_set_chip(virq, &phb->ioda.irq_chip); set_msi_irq_chip()
2501 struct pnv_phb *phb = hose->private_data; pnv_phb_to_cxl_mode() local
2511 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); pnv_phb_to_cxl_mode()
2525 struct pnv_phb *phb = hose->private_data; pnv_cxl_alloc_hwirqs() local
2526 int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); pnv_cxl_alloc_hwirqs()
2533 return phb->msi_base + hwirq; pnv_cxl_alloc_hwirqs()
2540 struct pnv_phb *phb = hose->private_data; pnv_cxl_release_hwirqs() local
2542 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); pnv_cxl_release_hwirqs()
2550 struct pnv_phb *phb = hose->private_data; pnv_cxl_release_hwirq_ranges() local
2559 hwirq = irqs->offset[i] - phb->msi_base; pnv_cxl_release_hwirq_ranges()
2560 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, pnv_cxl_release_hwirq_ranges()
2570 struct pnv_phb *phb = hose->private_data; pnv_cxl_alloc_hwirq_ranges() local
2579 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); pnv_cxl_alloc_hwirq_ranges()
2587 irqs->offset[i] = phb->msi_base + hwirq; pnv_cxl_alloc_hwirq_ranges()
2606 struct pnv_phb *phb = hose->private_data; pnv_cxl_get_irq_count() local
2608 return phb->msi_bmp.irq_count; pnv_cxl_get_irq_count()
2616 struct pnv_phb *phb = hose->private_data; pnv_cxl_ioda_msi_setup() local
2617 unsigned int xive_num = hwirq - phb->msi_base; pnv_cxl_ioda_msi_setup()
2625 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); pnv_cxl_ioda_msi_setup()
2629 pci_name(dev), rc, phb->msi_base, hwirq, xive_num); pnv_cxl_ioda_msi_setup()
2632 set_msi_irq_chip(phb, virq); pnv_cxl_ioda_msi_setup()
2639 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, pnv_pci_ioda_msi_setup() argument
2644 unsigned int xive_num = hwirq - phb->msi_base; pnv_pci_ioda_msi_setup()
2661 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); pnv_pci_ioda_msi_setup()
2671 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, pnv_pci_ioda_msi_setup()
2683 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, pnv_pci_ioda_msi_setup()
2695 set_msi_irq_chip(phb, virq); pnv_pci_ioda_msi_setup()
2705 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) pnv_pci_init_ioda_msis() argument
2708 const __be32 *prop = of_get_property(phb->hose->dn, pnv_pci_init_ioda_msis()
2712 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); pnv_pci_init_ioda_msis()
2717 phb->msi_base = be32_to_cpup(prop); pnv_pci_init_ioda_msis()
2719 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { pnv_pci_init_ioda_msis()
2721 phb->hose->global_number); pnv_pci_init_ioda_msis()
2725 phb->msi_setup = pnv_pci_ioda_msi_setup; pnv_pci_init_ioda_msis()
2726 phb->msi32_support = 1; pnv_pci_init_ioda_msis()
2728 count, phb->msi_base); pnv_pci_init_ioda_msis()
2731 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } pnv_pci_init_ioda_msis() argument
2738 struct pnv_phb *phb; pnv_pci_ioda_fixup_iov_resources() local
2749 phb = hose->private_data; pnv_pci_ioda_fixup_iov_resources()
2756 mul = phb->ioda.total_pe; pnv_pci_ioda_fixup_iov_resources()
2809 struct pnv_phb *phb = hose->private_data; pnv_ioda_setup_pe_seg() local
2828 region.start = res->start - phb->ioda.io_pci_base; pnv_ioda_setup_pe_seg()
2829 region.end = res->end - phb->ioda.io_pci_base; pnv_ioda_setup_pe_seg()
2830 index = region.start / phb->ioda.io_segsize; pnv_ioda_setup_pe_seg()
2832 while (index < phb->ioda.total_pe && pnv_ioda_setup_pe_seg()
2834 phb->ioda.io_segmap[index] = pe->pe_number; pnv_ioda_setup_pe_seg()
2835 rc = opal_pci_map_pe_mmio_window(phb->opal_id, pnv_ioda_setup_pe_seg()
2844 region.start += phb->ioda.io_segsize; pnv_ioda_setup_pe_seg()
2851 phb->ioda.m32_pci_base; pnv_ioda_setup_pe_seg()
2854 phb->ioda.m32_pci_base; pnv_ioda_setup_pe_seg()
2855 index = region.start / phb->ioda.m32_segsize; pnv_ioda_setup_pe_seg()
2857 while (index < phb->ioda.total_pe && pnv_ioda_setup_pe_seg()
2859 phb->ioda.m32_segmap[index] = pe->pe_number; pnv_ioda_setup_pe_seg()
2860 rc = opal_pci_map_pe_mmio_window(phb->opal_id, pnv_ioda_setup_pe_seg()
2869 region.start += phb->ioda.m32_segsize; pnv_ioda_setup_pe_seg()
2879 struct pnv_phb *phb; pnv_pci_ioda_setup_seg() local
2883 phb = hose->private_data; pnv_pci_ioda_setup_seg()
2884 list_for_each_entry(pe, &phb->ioda.pe_list, list) { pnv_pci_ioda_setup_seg()
2893 struct pnv_phb *phb; pnv_pci_ioda_setup_DMA() local
2899 phb = hose->private_data; pnv_pci_ioda_setup_DMA()
2900 phb->initialized = 1; pnv_pci_ioda_setup_DMA()
2908 struct pnv_phb *phb; pnv_pci_ioda_create_dbgfs() local
2912 phb = hose->private_data; pnv_pci_ioda_create_dbgfs()
2915 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); pnv_pci_ioda_create_dbgfs()
2916 if (!phb->dbgfs) pnv_pci_ioda_create_dbgfs()
2954 struct pnv_phb *phb = hose->private_data; pnv_pci_window_alignment() local
2969 if (phb->ioda.m64_segsize && pnv_pci_window_alignment()
2971 return phb->ioda.m64_segsize; pnv_pci_window_alignment()
2973 return phb->ioda.m32_segsize; pnv_pci_window_alignment()
2975 return phb->ioda.io_segsize; pnv_pci_window_alignment()
3003 struct pnv_phb *phb = hose->private_data; pnv_pci_enable_device_hook() local
3011 if (!phb->initialized) pnv_pci_enable_device_hook()
3021 static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, pnv_ioda_bdfn_to_pe() argument
3024 return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; pnv_ioda_bdfn_to_pe()
3029 struct pnv_phb *phb = hose->private_data; pnv_pci_ioda_shutdown() local
3031 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, pnv_pci_ioda_shutdown()
3054 struct pnv_phb *phb; pnv_pci_init_ioda_phb() local
3073 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); pnv_pci_init_ioda_phb()
3076 phb->hose = hose = pcibios_alloc_controller(np); pnv_pci_init_ioda_phb()
3077 if (!phb->hose) { pnv_pci_init_ioda_phb()
3080 memblock_free(__pa(phb), sizeof(struct pnv_phb)); pnv_pci_init_ioda_phb()
3084 spin_lock_init(&phb->lock); pnv_pci_init_ioda_phb()
3094 hose->private_data = phb; pnv_pci_init_ioda_phb()
3095 phb->hub_id = hub_id; pnv_pci_init_ioda_phb()
3096 phb->opal_id = phb_id; pnv_pci_init_ioda_phb()
3097 phb->type = ioda_type; pnv_pci_init_ioda_phb()
3098 mutex_init(&phb->ioda.pe_alloc_mutex); pnv_pci_init_ioda_phb()
3102 phb->model = PNV_PHB_MODEL_P7IOC; pnv_pci_init_ioda_phb()
3104 phb->model = PNV_PHB_MODEL_PHB3; pnv_pci_init_ioda_phb()
3106 phb->model = PNV_PHB_MODEL_UNKNOWN; pnv_pci_init_ioda_phb()
3112 phb->regs = of_iomap(np, 0); pnv_pci_init_ioda_phb()
3113 if (phb->regs == NULL) pnv_pci_init_ioda_phb()
3117 phb->ioda.total_pe = 1; pnv_pci_init_ioda_phb()
3120 phb->ioda.total_pe = be32_to_cpup(prop32); pnv_pci_init_ioda_phb()
3123 phb->ioda.reserved_pe = be32_to_cpup(prop32); pnv_pci_init_ioda_phb()
3126 pnv_ioda_parse_m64_window(phb); pnv_pci_init_ioda_phb()
3128 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); pnv_pci_init_ioda_phb()
3130 phb->ioda.m32_size += 0x10000; pnv_pci_init_ioda_phb()
3132 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; pnv_pci_init_ioda_phb()
3133 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; pnv_pci_init_ioda_phb()
3134 phb->ioda.io_size = hose->pci_io_size; pnv_pci_init_ioda_phb()
3135 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; pnv_pci_init_ioda_phb()
3136 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ pnv_pci_init_ioda_phb()
3139 size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); pnv_pci_init_ioda_phb()
3141 size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); pnv_pci_init_ioda_phb()
3142 if (phb->type == PNV_PHB_IODA1) { pnv_pci_init_ioda_phb()
3144 size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); pnv_pci_init_ioda_phb()
3147 size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); pnv_pci_init_ioda_phb()
3149 phb->ioda.pe_alloc = aux; pnv_pci_init_ioda_phb()
3150 phb->ioda.m32_segmap = aux + m32map_off; pnv_pci_init_ioda_phb()
3151 if (phb->type == PNV_PHB_IODA1) pnv_pci_init_ioda_phb()
3152 phb->ioda.io_segmap = aux + iomap_off; pnv_pci_init_ioda_phb()
3153 phb->ioda.pe_array = aux + pemap_off; pnv_pci_init_ioda_phb()
3154 set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc); pnv_pci_init_ioda_phb()
3156 INIT_LIST_HEAD(&phb->ioda.pe_dma_list); pnv_pci_init_ioda_phb()
3157 INIT_LIST_HEAD(&phb->ioda.pe_list); pnv_pci_init_ioda_phb()
3158 mutex_init(&phb->ioda.pe_list_mutex); pnv_pci_init_ioda_phb()
3161 phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; pnv_pci_init_ioda_phb()
3173 phb->ioda.total_pe, phb->ioda.reserved_pe, pnv_pci_init_ioda_phb()
3174 phb->ioda.m32_size, phb->ioda.m32_segsize); pnv_pci_init_ioda_phb()
3175 if (phb->ioda.m64_size) pnv_pci_init_ioda_phb()
3177 phb->ioda.m64_size, phb->ioda.m64_segsize); pnv_pci_init_ioda_phb()
3178 if (phb->ioda.io_size) pnv_pci_init_ioda_phb()
3180 phb->ioda.io_size, phb->ioda.io_segsize); pnv_pci_init_ioda_phb()
3183 phb->hose->ops = &pnv_pci_ops; pnv_pci_init_ioda_phb()
3184 phb->get_pe_state = pnv_ioda_get_pe_state; pnv_pci_init_ioda_phb()
3185 phb->freeze_pe = pnv_ioda_freeze_pe; pnv_pci_init_ioda_phb()
3186 phb->unfreeze_pe = pnv_ioda_unfreeze_pe; pnv_pci_init_ioda_phb()
3189 phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; pnv_pci_init_ioda_phb()
3192 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; pnv_pci_init_ioda_phb()
3195 pnv_pci_init_ioda_msis(phb); pnv_pci_init_ioda_phb()
3231 if (!phb->init_m64 || phb->init_m64(phb)) pnv_pci_init_ioda_phb()
3259 if (of_device_is_compatible(phbn, "ibm,ioda-phb")) for_each_child_of_node()
H A Dpci.c51 struct pnv_phb *phb = hose->private_data; pnv_setup_msi_irqs() local
58 if (WARN_ON(!phb) || !phb->msi_bmp.bitmap) pnv_setup_msi_irqs()
61 if (pdev->no_64bit_msi && !phb->msi32_support) pnv_setup_msi_irqs()
65 if (!entry->msi_attrib.is_64 && !phb->msi32_support) { for_each_pci_msi_entry()
70 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1); for_each_pci_msi_entry()
76 virq = irq_create_mapping(NULL, phb->msi_base + hwirq); for_each_pci_msi_entry()
80 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); for_each_pci_msi_entry()
83 rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq, for_each_pci_msi_entry()
88 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); for_each_pci_msi_entry()
100 struct pnv_phb *phb = hose->private_data; pnv_teardown_msi_irqs() local
104 if (WARN_ON(!phb)) pnv_teardown_msi_irqs()
113 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, 1); for_each_pci_msi_entry()
328 static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no) pnv_pci_handle_eeh_config() argument
333 spin_lock_irqsave(&phb->lock, flags); pnv_pci_handle_eeh_config()
336 rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob, pnv_pci_handle_eeh_config()
341 if (phb->unfreeze_pe) { pnv_pci_handle_eeh_config()
342 ret = phb->unfreeze_pe(phb, pnv_pci_handle_eeh_config()
346 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pnv_pci_handle_eeh_config()
352 __func__, rc, phb->hose->global_number, pnv_pci_handle_eeh_config()
365 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob); pnv_pci_handle_eeh_config()
367 spin_unlock_irqrestore(&phb->lock, flags); pnv_pci_handle_eeh_config()
372 struct pnv_phb *phb = pdn->phb->private_data; pnv_pci_config_check_eeh() local
385 if (phb->type == PNV_PHB_P5IOC2) pnv_pci_config_check_eeh()
388 pe_no = phb->ioda.reserved_pe; pnv_pci_config_check_eeh()
395 if (phb->get_pe_state) { pnv_pci_config_check_eeh()
396 fstate = phb->get_pe_state(phb, pe_no); pnv_pci_config_check_eeh()
398 rc = opal_pci_eeh_freeze_status(phb->opal_id, pnv_pci_config_check_eeh()
405 __func__, rc, phb->hose->global_number, pe_no); pnv_pci_config_check_eeh()
421 if (phb->freeze_pe) pnv_pci_config_check_eeh()
422 phb->freeze_pe(phb, pe_no); pnv_pci_config_check_eeh()
424 pnv_pci_handle_eeh_config(phb, pe_no); pnv_pci_config_check_eeh()
431 struct pnv_phb *phb = pdn->phb->private_data; pnv_pci_cfg_read() local
438 rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8); pnv_pci_cfg_read()
444 rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where, pnv_pci_cfg_read()
451 rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32); pnv_pci_cfg_read()
467 struct pnv_phb *phb = pdn->phb->private_data; pnv_pci_cfg_write() local
474 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val); pnv_pci_cfg_write()
477 opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val); pnv_pci_cfg_write()
480 opal_pci_config_write_word(phb->opal_id, bdfn, where, val); pnv_pci_cfg_write()
493 struct pnv_phb *phb = pdn->phb->private_data; pnv_pci_cfg_check() local
496 if (!(phb->flags & PNV_PHB_FLAG_EEH)) pnv_pci_cfg_check()
524 struct pnv_phb *phb; pnv_pci_read_config() local
536 phb = pdn->phb->private_data; pnv_pci_read_config()
537 if (phb->flags & PNV_PHB_FLAG_EEH && pdn->edev) { pnv_pci_read_config()
553 struct pnv_phb *phb; pnv_pci_write_config() local
564 phb = pdn->phb->private_data; pnv_pci_write_config()
565 if (!(phb->flags & PNV_PHB_FLAG_EEH)) pnv_pci_write_config()
747 struct pnv_phb *phb = hose->private_data; pnv_pci_dma_dev_setup() local
756 list_for_each_entry(pe, &phb->ioda.pe_list, list) { pnv_pci_dma_dev_setup()
767 if (phb && phb->dma_dev_setup) pnv_pci_dma_dev_setup()
768 phb->dma_dev_setup(phb, pdev); pnv_pci_dma_dev_setup()
774 struct pnv_phb *phb = hose->private_data; pnv_pci_dma_bus_setup() local
777 list_for_each_entry(pe, &phb->ioda.pe_list, list) { pnv_pci_dma_bus_setup()
833 for_each_compatible_node(np, NULL, "ibm,ioda2-phb") pnv_pci_init()
H A Deeh-powernv.c49 struct pnv_phb *phb; pnv_eeh_init() local
66 phb = hose->private_data; pnv_eeh_init()
68 if (phb->model == PNV_PHB_MODEL_P7IOC) pnv_eeh_init()
78 if (phb->ioda.reserved_pe != 0) pnv_eeh_init()
134 edev->phb = hose; pnv_eeh_ei_write()
155 struct pnv_phb *phb = hose->private_data; pnv_eeh_dbgfs_set() local
157 out_be64(phb->regs + offset, val); pnv_eeh_dbgfs_set()
164 struct pnv_phb *phb = hose->private_data; pnv_eeh_dbgfs_get() local
166 *val = in_be64(phb->regs + offset); pnv_eeh_dbgfs_get()
219 struct pnv_phb *phb; pnv_eeh_post_init() local
247 phb = hose->private_data; pnv_eeh_post_init()
255 phb->flags |= PNV_PHB_FLAG_EEH; pnv_eeh_post_init()
257 phb->flags &= ~PNV_PHB_FLAG_EEH; pnv_eeh_post_init()
261 if (phb->has_dbgfs || !phb->dbgfs) pnv_eeh_post_init()
264 phb->has_dbgfs = 1; pnv_eeh_post_init()
266 phb->dbgfs, hose, pnv_eeh_post_init()
270 phb->dbgfs, hose, pnv_eeh_post_init()
273 phb->dbgfs, hose, pnv_eeh_post_init()
276 phb->dbgfs, hose, pnv_eeh_post_init()
366 struct pci_controller *hose = pdn->phb; pnv_eeh_probe()
367 struct pnv_phb *phb = hose->private_data; pnv_eeh_probe() local
405 edev->pe_config_addr = phb->ioda.pe_rmap[edev->config_addr]; pnv_eeh_probe()
477 struct pci_controller *hose = pe->phb; pnv_eeh_set_option()
478 struct pnv_phb *phb = hose->private_data; pnv_eeh_set_option() local
505 if (phb->freeze_pe) { pnv_eeh_set_option()
506 phb->freeze_pe(phb, pe->addr); pnv_eeh_set_option()
510 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); pnv_eeh_set_option()
513 __func__, rc, phb->hose->global_number, pnv_eeh_set_option()
522 if (phb->unfreeze_pe) pnv_eeh_set_option()
523 return phb->unfreeze_pe(phb, pe->addr, opt); pnv_eeh_set_option()
525 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); pnv_eeh_set_option()
528 __func__, rc, option, phb->hose->global_number, pnv_eeh_set_option()
550 struct pnv_phb *phb = pe->phb->private_data; pnv_eeh_get_phb_diag() local
553 rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, pnv_eeh_get_phb_diag()
557 __func__, rc, pe->phb->global_number); pnv_eeh_get_phb_diag()
562 struct pnv_phb *phb = pe->phb->private_data; pnv_eeh_get_phb_state() local
568 rc = opal_pci_eeh_freeze_status(phb->opal_id, pnv_eeh_get_phb_state()
575 __func__, rc, phb->hose->global_number); pnv_eeh_get_phb_state()
593 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); pnv_eeh_get_phb_state()
601 struct pnv_phb *phb = pe->phb->private_data; pnv_eeh_get_pe_state() local
625 if (phb->get_pe_state) { pnv_eeh_get_pe_state()
626 fstate = phb->get_pe_state(phb, pe->addr); pnv_eeh_get_pe_state()
628 rc = opal_pci_eeh_freeze_status(phb->opal_id, pnv_eeh_get_pe_state()
635 __func__, rc, phb->hose->global_number, pnv_eeh_get_pe_state()
672 __func__, phb->hose->global_number, pnv_eeh_get_pe_state()
688 if (phb->freeze_pe) pnv_eeh_get_pe_state()
689 phb->freeze_pe(phb, pe->addr); pnv_eeh_get_pe_state()
695 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); pnv_eeh_get_pe_state()
735 static s64 pnv_eeh_phb_poll(struct pnv_phb *phb) pnv_eeh_phb_poll() argument
740 rc = opal_pci_poll(phb->opal_id); pnv_eeh_phb_poll()
755 struct pnv_phb *phb = hose->private_data; pnv_eeh_phb_reset() local
764 rc = opal_pci_reset(phb->opal_id, pnv_eeh_phb_reset()
768 rc = opal_pci_reset(phb->opal_id, pnv_eeh_phb_reset()
780 rc = pnv_eeh_phb_poll(phb); pnv_eeh_phb_reset()
796 struct pnv_phb *phb = hose->private_data; pnv_eeh_root_reset() local
808 rc = opal_pci_reset(phb->opal_id, pnv_eeh_root_reset()
812 rc = opal_pci_reset(phb->opal_id, pnv_eeh_root_reset()
816 rc = opal_pci_reset(phb->opal_id, pnv_eeh_root_reset()
823 rc = pnv_eeh_phb_poll(phb); pnv_eeh_root_reset()
912 struct pci_controller *hose = pe->phb; pnv_eeh_reset()
933 struct pnv_phb *phb; pnv_eeh_reset() local
943 phb = hose->private_data; pnv_eeh_reset()
944 if (phb->model == PNV_PHB_MODEL_P7IOC && pnv_eeh_reset()
947 rc = opal_pci_reset(phb->opal_id, pnv_eeh_reset()
1019 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); pnv_eeh_get_log()
1052 struct pci_controller *hose = pe->phb; pnv_eeh_err_inject()
1053 struct pnv_phb *phb = hose->private_data; pnv_eeh_err_inject() local
1078 rc = opal_pci_err_inject(phb->opal_id, pe->addr, pnv_eeh_err_inject()
1155 struct pnv_phb *phb = hose->private_data; pnv_eeh_get_and_dump_hub_diag() local
1156 struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag; pnv_eeh_get_and_dump_hub_diag()
1159 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); pnv_eeh_get_and_dump_hub_diag()
1162 __func__, phb->hub_id, rc); pnv_eeh_get_and_dump_hub_diag()
1206 __func__, phb->hub_id, data->type); pnv_eeh_get_and_dump_hub_diag()
1213 struct pnv_phb *phb = hose->private_data; pnv_eeh_get_pe() local
1223 pnv_pe = &phb->ioda.pe_array[pe_no]; pnv_eeh_get_pe()
1233 edev.phb = hose; pnv_eeh_get_pe()
1242 phb->freeze_pe(phb, pe_no); pnv_eeh_get_pe()
1264 phb->freeze_pe(phb, dev_pe->addr); pnv_eeh_get_pe()
1286 struct pnv_phb *phb; pnv_eeh_next_error() local
1306 phb = hose->private_data; pnv_eeh_next_error()
1311 rc = opal_pci_next_error(phb->opal_id, pnv_eeh_next_error()
1390 rc = opal_pci_get_phb_diag_data2(phb->opal_id, pnv_eeh_next_error()
1391 phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE); pnv_eeh_next_error()
1394 phb->diag.blob); pnv_eeh_next_error()
1397 opal_pci_eeh_freeze_clear(phb->opal_id, pnv_eeh_next_error()
1408 (*pe)->phb->global_number); pnv_eeh_next_error()
1436 pnv_pci_dump_phb_diag_data((*pe)->phb, pnv_eeh_next_error()
1485 struct pnv_phb *phb; pnv_eeh_restore_config() local
1491 phb = edev->phb->private_data; pnv_eeh_restore_config()
1492 ret = opal_pci_reinit(phb->opal_id, pnv_eeh_restore_config()
H A Dpci.h32 struct pnv_phb *phb; member in struct:pnv_ioda_pe
104 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
107 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
109 u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
110 int (*init_m64)(struct pnv_phb *phb);
114 int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
115 void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
116 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
/linux-4.4.14/arch/powerpc/platforms/pseries/
H A Dpci_dlpar.c62 if (!pdn || !pdn->phb || !pdn->phb->bus) pcibios_find_pci_bus()
65 return find_bus_among_children(pdn->phb->bus, dn); pcibios_find_pci_bus()
71 struct pci_controller *phb; init_phb_dynamic() local
75 phb = pcibios_alloc_controller(dn); init_phb_dynamic()
76 if (!phb) init_phb_dynamic()
78 rtas_setup_phb(phb); init_phb_dynamic()
79 pci_process_bridge_OF_ranges(phb, dn, 0); init_phb_dynamic()
80 phb->controller_ops = pseries_pci_controller_ops; init_phb_dynamic()
82 pci_devs_phb_init_dynamic(phb); init_phb_dynamic()
85 eeh_dev_phb_init_dynamic(phb); init_phb_dynamic()
90 pcibios_scan_phb(phb); init_phb_dynamic()
91 pcibios_finish_adding_to_bus(phb->bus); init_phb_dynamic()
93 return phb; init_phb_dynamic()
98 int remove_phb_dynamic(struct pci_controller *phb) remove_phb_dynamic() argument
100 struct pci_bus *b = phb->bus; remove_phb_dynamic()
114 res = &phb->io_resource; remove_phb_dynamic()
125 phb->bus = NULL; remove_phb_dynamic()
135 res = &phb->mem_resources[i]; remove_phb_dynamic()
142 pcibios_free_controller(phb); remove_phb_dynamic()
H A Deeh_pseries.c245 pe.phb = edev->phb; pseries_eeh_probe()
270 PCI_FUNC(pdn->devfn), pe.phb->global_number, pseries_eeh_probe()
328 config_addr, BUID_HI(pe->phb->buid), pseries_eeh_set_option()
329 BUID_LO(pe->phb->buid), option); pseries_eeh_set_option()
359 pe->config_addr, BUID_HI(pe->phb->buid), pseries_eeh_get_pe_addr()
360 BUID_LO(pe->phb->buid), 1); pseries_eeh_get_pe_addr()
366 pe->config_addr, BUID_HI(pe->phb->buid), pseries_eeh_get_pe_addr()
367 BUID_LO(pe->phb->buid), 0); pseries_eeh_get_pe_addr()
370 __func__, pe->phb->global_number, pe->config_addr); pseries_eeh_get_pe_addr()
379 pe->config_addr, BUID_HI(pe->phb->buid), pseries_eeh_get_pe_addr()
380 BUID_LO(pe->phb->buid), 0); pseries_eeh_get_pe_addr()
383 __func__, pe->phb->global_number, pe->config_addr); pseries_eeh_get_pe_addr()
420 config_addr, BUID_HI(pe->phb->buid), pseries_eeh_get_state()
421 BUID_LO(pe->phb->buid)); pseries_eeh_get_state()
426 config_addr, BUID_HI(pe->phb->buid), pseries_eeh_get_state()
427 BUID_LO(pe->phb->buid)); pseries_eeh_get_state()
489 config_addr, BUID_HI(pe->phb->buid), pseries_eeh_reset()
490 BUID_LO(pe->phb->buid), option); pseries_eeh_reset()
497 config_addr, BUID_HI(pe->phb->buid), pseries_eeh_reset()
498 BUID_LO(pe->phb->buid), option); pseries_eeh_reset()
595 BUID_HI(pe->phb->buid), BUID_LO(pe->phb->buid), pseries_eeh_get_log()
630 config_addr, BUID_HI(pe->phb->buid), pseries_eeh_configure_bridge()
631 BUID_LO(pe->phb->buid)); pseries_eeh_configure_bridge()
634 config_addr, BUID_HI(pe->phb->buid), pseries_eeh_configure_bridge()
635 BUID_LO(pe->phb->buid)); pseries_eeh_configure_bridge()
661 __func__, pe->phb->global_number, pe->addr, ret); pseries_eeh_configure_bridge()
H A Diommu.c535 static void iommu_table_setparms(struct pci_controller *phb, iommu_table_setparms() argument
543 node = phb->dn; iommu_table_setparms()
558 tbl->it_busno = phb->bus->number; iommu_table_setparms()
562 tbl->it_offset = phb->dma_window_base_cur >> tbl->it_page_shift; iommu_table_setparms()
565 if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) { iommu_table_setparms()
570 phb->dma_window_base_cur += phb->dma_window_size; iommu_table_setparms()
573 tbl->it_size = phb->dma_window_size >> tbl->it_page_shift; iommu_table_setparms()
601 static void iommu_table_setparms_lpar(struct pci_controller *phb, iommu_table_setparms_lpar() argument
610 tbl->it_busno = phb->bus->number; iommu_table_setparms_lpar()
670 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */ pci_dma_bus_setup_pSeries()
672 while (pci->phb->dma_window_size * children > 0x80000000ul) pci_dma_bus_setup_pSeries()
673 pci->phb->dma_window_size >>= 1; pci_dma_bus_setup_pSeries()
675 pci->phb->dma_window_size); pci_dma_bus_setup_pSeries()
676 pci->phb->dma_window_base_cur = 0; pci_dma_bus_setup_pSeries()
686 pci->phb->dma_window_size = 0x8000000ul; pci_dma_bus_setup_pSeries()
687 pci->phb->dma_window_base_cur = 0x8000000ul; pci_dma_bus_setup_pSeries()
689 pci->table_group = iommu_pseries_alloc_group(pci->phb->node); pci_dma_bus_setup_pSeries()
692 iommu_table_setparms(pci->phb, dn, tbl); pci_dma_bus_setup_pSeries()
694 iommu_init_table(tbl, pci->phb->node); pci_dma_bus_setup_pSeries()
698 pci->phb->dma_window_size = 0x80000000ul; pci_dma_bus_setup_pSeries()
699 while (pci->phb->dma_window_size * children > 0x70000000ul) pci_dma_bus_setup_pSeries()
700 pci->phb->dma_window_size >>= 1; pci_dma_bus_setup_pSeries()
702 pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size); pci_dma_bus_setup_pSeries()
741 ppci->table_group = iommu_pseries_alloc_group(ppci->phb->node); pci_dma_bus_setup_pSeriesLP()
743 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window); pci_dma_bus_setup_pSeriesLP()
745 iommu_init_table(tbl, ppci->phb->node); pci_dma_bus_setup_pSeriesLP()
767 struct pci_controller *phb = PCI_DN(dn)->phb; pci_dma_dev_setup_pSeries() local
770 PCI_DN(dn)->table_group = iommu_pseries_alloc_group(phb->node); pci_dma_dev_setup_pSeries()
772 iommu_table_setparms(phb, dn, tbl); pci_dma_dev_setup_pSeries()
774 iommu_init_table(tbl, phb->node); pci_dma_dev_setup_pSeries()
776 pci_domain_nr(phb->bus), 0); pci_dma_dev_setup_pSeries()
921 * Get the config address and phb buid of the PE window. query_ddw()
930 buid = edev->phb->buid; query_ddw()
950 * Get the config address and phb buid of the PE window. create_ddw()
959 buid = edev->phb->buid; create_ddw()
1195 pci->table_group = iommu_pseries_alloc_group(pci->phb->node); pci_dma_dev_setup_pSeriesLP()
1197 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window); pci_dma_dev_setup_pSeriesLP()
1199 iommu_init_table(tbl, pci->phb->node); pci_dma_dev_setup_pSeriesLP()
1201 pci_domain_nr(pci->phb->bus), 0); pci_dma_dev_setup_pSeriesLP()
H A Dmsi.c41 buid = pdn->phb->buid; rtas_change_msi()
102 buid = pdn->phb->buid; rtas_query_irq_number()
510 struct pci_controller *phb; rtas_msi_init() local
527 list_for_each_entry(phb, &hose_list, list_node) { rtas_msi_init()
528 WARN_ON(phb->controller_ops.setup_msi_irqs); rtas_msi_init()
529 phb->controller_ops.setup_msi_irqs = rtas_setup_msi_irqs; rtas_msi_init()
530 phb->controller_ops.teardown_msi_irqs = rtas_teardown_msi_irqs; rtas_msi_init()
H A Dsetup.c268 update_dn_pci_info(np, pdn->phb); pci_dn_reconfig_notifier()
269 eeh_dev_init(PCI_DN(np), pdn->phb); pci_dn_reconfig_notifier()
475 struct pci_controller *phb; find_and_init_phbs() local
483 phb = pcibios_alloc_controller(node); for_each_child_of_node()
484 if (!phb) for_each_child_of_node()
486 rtas_setup_phb(phb); for_each_child_of_node()
487 pci_process_bridge_OF_ranges(phb, node, 0); for_each_child_of_node()
488 isa_bridge_find_early(phb); for_each_child_of_node()
489 phb->controller_ops = pseries_pci_controller_ops; for_each_child_of_node()
/linux-4.4.14/drivers/misc/cxl/
H A Dvphb.c45 struct pci_controller *phb; cxl_pci_enable_device_hook() local
49 phb = pci_bus_to_host(dev->bus); cxl_pci_enable_device_hook()
50 afu = (struct cxl_afu *)phb->private_data; cxl_pci_enable_device_hook()
102 static unsigned long cxl_pcie_cfg_addr(struct pci_controller* phb, cxl_pcie_cfg_addr() argument
107 return (unsigned long)phb->cfg_addr + ((unsigned long)phb->cfg_data * record) + offset; cxl_pcie_cfg_addr()
116 struct pci_controller *phb; cxl_pcie_config_info() local
120 phb = pci_bus_to_host(bus); cxl_pcie_config_info()
121 if (phb == NULL) cxl_pcie_config_info()
123 afu = (struct cxl_afu *)phb->private_data; cxl_pcie_config_info()
127 if (offset >= (unsigned long)phb->cfg_data) cxl_pcie_config_info()
129 addr = cxl_pcie_cfg_addr(phb, bus->number, devfn, offset); cxl_pcie_config_info()
150 struct pci_controller *phb; cxl_config_link_ok() local
153 /* Config space IO is based on phb->cfg_addr, which is based on cxl_config_link_ok()
160 phb = pci_bus_to_host(bus); cxl_config_link_ok()
161 if (phb == NULL) cxl_config_link_ok()
163 afu = (struct cxl_afu *)phb->private_data; cxl_config_link_ok()
235 struct pci_controller *phb, *phys_phb; cxl_pci_vphb_add() local
241 phb = pcibios_alloc_controller(phys_phb->dn); cxl_pci_vphb_add()
243 if (!phb) cxl_pci_vphb_add()
247 phb->parent = &phys_dev->dev; cxl_pci_vphb_add()
250 phb->ops = &cxl_pcie_pci_ops; cxl_pci_vphb_add()
251 phb->cfg_addr = afu->afu_desc_mmio + afu->crs_offset; cxl_pci_vphb_add()
252 phb->cfg_data = (void *)(u64)afu->crs_len; cxl_pci_vphb_add()
253 phb->private_data = afu; cxl_pci_vphb_add()
254 phb->controller_ops = cxl_pci_controller_ops; cxl_pci_vphb_add()
257 pcibios_scan_phb(phb); cxl_pci_vphb_add()
258 if (phb->bus == NULL) cxl_pci_vphb_add()
265 pcibios_claim_one_bus(phb->bus); cxl_pci_vphb_add()
268 pci_bus_add_devices(phb->bus); cxl_pci_vphb_add()
270 afu->phb = phb; cxl_pci_vphb_add()
281 afu->phb->cfg_addr = afu->afu_desc_mmio + afu->crs_offset; cxl_pci_vphb_reconfigure()
286 struct pci_controller *phb; cxl_pci_vphb_remove() local
289 if (!afu || !afu->phb) cxl_pci_vphb_remove()
292 phb = afu->phb; cxl_pci_vphb_remove()
293 afu->phb = NULL; cxl_pci_vphb_remove()
295 pci_remove_root_bus(phb->bus); cxl_pci_vphb_remove()
296 pcibios_free_controller(phb); cxl_pci_vphb_remove()
301 struct pci_controller *phb; cxl_pci_to_afu() local
303 phb = pci_bus_to_host(dev->bus); cxl_pci_to_afu()
305 return (struct cxl_afu *)phb->private_data; cxl_pci_to_afu()
H A Dpci.c1331 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { cxl_vphb_error_detected()
1496 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { cxl_pci_slot_reset()
1558 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { cxl_pci_resume()
H A Dcxl.h387 struct pci_controller *phb; member in struct:cxl_afu
/linux-4.4.14/arch/powerpc/kernel/
H A Dmsi.c18 struct pci_controller *phb = pci_bus_to_host(dev->bus); arch_setup_msi_irqs() local
20 if (!phb->controller_ops.setup_msi_irqs || arch_setup_msi_irqs()
21 !phb->controller_ops.teardown_msi_irqs) { arch_setup_msi_irqs()
30 return phb->controller_ops.setup_msi_irqs(dev, nvec, type); arch_setup_msi_irqs()
35 struct pci_controller *phb = pci_bus_to_host(dev->bus); arch_teardown_msi_irqs() local
37 phb->controller_ops.teardown_msi_irqs(dev); arch_teardown_msi_irqs()
H A Dof_platform.c42 struct pci_controller *phb; of_pci_phb_probe() local
51 phb = pcibios_alloc_controller(dev->dev.of_node); of_pci_phb_probe()
52 if (!phb) of_pci_phb_probe()
56 phb->parent = &dev->dev; of_pci_phb_probe()
59 if (ppc_md.pci_setup_phb(phb)) { of_pci_phb_probe()
60 pcibios_free_controller(phb); of_pci_phb_probe()
65 pci_process_bridge_OF_ranges(phb, dev->dev.of_node, 0); of_pci_phb_probe()
68 pci_devs_phb_init_dynamic(phb); of_pci_phb_probe()
71 eeh_dev_phb_init_dynamic(phb); of_pci_phb_probe()
78 pcibios_scan_phb(phb); of_pci_phb_probe()
79 if (phb->bus == NULL) of_pci_phb_probe()
86 pcibios_claim_one_bus(phb->bus); of_pci_phb_probe()
89 eeh_add_device_tree_late(phb->bus); of_pci_phb_probe()
92 pci_bus_add_devices(phb->bus); of_pci_phb_probe()
95 eeh_add_sysfs_files(phb->bus); of_pci_phb_probe()
H A Deeh_dev.c54 struct pci_controller *phb = data; eeh_dev_init() local
68 edev->phb = phb; eeh_dev_init()
76 * @phb: PHB
81 void eeh_dev_phb_init_dynamic(struct pci_controller *phb) eeh_dev_phb_init_dynamic() argument
83 struct pci_dn *root = phb->pci_data; eeh_dev_phb_init_dynamic()
86 eeh_phb_pe_create(phb); eeh_dev_phb_init_dynamic()
89 eeh_dev_init(root, phb); eeh_dev_phb_init_dynamic()
92 traverse_pci_dn(root, eeh_dev_init, phb); eeh_dev_phb_init_dynamic()
103 struct pci_controller *phb, *tmp; eeh_dev_phb_init() local
105 list_for_each_entry_safe(phb, tmp, &hose_list, list_node) eeh_dev_phb_init()
106 eeh_dev_phb_init_dynamic(phb); eeh_dev_phb_init()
H A Dpci-hotplug.c32 struct pci_controller *phb = pci_bus_to_host(dev->bus); pcibios_release_device() local
36 if (phb->controller_ops.release_device) pcibios_release_device()
37 phb->controller_ops.release_device(dev); pcibios_release_device()
81 struct pci_controller *phb; pcibios_add_pci_devices() local
86 phb = pci_bus_to_host(bus); pcibios_add_pci_devices()
89 if (phb->controller_ops.probe_mode) pcibios_add_pci_devices()
90 mode = phb->controller_ops.probe_mode(bus); pcibios_add_pci_devices()
H A Dio-workarounds.c36 struct pci_controller *phb = bus->phb; iowa_pci_find() local
39 vstart = (unsigned long)phb->io_base_virt; iowa_pci_find()
40 vend = vstart + phb->pci_io_size - 1; iowa_pci_find()
47 res = &phb->mem_resources[j]; iowa_pci_find()
185 void iowa_register_bus(struct pci_controller *phb, struct ppc_pci_io *ops, iowa_register_bus() argument
189 struct device_node *np = phb->dn; iowa_register_bus()
200 bus->phb = phb; iowa_register_bus()
H A Drtas_pci.c75 buid = pdn->phb->buid; rtas_read_config()
138 buid = pdn->phb->buid; rtas_write_config()
237 unsigned long get_phb_buid(struct device_node *phb) get_phb_buid() argument
243 if (of_address_to_resource(phb, 0, &r)) get_phb_buid()
249 struct pci_controller *phb) phb_set_bus_ranges()
259 phb->first_busno = be32_to_cpu(bus_range[0]); phb_set_bus_ranges()
260 phb->last_busno = be32_to_cpu(bus_range[1]); phb_set_bus_ranges()
265 int rtas_setup_phb(struct pci_controller *phb) rtas_setup_phb() argument
267 struct device_node *dev = phb->dn; rtas_setup_phb()
272 if (phb_set_bus_ranges(dev, phb)) rtas_setup_phb()
275 phb->ops = &rtas_pci_ops; rtas_setup_phb()
276 phb->buid = get_phb_buid(dev); rtas_setup_phb()
248 phb_set_bus_ranges(struct device_node *dev, struct pci_controller *phb) phb_set_bus_ranges() argument
H A Dpci_dn.c156 pdn->phb = parent->phb; add_one_dev_pci_data()
274 struct pci_controller *phb = data; update_dn_pci_info() local
285 pdn->phb = phb; update_dn_pci_info()
332 * because the start node is often a phb which may be missing PCI
344 /* We started with a phb, iterate all childs */ traverse_pci_devices()
420 * phb: pci-to-host bridge (top-level bridge connecting to cpu)
426 void pci_devs_phb_init_dynamic(struct pci_controller *phb) pci_devs_phb_init_dynamic() argument
428 struct device_node *dn = phb->dn; pci_devs_phb_init_dynamic()
432 update_dn_pci_info(dn, phb); pci_devs_phb_init_dynamic()
437 pdn->phb = phb; pci_devs_phb_init_dynamic()
438 phb->pci_data = pdn; pci_devs_phb_init_dynamic()
441 /* Update dn->phb ptrs for new phb and children devices */ pci_devs_phb_init_dynamic()
442 traverse_pci_devices(dn, update_dn_pci_info, phb); pci_devs_phb_init_dynamic()
448 * This routine walks over all phb's (pci-host bridges) on the
456 struct pci_controller *phb, *tmp; pci_devs_phb_init() local
459 list_for_each_entry_safe(phb, tmp, &hose_list, list_node) pci_devs_phb_init()
460 pci_devs_phb_init_dynamic(phb); pci_devs_phb_init()
H A Ddma.c329 struct pci_controller *phb = pci_bus_to_host(pdev->bus); dma_set_mask() local
330 if (phb->controller_ops.dma_set_mask) dma_set_mask()
331 return phb->controller_ops.dma_set_mask(pdev, dma_mask); dma_set_mask()
358 struct pci_controller *phb = pci_bus_to_host(pdev->bus); dma_get_required_mask() local
359 if (phb->controller_ops.dma_get_required_mask) dma_get_required_mask()
360 return phb->controller_ops.dma_get_required_mask(pdev); dma_get_required_mask()
H A Deeh_pe.c54 * @phb: PCI controller
59 static struct eeh_pe *eeh_pe_alloc(struct pci_controller *phb, int type) eeh_pe_alloc() argument
76 pe->phb = phb; eeh_pe_alloc()
88 * @phb: PCI controller
93 int eeh_phb_pe_create(struct pci_controller *phb) eeh_phb_pe_create() argument
98 pe = eeh_pe_alloc(phb, EEH_PE_PHB); eeh_phb_pe_create()
107 pr_debug("EEH: Add PE for PHB#%d\n", phb->global_number); eeh_phb_pe_create()
114 * @phb: PCI controller
120 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb) eeh_phb_pe_get() argument
130 if ((pe->type & EEH_PE_PHB) && pe->phb == phb) eeh_phb_pe_get()
276 struct eeh_pe *root = eeh_phb_pe_get(edev->phb); eeh_pe_get()
334 __func__, edev->config_addr, edev->phb->global_number); eeh_add_to_parent_pe()
353 edev->phb->global_number, eeh_add_to_parent_pe()
376 edev->phb->global_number, eeh_add_to_parent_pe()
385 pe = eeh_pe_alloc(edev->phb, EEH_PE_DEVICE); eeh_add_to_parent_pe()
401 parent = eeh_phb_pe_get(edev->phb); eeh_add_to_parent_pe()
404 __func__, edev->phb->global_number); eeh_add_to_parent_pe()
421 edev->phb->global_number, eeh_add_to_parent_pe()
446 __func__, edev->phb->global_number, eeh_rmv_from_parent_pe()
708 __func__, edev->phb->global_number, eeh_bridge_check_link()
928 bus = pe->phb->bus; eeh_pe_bus_get()
H A Dpci-common.c48 static int global_phb_number; /* Global phb counter */
69 struct pci_controller *phb; pcibios_alloc_controller() local
71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); pcibios_alloc_controller()
72 if (phb == NULL) pcibios_alloc_controller()
75 phb->global_number = global_phb_number++; pcibios_alloc_controller()
76 list_add_tail(&phb->list_node, &hose_list); pcibios_alloc_controller()
78 phb->dn = dev; pcibios_alloc_controller()
79 phb->is_dynamic = slab_is_available(); pcibios_alloc_controller()
87 PHB_SET_NODE(phb, nid); pcibios_alloc_controller()
90 return phb; pcibios_alloc_controller()
94 void pcibios_free_controller(struct pci_controller *phb) pcibios_free_controller() argument
97 list_del(&phb->list_node); pcibios_free_controller()
100 if (phb->is_dynamic) pcibios_free_controller()
101 kfree(phb); pcibios_free_controller()
114 struct pci_controller *phb = pci_bus_to_host(bus); pcibios_window_alignment() local
116 if (phb->controller_ops.window_alignment) pcibios_window_alignment()
117 return phb->controller_ops.window_alignment(bus, type); pcibios_window_alignment()
129 struct pci_controller *phb = pci_bus_to_host(dev->bus); pcibios_reset_secondary_bus() local
131 if (phb->controller_ops.reset_secondary_bus) { pcibios_reset_secondary_bus()
132 phb->controller_ops.reset_secondary_bus(dev); pcibios_reset_secondary_bus()
953 struct pci_controller *phb; pcibios_setup_bus_self() local
966 phb = pci_bus_to_host(bus); pcibios_setup_bus_self()
967 if (phb->controller_ops.dma_bus_setup) pcibios_setup_bus_self()
968 phb->controller_ops.dma_bus_setup(bus); pcibios_setup_bus_self()
973 struct pci_controller *phb; pcibios_setup_device() local
984 phb = pci_bus_to_host(dev->bus); pcibios_setup_device()
985 if (phb->controller_ops.dma_dev_setup) pcibios_setup_device()
986 phb->controller_ops.dma_dev_setup(dev); pcibios_setup_device()
1455 struct pci_controller *phb = pci_bus_to_host(dev->bus); pcibios_enable_device() local
1457 if (phb->controller_ops.enable_device_hook) pcibios_enable_device()
1458 if (!phb->controller_ops.enable_device_hook(dev)) pcibios_enable_device()
1466 struct pci_controller *phb = pci_bus_to_host(dev->bus); pcibios_disable_device() local
1468 if (phb->controller_ops.disable_device) pcibios_disable_device()
1469 phb->controller_ops.disable_device(dev); pcibios_disable_device()
H A Deeh_event.c79 pe->phb->global_number); eeh_event_handler()
83 pe->phb->global_number, pe->addr); eeh_event_handler()
186 if (event->pe && event->pe->phb == pe->phb) { eeh_remove_event()
H A Dpci_of_scan.c209 struct pci_controller *phb; of_scan_pci_bridge() local
289 phb = pci_bus_to_host(bus); of_scan_pci_bridge()
292 if (phb->controller_ops.probe_mode) of_scan_pci_bridge()
293 mode = phb->controller_ops.probe_mode(bus); of_scan_pci_bridge()
H A Dpci_64.c242 hose = PCI_DN(hose_node)->phb; sys_pciconfig_iobase()
263 struct pci_controller *phb = pci_bus_to_host(bus); pcibus_to_node() local
264 return phb->node; pcibus_to_node()
H A Deeh.c172 edev->phb->global_number, pdn->busno, eeh_dump_dev_log()
175 edev->phb->global_number, pdn->busno, eeh_dump_dev_log()
379 phb_pe = eeh_phb_pe_get(pe->phb); eeh_phb_check_failure()
382 __func__, pe->phb->global_number); eeh_phb_check_failure()
408 phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe)); eeh_phb_check_failure()
568 phb_pe = eeh_phb_pe_get(pe->phb); eeh_dev_check_failure()
570 pe->phb->global_number, pe->addr); eeh_dev_check_failure()
674 __func__, function, pe->phb->global_number, eeh_pci_enable()
871 __func__, pe->phb->global_number, pe->addr); eeh_reset_pe()
879 __func__, state, pe->phb->global_number, pe->addr, (i + 1)); eeh_reset_pe()
1072 struct pci_controller *phb; eeh_add_device_early() local
1082 phb = edev->phb; eeh_add_device_early()
1083 if (NULL == phb || eeh_add_device_early()
1084 (eeh_has_flag(EEH_PROBE_MODE_DEVTREE) && 0 == phb->buid)) eeh_add_device_early()
1272 __func__, ret, pe->phb->global_number, pe->addr); eeh_unfreeze_pe()
1279 __func__, ret, pe->phb->global_number, pe->addr); eeh_unfreeze_pe()
H A Deeh_driver.c497 __func__, rc, pe->phb->global_number, pe->addr); __eeh_clear_pe_frozen_state()
665 __func__, pe->phb->global_number, pe->addr); eeh_handle_normal_event()
802 pe->phb->global_number, pe->addr, eeh_handle_normal_event()
809 pe->phb->global_number, pe->addr); eeh_handle_normal_event()
/linux-4.4.14/arch/powerpc/sysdev/
H A Dmv64x60_pci.c32 struct pci_dev *phb; mv64x60_hs_reg_read() local
40 phb = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); mv64x60_hs_reg_read()
41 if (!phb) mv64x60_hs_reg_read()
43 pci_read_config_dword(phb, MV64X60_PCICFG_CPCI_HOTSWAP, &v); mv64x60_hs_reg_read()
44 pci_dev_put(phb); mv64x60_hs_reg_read()
53 struct pci_dev *phb; mv64x60_hs_reg_write() local
64 phb = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); mv64x60_hs_reg_write()
65 if (!phb) mv64x60_hs_reg_write()
67 pci_write_config_dword(phb, MV64X60_PCICFG_CPCI_HOTSWAP, v); mv64x60_hs_reg_write()
68 pci_dev_put(phb); mv64x60_hs_reg_write()
H A Dmpic_u3msi.c185 struct pci_controller *phb; mpic_u3msi_init() local
198 list_for_each_entry(phb, &hose_list, list_node) { mpic_u3msi_init()
199 WARN_ON(phb->controller_ops.setup_msi_irqs); mpic_u3msi_init()
200 phb->controller_ops.setup_msi_irqs = u3msi_setup_msi_irqs; mpic_u3msi_init()
201 phb->controller_ops.teardown_msi_irqs = u3msi_teardown_msi_irqs; mpic_u3msi_init()
H A Dppc4xx_hsta_msi.c132 struct pci_controller *phb; hsta_msi_probe() local
176 list_for_each_entry(phb, &hose_list, list_node) { hsta_msi_probe()
177 phb->controller_ops.setup_msi_irqs = hsta_setup_msi_irqs; hsta_msi_probe()
178 phb->controller_ops.teardown_msi_irqs = hsta_teardown_msi_irqs; hsta_msi_probe()
H A Dppc4xx_msi.c222 struct pci_controller *phb; ppc4xx_msi_probe() local
255 list_for_each_entry(phb, &hose_list, list_node) { ppc4xx_msi_probe()
256 phb->controller_ops.setup_msi_irqs = ppc4xx_setup_msi_irqs; ppc4xx_msi_probe()
257 phb->controller_ops.teardown_msi_irqs = ppc4xx_teardown_msi_irqs; ppc4xx_msi_probe()
H A Dfsl_msi.c409 struct pci_controller *phb; fsl_of_msi_probe() local
551 list_for_each_entry(phb, &hose_list, list_node) { fsl_of_msi_probe()
552 if (!phb->controller_ops.setup_msi_irqs) { fsl_of_msi_probe()
553 phb->controller_ops.setup_msi_irqs = fsl_setup_msi_irqs; fsl_of_msi_probe()
554 phb->controller_ops.teardown_msi_irqs = fsl_teardown_msi_irqs; fsl_of_msi_probe()
555 } else if (phb->controller_ops.setup_msi_irqs != fsl_setup_msi_irqs) { fsl_of_msi_probe()
H A Dfsl_pci.h121 extern void fsl_pcibios_fixup_phb(struct pci_controller *phb);
H A Dfsl_pci.c1251 void fsl_pcibios_fixup_phb(struct pci_controller *phb) fsl_pcibios_fixup_phb() argument
1254 fsl_pci_pme_probe(phb); fsl_pcibios_fixup_phb()
/linux-4.4.14/drivers/pci/hotplug/
H A Drpadlpar_core.c146 struct pci_controller *phb = pdn->phb; dlpar_pci_add_bus() local
152 dev = of_create_pci_dev(dn, phb->bus, pdn->devfn); dlpar_pci_add_bus()
171 pcibios_finish_adding_to_bus(phb->bus); dlpar_pci_add_bus()
177 struct pci_controller *phb; dlpar_add_pci_slot() local
186 phb = PCI_DN(dn)->phb; dlpar_add_pci_slot()
187 dev = dlpar_find_new_dev(phb->bus, dn); dlpar_add_pci_slot()
228 BUG_ON(!pdn || !pdn->phb); dlpar_remove_phb()
229 rc = remove_phb_dynamic(pdn->phb); dlpar_remove_phb()
233 pdn->phb = NULL; dlpar_remove_phb()
240 struct pci_controller *phb; dlpar_add_phb() local
242 if (PCI_DN(dn) && PCI_DN(dn)->phb) { dlpar_add_phb()
247 phb = init_phb_dynamic(dn); dlpar_add_phb()
248 if (!phb) dlpar_add_phb()
/linux-4.4.14/arch/powerpc/platforms/cell/
H A Dspider-pci.c82 static int __init spiderpci_pci_setup_chip(struct pci_controller *phb, spiderpci_pci_setup_chip() argument
112 dummy_page_da = dma_map_single(phb->parent, dummy_page_va, spiderpci_pci_setup_chip()
114 if (dma_mapping_error(phb->parent, dummy_page_da)) { spiderpci_pci_setup_chip()
129 struct device_node *np = bus->phb->dn; spiderpci_iowa_init()
156 if (spiderpci_pci_setup_chip(bus->phb, regs)) spiderpci_iowa_init()
H A Dsetup.c121 static int cell_setup_phb(struct pci_controller *phb) cell_setup_phb() argument
126 int rc = rtas_setup_phb(phb); cell_setup_phb()
130 phb->controller_ops = cell_pci_controller_ops; cell_setup_phb()
132 np = phb->dn; cell_setup_phb()
141 iowa_register_bus(phb, &spiderpci_ops, &spiderpci_iowa_init, cell_setup_phb()
/linux-4.4.14/arch/powerpc/platforms/pasemi/
H A Dmsi.c146 struct pci_controller *phb; mpic_pasemi_msi_init() local
164 list_for_each_entry(phb, &hose_list, list_node) { mpic_pasemi_msi_init()
165 WARN_ON(phb->controller_ops.setup_msi_irqs); mpic_pasemi_msi_init()
166 phb->controller_ops.setup_msi_irqs = pasemi_msi_setup_msi_irqs; mpic_pasemi_msi_init()
167 phb->controller_ops.teardown_msi_irqs = pasemi_msi_teardown_msi_irqs; mpic_pasemi_msi_init()
/linux-4.4.14/arch/powerpc/include/asm/
H A Dppc-pci.h44 extern void pci_devs_phb_init_dynamic(struct pci_controller *phb);
49 extern int rtas_setup_phb(struct pci_controller *phb);
H A Dio-workarounds.h29 struct pci_controller *phb; member in struct:iowa_bus
H A Deeh.h91 struct pci_controller *phb; /* Associated PHB */ member in struct:eeh_pe
141 struct pci_controller *phb; /* Associated PHB */ member in struct:eeh_dev
258 int eeh_phb_pe_create(struct pci_controller *phb);
259 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
273 void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
330 static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { } eeh_dev_phb_init_dynamic() argument
H A Dpci-bridge.h202 struct pci_controller *phb; /* for pci devices */ member in struct:pci_dn
203 struct iommu_table_group *table_group; /* for phb's or bridges */
297 extern void pcibios_free_controller(struct pci_controller *phb);
H A Dpci.h124 extern int remove_phb_dynamic(struct pci_controller *phb);
/linux-4.4.14/arch/powerpc/platforms/amigaone/
H A Dsetup.c74 int phb = -ENODEV; amigaone_setup_arch() local
78 phb = amigaone_add_bridge(np); amigaone_setup_arch()
80 BUG_ON(phb != 0); amigaone_setup_arch()
/linux-4.4.14/arch/microblaze/pci/
H A Dpci-common.c45 static int global_phb_number; /* Global phb counter */
55 struct pci_controller *phb; pcibios_alloc_controller() local
57 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); pcibios_alloc_controller()
58 if (!phb) pcibios_alloc_controller()
61 phb->global_number = global_phb_number++; pcibios_alloc_controller()
62 list_add_tail(&phb->list_node, &hose_list); pcibios_alloc_controller()
64 phb->dn = dev; pcibios_alloc_controller()
65 phb->is_dynamic = mem_init_done; pcibios_alloc_controller()
66 return phb; pcibios_alloc_controller()
69 void pcibios_free_controller(struct pci_controller *phb) pcibios_free_controller() argument
72 list_del(&phb->list_node); pcibios_free_controller()
75 if (phb->is_dynamic) pcibios_free_controller()
76 kfree(phb); pcibios_free_controller()
/linux-4.4.14/arch/microblaze/include/asm/
H A Dpci-bridge.h141 extern void pcibios_free_controller(struct pci_controller *phb);
/linux-4.4.14/arch/x86/kernel/
H A Dpci-calgary_64.c1087 int rioidx, phb, bus; calgary_locate_bbars() local
1106 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) { calgary_locate_bbars()
1107 offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET; calgary_locate_bbars()
1118 bus_info[bus].phbid = phb; calgary_locate_bbars()
1122 bus_info[start_bus].phbid = phb; calgary_locate_bbars()

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