1/* 2 * Support PCI/PCIe on PowerNV platforms 3 * 4 * Currently supports only P5IOC2 5 * 6 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14#include <linux/kernel.h> 15#include <linux/pci.h> 16#include <linux/delay.h> 17#include <linux/string.h> 18#include <linux/init.h> 19#include <linux/bootmem.h> 20#include <linux/irq.h> 21#include <linux/io.h> 22#include <linux/msi.h> 23 24#include <asm/sections.h> 25#include <asm/io.h> 26#include <asm/prom.h> 27#include <asm/pci-bridge.h> 28#include <asm/machdep.h> 29#include <asm/msi_bitmap.h> 30#include <asm/ppc-pci.h> 31#include <asm/opal.h> 32#include <asm/iommu.h> 33#include <asm/tce.h> 34 35#include "powernv.h" 36#include "pci.h" 37 38/* For now, use a fixed amount of TCE memory for each p5ioc2 39 * hub, 16M will do 40 */ 41#define P5IOC2_TCE_MEMORY 0x01000000 42 43#ifdef CONFIG_PCI_MSI 44static int pnv_pci_p5ioc2_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 45 unsigned int hwirq, unsigned int virq, 46 unsigned int is_64, struct msi_msg *msg) 47{ 48 if (WARN_ON(!is_64)) 49 return -ENXIO; 50 msg->data = hwirq - phb->msi_base; 51 msg->address_hi = 0x10000000; 52 msg->address_lo = 0; 53 54 return 0; 55} 56 57static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb) 58{ 59 unsigned int count; 60 const __be32 *prop = of_get_property(phb->hose->dn, 61 "ibm,opal-msi-ranges", NULL); 62 if (!prop) 63 return; 64 65 /* Don't do MSI's on p5ioc2 PCI-X are they are not properly 66 * verified in HW 67 */ 68 if (of_device_is_compatible(phb->hose->dn, "ibm,p5ioc2-pcix")) 69 return; 70 phb->msi_base = be32_to_cpup(prop); 71 count = be32_to_cpup(prop + 1); 72 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { 73 pr_err("PCI %d: Failed to allocate MSI bitmap !\n", 74 phb->hose->global_number); 75 return; 76 } 77 phb->msi_setup = pnv_pci_p5ioc2_msi_setup; 78 phb->msi32_support = 0; 79 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", 80 count, phb->msi_base); 81} 82#else 83static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb) { } 84#endif /* CONFIG_PCI_MSI */ 85 86static struct iommu_table_ops pnv_p5ioc2_iommu_ops = { 87 .set = pnv_tce_build, 88#ifdef CONFIG_IOMMU_API 89 .exchange = pnv_tce_xchg, 90#endif 91 .clear = pnv_tce_free, 92 .get = pnv_tce_get, 93}; 94 95static void pnv_pci_p5ioc2_dma_dev_setup(struct pnv_phb *phb, 96 struct pci_dev *pdev) 97{ 98 struct iommu_table *tbl = phb->p5ioc2.table_group.tables[0]; 99 100 if (!tbl->it_map) { 101 tbl->it_ops = &pnv_p5ioc2_iommu_ops; 102 iommu_init_table(tbl, phb->hose->node); 103 iommu_register_group(&phb->p5ioc2.table_group, 104 pci_domain_nr(phb->hose->bus), phb->opal_id); 105 INIT_LIST_HEAD_RCU(&tbl->it_group_list); 106 pnv_pci_link_table_and_group(phb->hose->node, 0, 107 tbl, &phb->p5ioc2.table_group); 108 } 109 110 set_iommu_table_base(&pdev->dev, tbl); 111 iommu_add_device(&pdev->dev); 112} 113 114static const struct pci_controller_ops pnv_pci_p5ioc2_controller_ops = { 115 .dma_dev_setup = pnv_pci_dma_dev_setup, 116#ifdef CONFIG_PCI_MSI 117 .setup_msi_irqs = pnv_setup_msi_irqs, 118 .teardown_msi_irqs = pnv_teardown_msi_irqs, 119#endif 120}; 121 122static void __init pnv_pci_init_p5ioc2_phb(struct device_node *np, u64 hub_id, 123 void *tce_mem, u64 tce_size) 124{ 125 struct pnv_phb *phb; 126 const __be64 *prop64; 127 u64 phb_id; 128 int64_t rc; 129 static int primary = 1; 130 struct iommu_table_group *table_group; 131 struct iommu_table *tbl; 132 133 pr_info(" Initializing p5ioc2 PHB %s\n", np->full_name); 134 135 prop64 = of_get_property(np, "ibm,opal-phbid", NULL); 136 if (!prop64) { 137 pr_err(" Missing \"ibm,opal-phbid\" property !\n"); 138 return; 139 } 140 phb_id = be64_to_cpup(prop64); 141 pr_devel(" PHB-ID : 0x%016llx\n", phb_id); 142 pr_devel(" TCE AT : 0x%016lx\n", __pa(tce_mem)); 143 pr_devel(" TCE SZ : 0x%016llx\n", tce_size); 144 145 rc = opal_pci_set_phb_tce_memory(phb_id, __pa(tce_mem), tce_size); 146 if (rc != OPAL_SUCCESS) { 147 pr_err(" Failed to set TCE memory, OPAL error %lld\n", rc); 148 return; 149 } 150 151 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); 152 phb->hose = pcibios_alloc_controller(np); 153 if (!phb->hose) { 154 pr_err(" Failed to allocate PCI controller\n"); 155 return; 156 } 157 158 spin_lock_init(&phb->lock); 159 phb->hose->first_busno = 0; 160 phb->hose->last_busno = 0xff; 161 phb->hose->private_data = phb; 162 phb->hose->controller_ops = pnv_pci_p5ioc2_controller_ops; 163 phb->hub_id = hub_id; 164 phb->opal_id = phb_id; 165 phb->type = PNV_PHB_P5IOC2; 166 phb->model = PNV_PHB_MODEL_P5IOC2; 167 168 phb->regs = of_iomap(np, 0); 169 170 if (phb->regs == NULL) 171 pr_err(" Failed to map registers !\n"); 172 else { 173 pr_devel(" P_BUID = 0x%08x\n", in_be32(phb->regs + 0x100)); 174 pr_devel(" P_IOSZ = 0x%08x\n", in_be32(phb->regs + 0x1b0)); 175 pr_devel(" P_IO_ST = 0x%08x\n", in_be32(phb->regs + 0x1e0)); 176 pr_devel(" P_MEM1_H = 0x%08x\n", in_be32(phb->regs + 0x1a0)); 177 pr_devel(" P_MEM1_L = 0x%08x\n", in_be32(phb->regs + 0x190)); 178 pr_devel(" P_MSZ1_L = 0x%08x\n", in_be32(phb->regs + 0x1c0)); 179 pr_devel(" P_MEM_ST = 0x%08x\n", in_be32(phb->regs + 0x1d0)); 180 pr_devel(" P_MEM2_H = 0x%08x\n", in_be32(phb->regs + 0x2c0)); 181 pr_devel(" P_MEM2_L = 0x%08x\n", in_be32(phb->regs + 0x2b0)); 182 pr_devel(" P_MSZ2_H = 0x%08x\n", in_be32(phb->regs + 0x2d0)); 183 pr_devel(" P_MSZ2_L = 0x%08x\n", in_be32(phb->regs + 0x2e0)); 184 } 185 186 /* Interpret the "ranges" property */ 187 /* This also maps the I/O region and sets isa_io/mem_base */ 188 pci_process_bridge_OF_ranges(phb->hose, np, primary); 189 primary = 0; 190 191 phb->hose->ops = &pnv_pci_ops; 192 193 /* Setup MSI support */ 194 pnv_pci_init_p5ioc2_msis(phb); 195 196 /* Setup TCEs */ 197 phb->dma_dev_setup = pnv_pci_p5ioc2_dma_dev_setup; 198 pnv_pci_setup_iommu_table(&phb->p5ioc2.iommu_table, 199 tce_mem, tce_size, 0, 200 IOMMU_PAGE_SHIFT_4K); 201 /* 202 * We do not allocate iommu_table as we do not support 203 * hotplug or SRIOV on P5IOC2 and therefore iommu_free_table() 204 * should not be called for phb->p5ioc2.table_group.tables[0] ever. 205 */ 206 tbl = phb->p5ioc2.table_group.tables[0] = &phb->p5ioc2.iommu_table; 207 table_group = &phb->p5ioc2.table_group; 208 table_group->tce32_start = tbl->it_offset << tbl->it_page_shift; 209 table_group->tce32_size = tbl->it_size << tbl->it_page_shift; 210} 211 212void __init pnv_pci_init_p5ioc2_hub(struct device_node *np) 213{ 214 struct device_node *phbn; 215 const __be64 *prop64; 216 u64 hub_id; 217 void *tce_mem; 218 uint64_t tce_per_phb; 219 int64_t rc; 220 int phb_count = 0; 221 222 pr_info("Probing p5ioc2 IO-Hub %s\n", np->full_name); 223 224 prop64 = of_get_property(np, "ibm,opal-hubid", NULL); 225 if (!prop64) { 226 pr_err(" Missing \"ibm,opal-hubid\" property !\n"); 227 return; 228 } 229 hub_id = be64_to_cpup(prop64); 230 pr_info(" HUB-ID : 0x%016llx\n", hub_id); 231 232 /* Count child PHBs and calculate TCE space per PHB */ 233 for_each_child_of_node(np, phbn) { 234 if (of_device_is_compatible(phbn, "ibm,p5ioc2-pcix") || 235 of_device_is_compatible(phbn, "ibm,p5ioc2-pciex")) 236 phb_count++; 237 } 238 239 if (phb_count <= 0) { 240 pr_info(" No PHBs for Hub %s\n", np->full_name); 241 return; 242 } 243 244 tce_per_phb = __rounddown_pow_of_two(P5IOC2_TCE_MEMORY / phb_count); 245 pr_info(" Allocating %lld MB of TCE memory per PHB\n", 246 tce_per_phb >> 20); 247 248 /* Currently allocate 16M of TCE memory for every Hub 249 * 250 * XXX TODO: Make it chip local if possible 251 */ 252 tce_mem = memblock_virt_alloc(P5IOC2_TCE_MEMORY, P5IOC2_TCE_MEMORY); 253 pr_debug(" TCE : 0x%016lx..0x%016lx\n", 254 __pa(tce_mem), __pa(tce_mem) + P5IOC2_TCE_MEMORY - 1); 255 rc = opal_pci_set_hub_tce_memory(hub_id, __pa(tce_mem), 256 P5IOC2_TCE_MEMORY); 257 if (rc != OPAL_SUCCESS) { 258 pr_err(" Failed to allocate TCE memory, OPAL error %lld\n", rc); 259 return; 260 } 261 262 /* Initialize PHBs */ 263 for_each_child_of_node(np, phbn) { 264 if (of_device_is_compatible(phbn, "ibm,p5ioc2-pcix") || 265 of_device_is_compatible(phbn, "ibm,p5ioc2-pciex")) { 266 pnv_pci_init_p5ioc2_phb(phbn, hub_id, 267 tce_mem, tce_per_phb); 268 tce_mem += tce_per_phb; 269 } 270 } 271} 272