Searched refs:op_regs (Results 1 - 13 of 13) sorted by relevance

/linux-4.4.14/drivers/usb/gadget/udc/
H A Dmv_udc_core.c96 epctrlx = readl(&udc->op_regs->epctrlx[0]); ep0_reset()
108 writel(epctrlx, &udc->op_regs->epctrlx[0]); ep0_reset()
118 epctrlx = readl(&udc->op_regs->epctrlx[0]); ep0_stall()
120 writel(epctrlx, &udc->op_regs->epctrlx[0]); ep0_stall()
196 while (readl(&udc->op_regs->epstatus) & bit_pos) process_ep_req()
281 if (readl(&udc->op_regs->epprime) & bit_pos) queue_dtd()
287 usbcmd = readl(&udc->op_regs->usbcmd); queue_dtd()
289 writel(usbcmd, &udc->op_regs->usbcmd); queue_dtd()
292 epstatus = readl(&udc->op_regs->epstatus) & bit_pos; queue_dtd()
301 if (readl(&udc->op_regs->usbcmd) queue_dtd()
316 usbcmd = readl(&udc->op_regs->usbcmd); queue_dtd()
318 writel(usbcmd, &udc->op_regs->usbcmd); queue_dtd()
335 writel(bit_pos, &udc->op_regs->epprime); queue_dtd()
477 if ((readl(&udc->op_regs->epprime) & bit_pos) mv_ep_enable()
478 || (readl(&udc->op_regs->epstatus) & bit_pos)) { mv_ep_enable()
483 (unsigned)readl(&udc->op_regs->epprime), mv_ep_enable()
484 (unsigned)readl(&udc->op_regs->epstatus), mv_ep_enable()
526 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]); mv_ep_enable()
538 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]); mv_ep_enable()
544 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]); mv_ep_enable()
548 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]); mv_ep_enable()
551 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]); mv_ep_enable()
555 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]); mv_ep_enable()
591 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]); mv_ep_disable()
595 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]); mv_ep_disable()
664 (unsigned)readl(&udc->op_regs->epstatus), mv_ep_fifo_flush()
669 writel(bit_pos, &udc->op_regs->epflush); mv_ep_fifo_flush()
673 while (readl(&udc->op_regs->epflush)) { mv_ep_fifo_flush()
682 (unsigned)readl(&udc->op_regs->epflush), mv_ep_fifo_flush()
690 } while (readl(&udc->op_regs->epstatus) & bit_pos); mv_ep_fifo_flush()
780 writel(bit_pos, &ep->udc->op_regs->epprime); mv_prime_ep()
801 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]); mv_ep_dequeue()
806 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]); mv_ep_dequeue()
854 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]); mv_ep_dequeue()
859 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]); mv_ep_dequeue()
870 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]); ep_set_stall()
886 writel(epctrlx, &udc->op_regs->epctrlx[ep_num]); ep_set_stall()
893 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]); ep_is_stall()
985 tmp = readl(&udc->op_regs->usbintr); udc_stop()
988 writel(tmp, &udc->op_regs->usbintr); udc_stop()
993 tmp = readl(&udc->op_regs->usbcmd); udc_stop()
995 writel(tmp, &udc->op_regs->usbcmd); udc_stop()
1006 writel(usbintr, &udc->op_regs->usbintr); udc_start()
1011 writel(USBCMD_RUN_STOP, &udc->op_regs->usbcmd); udc_start()
1020 tmp = readl(&udc->op_regs->usbcmd); udc_reset()
1022 writel(tmp, &udc->op_regs->usbcmd); udc_reset()
1025 writel(USBCMD_CTRL_RESET, &udc->op_regs->usbcmd); udc_reset()
1029 while (readl(&udc->op_regs->usbcmd) & USBCMD_CTRL_RESET) { udc_reset()
1040 tmp = readl(&udc->op_regs->usbmode); udc_reset()
1046 writel(tmp, &udc->op_regs->usbmode); udc_reset()
1048 writel(0x0, &udc->op_regs->epsetupstat); udc_reset()
1052 &udc->op_regs->eplistaddr); udc_reset()
1054 portsc = readl(&udc->op_regs->portsc[0]); udc_reset()
1063 writel(portsc, &udc->op_regs->portsc[0]); udc_reset()
1065 tmp = readl(&udc->op_regs->epctrlx[0]); udc_reset()
1067 writel(tmp, &udc->op_regs->epctrlx[0]); udc_reset()
1130 retval = readl(&udc->op_regs->frindex) & USB_FRINDEX_MASKS; mv_udc_get_frame()
1145 portsc = readl(&udc->op_regs->portsc); mv_udc_wakeup()
1151 writel(portsc, &udc->op_regs->portsc[0]); mv_udc_wakeup()
1426 portsc = readl(&udc->op_regs->portsc[0]); mv_set_ptc()
1428 writel(portsc, &udc->op_regs->portsc[0]); mv_set_ptc()
1739 &udc->op_regs->deviceaddr); ep0_req_complete()
1775 writel((1 << ep_num), &udc->op_regs->epsetupstat); get_setup_data()
1780 temp = readl(&udc->op_regs->usbcmd); get_setup_data()
1781 writel(temp | USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd); get_setup_data()
1785 } while (!(readl(&udc->op_regs->usbcmd) & USBCMD_SETUP_TRIPWIRE_SET)); get_setup_data()
1788 temp = readl(&udc->op_regs->usbcmd); get_setup_data()
1789 writel(temp & ~USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd); get_setup_data()
1806 tmp = readl(&udc->op_regs->epsetupstat); irq_process_tr_complete()
1824 tmp = readl(&udc->op_regs->epcomplete); irq_process_tr_complete()
1829 writel(tmp, &udc->op_regs->epcomplete); irq_process_tr_complete()
1875 tmp = readl(&udc->op_regs->deviceaddr); irq_process_reset()
1877 writel(tmp, &udc->op_regs->deviceaddr); irq_process_reset()
1880 tmp = readl(&udc->op_regs->epsetupstat); irq_process_reset()
1881 writel(tmp, &udc->op_regs->epsetupstat); irq_process_reset()
1884 tmp = readl(&udc->op_regs->epcomplete); irq_process_reset()
1885 writel(tmp, &udc->op_regs->epcomplete); irq_process_reset()
1889 while (readl(&udc->op_regs->epprime) & 0xFFFFFFFF) { irq_process_reset()
1893 readl(&udc->op_regs->epprime)); irq_process_reset()
1901 writel((u32)~0, &udc->op_regs->epflush); irq_process_reset()
1903 if (readl(&udc->op_regs->portsc[0]) & PORTSCX_PORT_RESET) { irq_process_reset()
1910 readl(&udc->op_regs->portsc)); irq_process_reset()
1962 portsc = readl(&udc->op_regs->portsc[0]); irq_process_port_change()
2018 status = readl(&udc->op_regs->usbsts); mv_udc_irq()
2019 intr = readl(&udc->op_regs->usbintr); mv_udc_irq()
2028 writel(status, &udc->op_regs->usbsts); mv_udc_irq()
2189 udc->op_regs = mv_udc_probe()
2200 writel(0xFFFFFFFF, &udc->op_regs->usbsts); mv_udc_probe()
2412 mode = readl(&udc->op_regs->usbmode); mv_udc_shutdown()
2414 writel(mode, &udc->op_regs->usbmode); mv_udc_shutdown()
H A Dmv_u3d_core.c275 iowrite32(tmp, &u3d->op_regs->doorbell); mv_u3d_queue_trb()
1038 tmp = ioread32(&u3d->op_regs->usbcmd); mv_u3d_controller_stop()
1040 iowrite32(tmp, &u3d->op_regs->usbcmd); mv_u3d_controller_stop()
1042 ioread32(&u3d->op_regs->usbcmd)); mv_u3d_controller_stop()
1066 iowrite32(MV_U3D_CMD_RUN_STOP, &u3d->op_regs->usbcmd); mv_u3d_controller_start()
1068 ioread32(&u3d->op_regs->usbcmd)); mv_u3d_controller_start()
1077 tmp = ioread32(&u3d->op_regs->usbcmd); mv_u3d_controller_reset()
1079 iowrite32(tmp, &u3d->op_regs->usbcmd); mv_u3d_controller_reset()
1082 iowrite32(MV_U3D_CMD_CTRL_RESET, &u3d->op_regs->usbcmd); mv_u3d_controller_reset()
1086 while (ioread32(&u3d->op_regs->usbcmd) & MV_U3D_CMD_CTRL_RESET) { mv_u3d_controller_reset()
1097 iowrite32(u3d->ep_context_dma, &u3d->op_regs->dcbaapl); mv_u3d_controller_reset()
1098 iowrite32(0, &u3d->op_regs->dcbaaph); mv_u3d_controller_reset()
1857 u3d->op_regs = (struct mv_u3d_op_regs __iomem *)(u3d->cap_regs mv_u3d_probe()
2053 tmp = ioread32(&u3d->op_regs->usbcmd); mv_u3d_shutdown()
2055 iowrite32(tmp, &u3d->op_regs->usbcmd); mv_u3d_shutdown()
H A Dmv_u3d.h252 struct mv_u3d_op_regs __iomem *op_regs; member in struct:mv_u3d
H A Dmv_udc.h182 struct mv_op_regs __iomem *op_regs; member in struct:mv_udc
/linux-4.4.14/drivers/usb/phy/
H A Dphy-mv-usb.c151 tmp = readl(&mvotg->op_regs->usbcmd); mv_otg_reset()
153 writel(tmp, &mvotg->op_regs->usbcmd); mv_otg_reset()
156 writel(USBCMD_CTRL_RESET, &mvotg->op_regs->usbcmd); mv_otg_reset()
159 while (readl(&mvotg->op_regs->usbcmd) & USBCMD_CTRL_RESET) { mv_otg_reset()
169 writel(0x0, &mvotg->op_regs->usbintr); mv_otg_reset()
170 tmp = readl(&mvotg->op_regs->usbsts); mv_otg_reset()
171 writel(tmp, &mvotg->op_regs->usbsts); mv_otg_reset()
197 otgsc = readl(&mvotg->op_regs->otgsc); mv_otg_init_irq()
199 writel(otgsc, &mvotg->op_regs->otgsc); mv_otg_init_irq()
304 otgsc = readl(&mvotg->op_regs->otgsc); mv_otg_update_inputs()
496 otgsc = readl(&mvotg->op_regs->otgsc); mv_otg_irq()
497 writel(otgsc, &mvotg->op_regs->otgsc); mv_otg_irq()
766 mvotg->op_regs = mv_otg_probe()
881 otgsc = readl(&mvotg->op_regs->otgsc); mv_otg_resume()
883 writel(otgsc, &mvotg->op_regs->otgsc); mv_otg_resume()
H A Dphy-mv-usb.h145 struct mv_otg_regs __iomem *op_regs; member in struct:mv_otg
/linux-4.4.14/drivers/usb/host/
H A Dehci-mv.c30 void __iomem *op_regs; member in struct:ehci_hcd_mv
192 ehci_mv->op_regs = mv_ehci_probe()
197 hcd->regs = ehci_mv->op_regs; mv_ehci_probe()
247 pdata->private_init(ehci_mv->op_regs, ehci_mv->phy_regs); mv_ehci_probe()
H A Dxhci.c90 halted = readl(&xhci->op_regs->status) & STS_HALT; xhci_quiesce()
94 cmd = readl(&xhci->op_regs->command); xhci_quiesce()
96 writel(cmd, &xhci->op_regs->command); xhci_quiesce()
113 ret = xhci_handshake(&xhci->op_regs->status, xhci_halt()
132 temp = readl(&xhci->op_regs->command); xhci_start()
136 writel(temp, &xhci->op_regs->command); xhci_start()
142 ret = xhci_handshake(&xhci->op_regs->status, xhci_start()
168 state = readl(&xhci->op_regs->status); xhci_reset()
175 command = readl(&xhci->op_regs->command); xhci_reset()
177 writel(command, &xhci->op_regs->command); xhci_reset()
189 ret = xhci_handshake(&xhci->op_regs->command, xhci_reset()
200 ret = xhci_handshake(&xhci->op_regs->status, xhci_reset()
642 temp = readl(&xhci->op_regs->command); xhci_run()
646 writel(temp, &xhci->op_regs->command); xhci_run()
714 temp = readl(&xhci->op_regs->status); xhci_stop()
715 writel(temp & ~STS_EINT, &xhci->op_regs->status); xhci_stop()
724 readl(&xhci->op_regs->status)); xhci_stop()
755 readl(&xhci->op_regs->status)); xhci_shutdown()
765 xhci->s3.command = readl(&xhci->op_regs->command); xhci_save_registers()
766 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification); xhci_save_registers()
767 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); xhci_save_registers()
768 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg); xhci_save_registers()
778 writel(xhci->s3.command, &xhci->op_regs->command); xhci_restore_registers()
779 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification); xhci_restore_registers()
780 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr); xhci_restore_registers()
781 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg); xhci_restore_registers()
794 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); xhci_set_cmd_ring_deq()
803 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); xhci_set_cmd_ring_deq()
925 command = readl(&xhci->op_regs->command); xhci_suspend()
927 writel(command, &xhci->op_regs->command); xhci_suspend()
932 if (xhci_handshake(&xhci->op_regs->status, xhci_suspend()
944 command = readl(&xhci->op_regs->command); xhci_suspend()
946 writel(command, &xhci->op_regs->command); xhci_suspend()
947 if (xhci_handshake(&xhci->op_regs->status, xhci_suspend()
1014 command = readl(&xhci->op_regs->command); xhci_resume()
1016 writel(command, &xhci->op_regs->command); xhci_resume()
1017 if (xhci_handshake(&xhci->op_regs->status, xhci_resume()
1023 temp = readl(&xhci->op_regs->status); xhci_resume()
1047 temp = readl(&xhci->op_regs->status); xhci_resume()
1048 writel(temp & ~STS_EINT, &xhci->op_regs->status); xhci_resume()
1056 readl(&xhci->op_regs->status)); xhci_resume()
1085 command = readl(&xhci->op_regs->command); xhci_resume()
1087 writel(command, &xhci->op_regs->command); xhci_resume()
1088 xhci_handshake(&xhci->op_regs->status, STS_HALT, xhci_resume()
1105 status = readl(&xhci->op_regs->status); xhci_resume()
1548 temp = readl(&xhci->op_regs->status); xhci_urb_dequeue()
3647 state = readl(&xhci->op_regs->status); xhci_free_dev()
3929 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); xhci_setup_device()
3986 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base; xhci_find_raw_port_number()
4894 xhci->op_regs = hcd->regs + xhci_gen_setup()
H A Dxhci-dbg.c45 xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs); xhci_dbg_regs()
130 temp = readl(&xhci->op_regs->command); xhci_print_command_reg()
148 temp = readl(&xhci->op_regs->status); xhci_print_status()
160 xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs); xhci_print_op_regs()
178 addr = &xhci->op_regs->port_status_base; xhci_print_ports()
432 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); xhci_dbg_cmd_ptrs()
H A Dxhci-hub.c1372 temp = readl(&xhci->op_regs->command); xhci_bus_resume()
1374 writel(temp, &xhci->op_regs->command); xhci_bus_resume()
1430 (void) readl(&xhci->op_regs->command); xhci_bus_resume()
1434 temp = readl(&xhci->op_regs->command); xhci_bus_resume()
1436 writel(temp, &xhci->op_regs->command); xhci_bus_resume()
1437 temp = readl(&xhci->op_regs->command); xhci_bus_resume()
H A Dxhci-mem.c2314 &xhci->op_regs->port_status_base + xhci_setup_port_arrays()
2335 &xhci->op_regs->port_status_base + xhci_setup_port_arrays()
2365 page_size = readl(&xhci->op_regs->page_size); xhci_mem_init()
2391 val2 = readl(&xhci->op_regs->config_reg); xhci_mem_init()
2395 writel(val, &xhci->op_regs->config_reg); xhci_mem_init()
2410 xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr); xhci_mem_init()
2454 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); xhci_mem_init()
2460 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); xhci_mem_init()
2573 temp = readl(&xhci->op_regs->dev_notification); xhci_mem_init()
2576 writel(temp, &xhci->op_regs->dev_notification); xhci_mem_init()
H A Dxhci-ring.c290 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); xhci_abort_cmd_ring()
293 &xhci->op_regs->cmd_ring); xhci_abort_cmd_ring()
302 ret = xhci_handshake(&xhci->op_regs->cmd_ring, xhci_abort_cmd_ring()
307 &xhci->op_regs->cmd_ring); xhci_abort_cmd_ring()
309 ret = xhci_handshake(&xhci->op_regs->cmd_ring, xhci_abort_cmd_ring()
1267 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); xhci_handle_command_timeout()
1564 temp1 = readl(&xhci->op_regs->command); handle_port_status()
2696 status = readl(&xhci->op_regs->status); xhci_irq()
2718 writel(status, &xhci->op_regs->status); xhci_irq()
H A Dxhci.h1511 struct xhci_op_regs __iomem *op_regs; member in struct:xhci_hcd

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