90 	halted = readl(&xhci->op_regs->status) & STS_HALT;  in xhci_quiesce()
94 	cmd = readl(&xhci->op_regs->command);  in xhci_quiesce()
96 	writel(cmd, &xhci->op_regs->command);  in xhci_quiesce()
113 	ret = xhci_handshake(&xhci->op_regs->status,  in xhci_halt()
132 	temp = readl(&xhci->op_regs->command);  in xhci_start()
136 	writel(temp, &xhci->op_regs->command);  in xhci_start()
142 	ret = xhci_handshake(&xhci->op_regs->status,  in xhci_start()
168 	state = readl(&xhci->op_regs->status);  in xhci_reset()
175 	command = readl(&xhci->op_regs->command);  in xhci_reset()
177 	writel(command, &xhci->op_regs->command);  in xhci_reset()
189 	ret = xhci_handshake(&xhci->op_regs->command,  in xhci_reset()
200 	ret = xhci_handshake(&xhci->op_regs->status,  in xhci_reset()
642 	temp = readl(&xhci->op_regs->command);  in xhci_run()
646 	writel(temp, &xhci->op_regs->command);  in xhci_run()
714 	temp = readl(&xhci->op_regs->status);  in xhci_stop()
715 	writel(temp & ~STS_EINT, &xhci->op_regs->status);  in xhci_stop()
724 			readl(&xhci->op_regs->status));  in xhci_stop()
755 			readl(&xhci->op_regs->status));  in xhci_shutdown()
765 	xhci->s3.command = readl(&xhci->op_regs->command);  in xhci_save_registers()
766 	xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);  in xhci_save_registers()
767 	xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);  in xhci_save_registers()
768 	xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);  in xhci_save_registers()
778 	writel(xhci->s3.command, &xhci->op_regs->command);  in xhci_restore_registers()
779 	writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);  in xhci_restore_registers()
780 	xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);  in xhci_restore_registers()
781 	writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);  in xhci_restore_registers()
794 	val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);  in xhci_set_cmd_ring_deq()
803 	xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);  in xhci_set_cmd_ring_deq()
925 	command = readl(&xhci->op_regs->command);  in xhci_suspend()
927 	writel(command, &xhci->op_regs->command);  in xhci_suspend()
932 	if (xhci_handshake(&xhci->op_regs->status,  in xhci_suspend()
944 	command = readl(&xhci->op_regs->command);  in xhci_suspend()
946 	writel(command, &xhci->op_regs->command);  in xhci_suspend()
947 	if (xhci_handshake(&xhci->op_regs->status,  in xhci_suspend()
1014 		command = readl(&xhci->op_regs->command);  in xhci_resume()
1016 		writel(command, &xhci->op_regs->command);  in xhci_resume()
1017 		if (xhci_handshake(&xhci->op_regs->status,  in xhci_resume()
1023 		temp = readl(&xhci->op_regs->status);  in xhci_resume()
1047 		temp = readl(&xhci->op_regs->status);  in xhci_resume()
1048 		writel(temp & ~STS_EINT, &xhci->op_regs->status);  in xhci_resume()
1056 			    readl(&xhci->op_regs->status));  in xhci_resume()
1085 	command = readl(&xhci->op_regs->command);  in xhci_resume()
1087 	writel(command, &xhci->op_regs->command);  in xhci_resume()
1088 	xhci_handshake(&xhci->op_regs->status, STS_HALT,  in xhci_resume()
1105 		status = readl(&xhci->op_regs->status);  in xhci_resume()
1548 	temp = readl(&xhci->op_regs->status);  in xhci_urb_dequeue()
3647 	state = readl(&xhci->op_regs->status);  in xhci_free_dev()
3929 	temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);  in xhci_setup_device()
3986 	__le32 __iomem *base_addr = &xhci->op_regs->port_status_base;  in xhci_find_raw_port_number()
4894 	xhci->op_regs = hcd->regs +  in xhci_gen_setup()