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Searched refs:nvkm_mask (Results 1 – 120 of 120) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dhdmig84.c58 nvkm_mask(device, 0x6165a4 + hoff, 0x40000000, 0x00000000); in g84_hdmi_ctrl()
59 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
60 nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
65 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
71 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000001); in g84_hdmi_ctrl()
74 nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000); in g84_hdmi_ctrl()
78 nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000001); in g84_hdmi_ctrl()
80 nvkm_mask(device, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ in g84_hdmi_ctrl()
81 nvkm_mask(device, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ in g84_hdmi_ctrl()
82 nvkm_mask(device, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ in g84_hdmi_ctrl()
[all …]
Dhdmigt215.c59 nvkm_mask(device, 0x61c5a4 + soff, 0x40000000, 0x00000000); in gt215_hdmi_ctrl()
60 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
61 nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
66 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
72 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000001); in gt215_hdmi_ctrl()
75 nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000000); in gt215_hdmi_ctrl()
79 nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000001); in gt215_hdmi_ctrl()
81 nvkm_mask(device, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ in gt215_hdmi_ctrl()
82 nvkm_mask(device, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ in gt215_hdmi_ctrl()
83 nvkm_mask(device, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ in gt215_hdmi_ctrl()
[all …]
Dhdmigf119.c57 nvkm_mask(device, 0x616798 + hoff, 0x40000000, 0x00000000); in gf119_hdmi_ctrl()
58 nvkm_mask(device, 0x6167a4 + hoff, 0x00000001, 0x00000000); in gf119_hdmi_ctrl()
59 nvkm_mask(device, 0x616714 + hoff, 0x00000001, 0x00000000); in gf119_hdmi_ctrl()
64 nvkm_mask(device, 0x616714 + hoff, 0x00000001, 0x00000000); in gf119_hdmi_ctrl()
70 nvkm_mask(device, 0x616714 + hoff, 0x00000001, 0x00000001); in gf119_hdmi_ctrl()
73 nvkm_mask(device, 0x6167a4 + hoff, 0x00000001, 0x00000000); in gf119_hdmi_ctrl()
75 nvkm_mask(device, 0x6167a4 + hoff, 0x00000001, 0x00000001); in gf119_hdmi_ctrl()
78 nvkm_mask(device, 0x616798 + hoff, 0x401f007f, ctrl); in gf119_hdmi_ctrl()
Dhdmigk104.c58 nvkm_mask(device, 0x616798 + hoff, 0x40000000, 0x00000000); in gk104_hdmi_ctrl()
59 nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000000); in gk104_hdmi_ctrl()
60 nvkm_mask(device, 0x690000 + hdmi, 0x00000001, 0x00000000); in gk104_hdmi_ctrl()
65 nvkm_mask(device, 0x690000 + hdmi, 0x00000001, 0x00000000); in gk104_hdmi_ctrl()
71 nvkm_mask(device, 0x690000 + hdmi, 0x00000001, 0x00000001); in gk104_hdmi_ctrl()
74 nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000000); in gk104_hdmi_ctrl()
76 nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000001); in gk104_hdmi_ctrl()
82 nvkm_mask(device, 0x616798 + hoff, 0x401f007f, ctrl); in gk104_hdmi_ctrl()
Ddmacgf119.c48 nvkm_mask(device, 0x610490 + (chid * 0x0010), 0x00001010, 0x00001000); in gf119_disp_dmac_fini()
49 nvkm_mask(device, 0x610490 + (chid * 0x0010), 0x00000003, 0x00000000); in gf119_disp_dmac_fini()
59 nvkm_mask(device, 0x610090, 0x00000001 << chid, 0x00000000); in gf119_disp_dmac_fini()
60 nvkm_mask(device, 0x6100a0, 0x00000001 << chid, 0x00000000); in gf119_disp_dmac_fini()
72 nvkm_mask(device, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid); in gf119_disp_dmac_init()
78 nvkm_mask(device, 0x610490 + (chid * 0x0010), 0x00000010, 0x00000010); in gf119_disp_dmac_init()
Dcorenv50.c175 nvkm_mask(device, 0x610200, 0x00000010, 0x00000000); in nv50_disp_core_fini()
176 nvkm_mask(device, 0x610200, 0x00000003, 0x00000000); in nv50_disp_core_fini()
186 nvkm_mask(device, 0x610028, 0x00010001, 0x00000000); in nv50_disp_core_fini()
197 nvkm_mask(device, 0x610028, 0x00010000, 0x00010000); in nv50_disp_core_init()
201 nvkm_mask(device, 0x610200, 0x00800000, 0x00800000); in nv50_disp_core_init()
203 nvkm_mask(device, 0x610200, 0x00600000, 0x00600000); in nv50_disp_core_init()
209 nvkm_mask(device, 0x610200, 0x00000010, 0x00000010); in nv50_disp_core_init()
Dcoregf119.c182 nvkm_mask(device, 0x610490, 0x00000010, 0x00000000); in gf119_disp_core_fini()
183 nvkm_mask(device, 0x610490, 0x00000003, 0x00000000); in gf119_disp_core_fini()
193 nvkm_mask(device, 0x610090, 0x00000001, 0x00000000); in gf119_disp_core_fini()
194 nvkm_mask(device, 0x6100a0, 0x00000001, 0x00000000); in gf119_disp_core_fini()
205 nvkm_mask(device, 0x6100a0, 0x00000001, 0x00000001); in gf119_disp_core_init()
211 nvkm_mask(device, 0x610490, 0x00000010, 0x00000010); in gf119_disp_core_init()
Dhdagf119.c57 nvkm_mask(device, 0x616618 + hoff, 0x8000000c, 0x80000001); in gf119_hda_eld()
64 nvkm_mask(device, 0x616548 + hoff, 0x00000070, 0x00000000); in gf119_hda_eld()
69 nvkm_mask(device, 0x10ec10 + soff, 0x80000003, 0x80000003); in gf119_hda_eld()
72 nvkm_mask(device, 0x616618 + hoff, 0x80000001, 0x80000000); in gf119_hda_eld()
79 nvkm_mask(device, 0x10ec10 + soff, 0x80000003, 0x80000000 | !!size); in gf119_hda_eld()
Dhdagt215.c54 nvkm_mask(device, 0x61c1e0 + soff, 0x8000000d, 0x80000001); in gt215_hda_eld()
65 nvkm_mask(device, 0x61c448 + soff, 0x80000003, 0x80000003); in gt215_hda_eld()
68 nvkm_mask(device, 0x61c1e0 + soff, 0x80000001, 0x80000000); in gt215_hda_eld()
75 nvkm_mask(device, 0x61c448 + soff, 0x80000003, 0x80000000 | !!size); in gt215_hda_eld()
Dpiocgf119.c37 nvkm_mask(device, 0x610490 + (chid * 0x10), 0x00000001, 0x00000000); in gf119_disp_pioc_fini()
47 nvkm_mask(device, 0x610090, 0x00000001 << chid, 0x00000000); in gf119_disp_pioc_fini()
48 nvkm_mask(device, 0x6100a0, 0x00000001 << chid, 0x00000000); in gf119_disp_pioc_fini()
60 nvkm_mask(device, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid); in gf119_disp_pioc_init()
Dsorgm204.c48 nvkm_mask(device, 0x612308 + soff, 0x0000001f, 0x00000000 | data); in gm204_sor_magic()
50 nvkm_mask(device, 0x612388 + soff, 0x0000001f, 0x00000010 | data); in gm204_sor_magic()
66 nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, data); in gm204_sor_dp_pattern()
68 nvkm_mask(device, 0x61c12c + soff, 0x0f0f0f0f, data); in gm204_sor_dp_pattern()
83 nvkm_mask(device, 0x61c130 + loff, 0x0000000f, mask); in gm204_sor_dp_lnk_pwr()
84 nvkm_mask(device, 0x61c034 + soff, 0x80000000, 0x80000000); in gm204_sor_dp_lnk_pwr()
Ddacnv50.c61 nvkm_mask(device, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat); in nv50_dac_power()
91 nvkm_mask(device, 0x61a004 + doff, 0x807f0000, 0x80150000); in nv50_dac_sense()
100 loadval = nvkm_mask(device, 0x61a00c + doff, 0xffffffff, 0x00000000); in nv50_dac_sense()
102 nvkm_mask(device, 0x61a004 + doff, 0x807f0000, 0x80550000); in nv50_dac_sense()
Dsorg94.c77 nvkm_mask(device, 0x61c10c + loff, 0x0f000000, pattern << 24); in g94_sor_dp_pattern()
92 nvkm_mask(device, 0x61c130 + loff, 0x0000000f, mask); in g94_sor_dp_lnk_pwr()
93 nvkm_mask(device, 0x61c034 + soff, 0x80000000, 0x80000000); in g94_sor_dp_lnk_pwr()
116 nvkm_mask(device, 0x614300 + soff, 0x000c0000, clksor); in g94_sor_dp_lnk_ctl()
117 nvkm_mask(device, 0x61c10c + loff, 0x001f4000, dpctrl); in g94_sor_dp_lnk_ctl()
Ddmacnv50.c196 nvkm_mask(device, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000); in nv50_disp_dmac_fini()
197 nvkm_mask(device, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000); in nv50_disp_dmac_fini()
207 nvkm_mask(device, 0x610028, 0x00010001 << chid, 0x00000000 << chid); in nv50_disp_dmac_fini()
219 nvkm_mask(device, 0x610028, 0x00010000 << chid, 0x00010000 << chid); in nv50_disp_dmac_init()
225 nvkm_mask(device, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010); in nv50_disp_dmac_init()
Dchangf119.c31 nvkm_mask(device, 0x610090, 0x00000001 << index, 0x00000000 << index); in gf119_disp_chan_uevent_fini()
41 nvkm_mask(device, 0x610090, 0x00000001 << index, 0x00000001 << index); in gf119_disp_chan_uevent_init()
Dsorgf119.c44 nvkm_mask(device, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern); in gf119_sor_dp_pattern()
62 nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor); in gf119_sor_dp_lnk_ctl()
63 nvkm_mask(device, 0x61c10c + loff, 0x001f4000, dpctrl); in gf119_sor_dp_lnk_ctl()
Dgf119.c37 nvkm_mask(device, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000001); in gf119_disp_vblank_init()
44 nvkm_mask(device, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000000); in gf119_disp_vblank_fini()
268 nvkm_mask(device, 0x616620 + hoff, 0x0000ffff, value); in gf119_disp_intr_unk2_2_tu()
275 nvkm_mask(device, 0x616624 + hoff, 0x00ffffff, value); in gf119_disp_intr_unk2_2_tu()
339 nvkm_mask(device, addr, 0x007c0000, 0x00280000); in gf119_disp_intr_unk2_2()
349 nvkm_mask(device, addr, 0x00000707, data); in gf119_disp_intr_unk2_2()
496 nvkm_mask(device, 0x6100bc + (i * 0x800), 0, 0); in gf119_disp_intr()
Dnv50.c167 nvkm_mask(device, 0x61002c, (4 << head), 0); in nv50_disp_vblank_fini()
174 nvkm_mask(device, 0x61002c, (4 << head), (4 << head)); in nv50_disp_vblank_init()
516 nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, value); in nv50_disp_intr_unk20_2_dp()
523 nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, value); in nv50_disp_intr_unk20_2_dp()
599 nvkm_mask(device, 0x61c10c + loff, 0x000001fc, bestTU << 2); in nv50_disp_intr_unk20_2_dp()
600 nvkm_mask(device, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 | in nv50_disp_intr_unk20_2_dp()
684 nvkm_mask(device, hreg, 0x0000000f, hval); in nv50_disp_intr_unk20_2()
685 nvkm_mask(device, oreg, mask, oval); in nv50_disp_intr_unk20_2()
710 nvkm_mask(device, 0x61c10c + loff, 0x00000001, 0x00000000); in nv50_disp_intr_unk40_0_tmds()
Drootgf119.c114 nvkm_mask(device, 0x6194e8, 0x00000001, 0x00000000); in gf119_disp_root_init()
137 nvkm_mask(device, 0x616308 + (i * 0x800), 0x00000111, 0x00000010); in gf119_disp_root_init()
Dsornv50.c57 nvkm_mask(device, 0x61c004 + soff, 0x80000001, 0x80000000 | stat); in nv50_sor_power()
Dpiocnv50.c37 nvkm_mask(device, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000); in nv50_disp_pioc_fini()
Dpiornv50.c60 nvkm_mask(device, 0x61e004 + soff, 0x80000101, 0x80000000 | ctrl); in nv50_pior_power()
Dchannv50.c107 nvkm_mask(device, 0x610028, 0x00000001 << index, 0x00000000 << index); in nv50_disp_chan_uevent_fini()
117 nvkm_mask(device, 0x610028, 0x00000001 << index, 0x00000001 << index); in nv50_disp_chan_uevent_init()
Drootnv50.c353 nvkm_mask(device, 0x6194e8, 0x00000001, 0x00000000); in nv50_disp_root_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dgk110.c58 nvkm_mask(device, 0x000200, 0x00001000, 0x00000000); in gk110_pmu_pgob()
60 nvkm_mask(device, 0x000200, 0x08000000, 0x08000000); in gk110_pmu_pgob()
63 nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000002); in gk110_pmu_pgob()
64 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001); in gk110_pmu_pgob()
65 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000); in gk110_pmu_pgob()
67 nvkm_mask(device, 0x0206b4, 0x00000000, 0x00000000); in gk110_pmu_pgob()
76 nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000000); in gk110_pmu_pgob()
77 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001); in gk110_pmu_pgob()
78 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000); in gk110_pmu_pgob()
80 nvkm_mask(device, 0x000200, 0x08000000, 0x00000000); in gk110_pmu_pgob()
[all …]
Dgk104.c64 nvkm_mask(device, 0x000200, 0x00001000, 0x00000000); in gk104_pmu_pgob()
66 nvkm_mask(device, 0x000200, 0x08000000, 0x08000000); in gk104_pmu_pgob()
69 nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000002); in gk104_pmu_pgob()
70 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001); in gk104_pmu_pgob()
71 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000); in gk104_pmu_pgob()
73 nvkm_mask(device, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000); in gk104_pmu_pgob()
76 nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000000); in gk104_pmu_pgob()
77 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001); in gk104_pmu_pgob()
78 nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000); in gk104_pmu_pgob()
80 nvkm_mask(device, 0x000200, 0x08000000, 0x00000000); in gk104_pmu_pgob()
[all …]
Dgt215.c31 nvkm_mask(device, 0x022210, 0x00000001, 0x00000000); in gt215_pmu_reset()
32 nvkm_mask(device, 0x022210, 0x00000001, 0x00000001); in gt215_pmu_reset()
Dbase.c206 nvkm_mask(device, 0x000200, 0x00002000, 0x00000000); in nvkm_pmu_init()
207 nvkm_mask(device, 0x000200, 0x00002000, 0x00002000); in nvkm_pmu_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv05.c78 nvkm_mask(device, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); in nv05_devinit_meminit()
89 nvkm_mask(device, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]); in nv05_devinit_meminit()
92 nvkm_mask(device, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE); in nv05_devinit_meminit()
94 nvkm_mask(device, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20); in nv05_devinit_meminit()
95 nvkm_mask(device, NV04_PFB_CFG1, 0, 1); in nv05_devinit_meminit()
102 nvkm_mask(device, NV04_PFB_BOOT_0, in nv05_devinit_meminit()
111 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, in nv05_devinit_meminit()
116 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, in nv05_devinit_meminit()
120 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, in nv05_devinit_meminit()
Dnv04.c53 nvkm_mask(device, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF); in nv04_devinit_meminit()
55 nvkm_mask(device, NV04_PFB_BOOT_0, ~0, in nv04_devinit_meminit()
66 nvkm_mask(device, NV04_PFB_BOOT_0, in nv04_devinit_meminit()
69 nvkm_mask(device, NV04_PFB_DEBUG_0, in nv04_devinit_meminit()
76 nvkm_mask(device, NV04_PFB_BOOT_0, in nv04_devinit_meminit()
82 nvkm_mask(device, NV04_PFB_BOOT_0, in nv04_devinit_meminit()
89 nvkm_mask(device, NV04_PFB_BOOT_0, in nv04_devinit_meminit()
93 nvkm_mask(device, NV04_PFB_BOOT_0, in nv04_devinit_meminit()
97 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, in nv04_devinit_meminit()
101 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, in nv04_devinit_meminit()
[all …]
Dnv50.c60 nvkm_mask(device, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1); in nv50_devinit_pll_set()
61 nvkm_mask(device, info.reg + 8, 0x7fff00ff, (P << 28) | in nv50_devinit_pll_set()
65 nvkm_mask(device, info.reg + 0, 0x01ff0000, in nv50_devinit_pll_set()
72 nvkm_mask(device, info.reg + 0, 0x00070000, (P << 16)); in nv50_devinit_pll_set()
Dnv20.c51 nvkm_mask(device, NV04_PFB_CFG0, 0, mask); in nv20_devinit_meminit()
60 nvkm_mask(device, NV04_PFB_CFG0, mask, 0); in nv20_devinit_meminit()
Dnv10.c59 nvkm_mask(device, NV04_PFB_CFG0, 0x30, mem_width[i]); in nv10_devinit_meminit()
93 nvkm_mask(device, NV04_PFB_CFG0, 0x1000, 0); in nv10_devinit_meminit()
Dgm204.c128 nvkm_mask(device, 0x000200, 0x00002000, 0x00000000); in gm204_devinit_post()
129 nvkm_mask(device, 0x000200, 0x00002000, 0x00002000); in gm204_devinit_post()
Dgf100.c53 nvkm_mask(device, info.reg + 0x0c, 0x00000000, 0x00000100); in gf100_devinit_pll_set()
Dgt215.c52 nvkm_mask(device, info.reg + 4, 0x003fffff, in gt215_devinit_pll_set()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/
Dgk104.c34 nvkm_mask(device, 0x122128 + (i * 0x0800), 0x00000200, 0x00000000); in gk104_ibus_intr_hub()
45 nvkm_mask(device, 0x124128 + (i * 0x0800), 0x00000200, 0x00000000); in gk104_ibus_intr_rop()
56 nvkm_mask(device, 0x128128 + (i * 0x0800), 0x00000200, 0x00000000); in gk104_ibus_intr_gpc()
99 nvkm_mask(device, 0x122318, 0x0003ffff, 0x00001000); in gk104_ibus_init()
100 nvkm_mask(device, 0x12231c, 0x0003ffff, 0x00000200); in gk104_ibus_init()
101 nvkm_mask(device, 0x122310, 0x0003ffff, 0x00000800); in gk104_ibus_init()
102 nvkm_mask(device, 0x122348, 0x0003ffff, 0x00000100); in gk104_ibus_init()
103 nvkm_mask(device, 0x1223b0, 0x0003ffff, 0x00000fff); in gk104_ibus_init()
104 nvkm_mask(device, 0x122348, 0x0003ffff, 0x00000200); in gk104_ibus_init()
105 nvkm_mask(device, 0x122358, 0x0003ffff, 0x00002880); in gk104_ibus_init()
Dgk20a.c29 nvkm_mask(device, 0x137250, 0x3f, 0); in gk20a_ibus_init_ibus_ring()
31 nvkm_mask(device, 0x000200, 0x20, 0); in gk20a_ibus_init_ibus_ring()
33 nvkm_mask(device, 0x000200, 0x20, 0x20); in gk20a_ibus_init_ibus_ring()
60 nvkm_mask(device, 0x12004c, 0x2, 0x2); in gk20a_ibus_intr()
Dgf117.c30 nvkm_mask(device, 0x122310, 0x0003ffff, 0x00000800); in gf117_ibus_init()
31 nvkm_mask(device, 0x122348, 0x0003ffff, 0x00000100); in gf117_ibus_init()
32 nvkm_mask(device, 0x1223b0, 0x0003ffff, 0x00000fff); in gf117_ibus_init()
Dgf100.c34 nvkm_mask(device, 0x122128 + (i * 0x0400), 0x00000200, 0x00000000); in gf100_ibus_intr_hub()
45 nvkm_mask(device, 0x124128 + (i * 0x0400), 0x00000200, 0x00000000); in gf100_ibus_intr_rop()
56 nvkm_mask(device, 0x128128 + (i * 0x0400), 0x00000200, 0x00000000); in gf100_ibus_intr_gpc()
99 nvkm_mask(device, 0x122310, 0x0003ffff, 0x00000800); in gf100_ibus_init()
103 nvkm_mask(device, 0x122348, 0x0003ffff, 0x00000100); in gf100_ibus_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgt215.c310 nvkm_mask(device, 0x020060, 0x00070000, 0x00000000); in gt215_clk_pre()
311 nvkm_mask(device, 0x002504, 0x00000001, 0x00000001); in gt215_clk_pre()
347 nvkm_mask(device, 0x002504, 0x00000001, 0x00000000); in gt215_clk_post()
348 nvkm_mask(device, 0x020060, 0x00070000, 0x00040000); in gt215_clk_post()
355 nvkm_mask(device, src, 0x00000100, 0x00000000); in disable_clk_src()
356 nvkm_mask(device, src, 0x00000001, 0x00000000); in disable_clk_src()
374 nvkm_mask(device, src1, 0x00000101, 0x00000101); in prog_pll()
375 nvkm_mask(device, ctrl, 0x00000008, 0x00000008); in prog_pll()
379 nvkm_mask(device, src0, 0x003f3141, 0x00000101 | info->clk); in prog_pll()
381 nvkm_mask(device, ctrl, 0x00000015, 0x00000015); in prog_pll()
[all …]
Dgk104.c362 nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x8000003f, info->ddiv); in gk104_clk_prog_0()
371 nvkm_mask(device, 0x137100, (1 << idx), 0x00000000); in gk104_clk_prog_1_0()
382 nvkm_mask(device, 0x137160 + (idx * 0x04), 0x00000100, 0x00000000); in gk104_clk_prog_1_1()
391 nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000); in gk104_clk_prog_2()
392 nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000); in gk104_clk_prog_2()
395 nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); in gk104_clk_prog_2()
400 nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004); in gk104_clk_prog_2()
410 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f00, info->mdiv); in gk104_clk_prog_3()
412 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x0000003f, info->mdiv); in gk104_clk_prog_3()
421 nvkm_mask(device, 0x137100, (1 << idx), info->ssel); in gk104_clk_prog_4_0()
[all …]
Dgf100.c341 nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x80003f3f, info->ddiv); in gf100_clk_prog_0()
350 nvkm_mask(device, 0x137100, (1 << idx), 0x00000000); in gf100_clk_prog_1()
364 nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000); in gf100_clk_prog_2()
365 nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000); in gf100_clk_prog_2()
368 nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); in gf100_clk_prog_2()
373 nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004); in gf100_clk_prog_2()
384 nvkm_mask(device, 0x137100, (1 << idx), info->ssel); in gf100_clk_prog_3()
398 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f3f, info->mdiv); in gf100_clk_prog_4()
Dgk20a.c282 nvkm_mask(device, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT, in gk20a_pllg_slide()
284 nvkm_mask(device, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT, in gk20a_pllg_slide()
288 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, in gk20a_pllg_slide()
313 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN, in gk20a_pllg_slide()
330 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); in _gk20a_pllg_enable()
338 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); in _gk20a_pllg_disable()
373 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, in _gk20a_pllg_program_mnp()
418 nvkm_mask(device, SEL_VCO, 0, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); in _gk20a_pllg_program_mnp()
461 nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); in gk20a_pllg_disable()
618 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL); in gk20a_clk_init()
Dnv40.c190 nvkm_mask(device, 0x00c040, 0x00000333, 0x00000000); in nv40_clk_prog()
192 nvkm_mask(device, 0x004000, 0xc0070100, clk->npll_ctrl); in nv40_clk_prog()
193 nvkm_mask(device, 0x004008, 0xc007ffff, clk->spll); in nv40_clk_prog()
195 nvkm_mask(device, 0x00c040, 0x00000333, clk->ctrl); in nv40_clk_prog()
Dmcp77.c314 mast = nvkm_mask(device, 0xc054, 0x03400e70, 0x03400640); in mcp77_clk_prog()
320 nvkm_mask(device, 0x4028, 0x00070000, clk->cctrl); in mcp77_clk_prog()
337 nvkm_mask(device, 0x4020, 0x00070000, 0x00000000); in mcp77_clk_prog()
341 nvkm_mask(device, 0x4020, 0x00070000, clk->sctrl); in mcp77_clk_prog()
376 nvkm_mask(device, 0x4028, 0x80000000, 0x00000000); in mcp77_clk_prog()
381 nvkm_mask(device, 0x4020, 0x80000000, 0x00000000); in mcp77_clk_prog()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
Dpadgm204.c37 nvkm_mask(device, 0x00d97c + base, 0x00000001, 0x00000001); in gm204_i2c_pad_mode()
40 nvkm_mask(device, 0x00d970 + base, 0x0000c003, 0x0000c001); in gm204_i2c_pad_mode()
41 nvkm_mask(device, 0x00d97c + base, 0x00000001, 0x00000000); in gm204_i2c_pad_mode()
44 nvkm_mask(device, 0x00d970 + base, 0x0000c003, 0x00000002); in gm204_i2c_pad_mode()
45 nvkm_mask(device, 0x00d97c + base, 0x00000001, 0x00000000); in gm204_i2c_pad_mode()
Dpadg94.c37 nvkm_mask(device, 0x00e50c + base, 0x00000001, 0x00000001); in g94_i2c_pad_mode()
40 nvkm_mask(device, 0x00e500 + base, 0x0000c003, 0x0000c001); in g94_i2c_pad_mode()
41 nvkm_mask(device, 0x00e50c + base, 0x00000001, 0x00000000); in g94_i2c_pad_mode()
44 nvkm_mask(device, 0x00e500 + base, 0x0000c003, 0x00000002); in g94_i2c_pad_mode()
45 nvkm_mask(device, 0x00e50c + base, 0x00000001, 0x00000000); in g94_i2c_pad_mode()
Dauxg94.c36 nvkm_mask(device, 0x00e4e4 + (aux->ch * 0x50), 0x00310000, 0x00000000); in g94_i2c_aux_fini()
60 nvkm_mask(device, 0x00e4e4 + (aux->ch * 0x50), 0x00300000, ureq); in g94_i2c_aux_init()
137 stat = nvkm_mask(device, 0x00e4e8 + base, 0, 0); in g94_i2c_aux_xfer()
Dauxgm204.c36 nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00310000, 0x00000000); in gm204_i2c_aux_fini()
60 nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00300000, ureq); in gm204_i2c_aux_init()
137 stat = nvkm_mask(device, 0x00d958 + base, 0, 0); in gm204_i2c_aux_xfer()
Dbusnv4e.c37 nvkm_mask(device, bus->addr, 0x2f, state ? 0x21 : 0x01); in nv4e_i2c_bus_drive_scl()
45 nvkm_mask(device, bus->addr, 0x1f, state ? 0x11 : 0x01); in nv4e_i2c_bus_drive_sda()
Dbusgf119.c37 nvkm_mask(device, bus->addr, 0x00000001, state ? 0x00000001 : 0); in gf119_i2c_bus_drive_scl()
45 nvkm_mask(device, bus->addr, 0x00000002, state ? 0x00000002 : 0); in gf119_i2c_bus_drive_sda()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxgk104.c878 nvkm_mask(device, 0x418c6c, 0x00000001, 0x00000001); in gk104_grctx_generate_unkn()
879 nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010); in gk104_grctx_generate_unkn()
880 nvkm_mask(device, 0x41be08, 0x00000004, 0x00000004); in gk104_grctx_generate_unkn()
881 nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000); in gk104_grctx_generate_unkn()
882 nvkm_mask(device, 0x405800, 0x08000000, 0x08000000); in gk104_grctx_generate_unkn()
883 nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008); in gk104_grctx_generate_unkn()
950 nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */ in gk104_grctx_generate_rop_active_fbps()
951 nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */ in gk104_grctx_generate_rop_active_fbps()
986 nvkm_mask(device, 0x419f78, 0x00000001, 0x00000000); in gk104_grctx_generate_main()
993 nvkm_mask(device, 0x418800, 0x00200000, 0x00200000); in gk104_grctx_generate_main()
[all …]
Dctxgf108.c771 nvkm_mask(device, 0x418c6c, 0x00000001, 0x00000001); in gf108_grctx_generate_unkn()
772 nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010); in gf108_grctx_generate_unkn()
773 nvkm_mask(device, 0x419814, 0x00000004, 0x00000004); in gf108_grctx_generate_unkn()
774 nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000); in gf108_grctx_generate_unkn()
775 nvkm_mask(device, 0x405800, 0x08000000, 0x08000000); in gf108_grctx_generate_unkn()
776 nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008); in gf108_grctx_generate_unkn()
Dctxgm204.c944 nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */ in gm204_grctx_generate_rop_active_fbps()
945 nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */ in gm204_grctx_generate_rop_active_fbps()
1023 nvkm_mask(device, 0x418e94, 0xffffffff, 0xc4230000); in gm204_grctx_generate_main()
1024 nvkm_mask(device, 0x418e4c, 0xffffffff, 0x70000000); in gm204_grctx_generate_main()
Dnv40.c101 nvkm_mask(device, 0x400720, 0x00000001, 0x00000000); in nv40_gr_chan_fini()
107 nvkm_mask(device, 0x400310, 0x00000020, 0x00000020); in nv40_gr_chan_fini()
108 nvkm_mask(device, 0x400304, 0x00000001, 0x00000001); in nv40_gr_chan_fini()
119 nvkm_mask(device, 0x40032c, 0x01000000, 0x00000000); in nv40_gr_chan_fini()
123 nvkm_mask(device, 0x400330, 0x01000000, 0x00000000); in nv40_gr_chan_fini()
125 nvkm_mask(device, 0x400720, 0x00000001, 0x00000001); in nv40_gr_chan_fini()
263 nvkm_mask(device, 0x402000, 0, 0); in nv40_gr_intr()
Dnv10.c511 nvkm_mask(device, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100); in nv17_gr_mthd_lma_enable()
512 nvkm_mask(device, 0x4006b0, 0x08000000, 0x08000000); in nv17_gr_mthd_lma_enable()
856 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13); in nv10_gr_load_dma_vtxbuf()
863 nvkm_mask(device, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000); in nv10_gr_load_dma_vtxbuf()
864 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); in nv10_gr_load_dma_vtxbuf()
865 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); in nv10_gr_load_dma_vtxbuf()
904 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24); in nv10_gr_load_context()
905 nvkm_mask(device, NV10_PGRAPH_FFINTFC_ST2, 0x30000000, 0x00000000); in nv10_gr_load_context()
927 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); in nv10_gr_unload_context()
962 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); in nv10_gr_chan_fini()
[all …]
Dctxgm107.c993 nvkm_mask(device, 0x419e00, 0x00808080, 0x00808080); in gm107_grctx_generate_main()
994 nvkm_mask(device, 0x419ccc, 0x80000000, 0x80000000); in gm107_grctx_generate_main()
995 nvkm_mask(device, 0x419f80, 0x80000000, 0x80000000); in gm107_grctx_generate_main()
996 nvkm_mask(device, 0x419f88, 0x80000000, 0x80000000); in gm107_grctx_generate_main()
Dg84.c126 nvkm_mask(device, 0x400500, 0x00000001, 0x00000000); in g84_gr_tlb_flush()
170 nvkm_mask(device, 0x400500, 0x00000001, 0x00000001); in g84_gr_tlb_flush()
Dgm204.c254 nvkm_mask(device, 0x4188b0, 0x00040000, 0x00040000); in gm204_gr_init()
259 nvkm_mask(device, 0x100cc4, 0x00040000, 0x00040000); in gm204_gr_init()
310 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); in gm204_gr_init()
Dgk104.c246 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); in gk104_gr_init()
247 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); in gk104_gr_init()
Dctxgk20a.c58 nvkm_mask(device, 0x5044b0, 0x8000000, 0x8000000); in gk20a_grctx_generate_main()
Dnv04.c1094 nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24); in nv04_gr_load_context()
1095 nvkm_mask(device, NV04_PGRAPH_FFINTFC_ST2, 0xfff00000, 0x00000000); in nv04_gr_load_context()
1109 nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); in nv04_gr_unload_context()
1169 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); in nv04_gr_chan_fini()
1172 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); in nv04_gr_chan_fini()
1356 nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); in nv04_gr_init()
Dnv20.c37 nvkm_mask(device, 0x400720, 0x00000001, 0x00000000); in nv20_gr_chan_fini()
48 nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000); in nv20_gr_chan_fini()
50 nvkm_mask(device, 0x400720, 0x00000001, 0x00000001); in nv20_gr_chan_fini()
Dgm107.c374 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); in gm107_gr_init()
Dgk20a.c213 nvkm_mask(device, 0x503018, 0x1, 0x1); in gk20a_gr_init()
Dgf100.c1720 nvkm_mask(device, TPC_UNIT(0, 0, 0x05c), 0x00000001, 0x00000001); in gf100_gr_init()
1766 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); in gf100_gr_init()
1767 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); in gf100_gr_init()
Dctxgf100.c1360 nvkm_mask(device, 0x409b04, 0x80000000, 0x00000000); in gf100_grctx_generate()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramnv40.c119 nvkm_mask(device, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */ in nv40_ram_prog()
123 nvkm_mask(device, 0x00c040, 0x0000c000, 0x00000000); in nv40_ram_prog()
130 nvkm_mask(device, 0x004044, 0xc0771100, ram->ctrl); in nv40_ram_prog()
131 nvkm_mask(device, 0x00402c, 0xc0771100, ram->ctrl); in nv40_ram_prog()
137 nvkm_mask(device, 0x004038, 0xc0771100, ram->ctrl); in nv40_ram_prog()
140 nvkm_mask(device, 0x004020, 0xc0771100, ram->ctrl); in nv40_ram_prog()
145 nvkm_mask(device, 0x00c040, 0x0000c000, 0x0000c000); in nv40_ram_prog()
149 nvkm_mask(device, 0x100210, 0x80000000, 0x80000000); in nv40_ram_prog()
Drammcp77.c45 nvkm_mask(device, 0x100c14, 0x00000000, 0x00000001); in mcp77_ram_init()
47 nvkm_mask(device, 0x100c14, 0x00000000, 0x00000002); in mcp77_ram_init()
49 nvkm_mask(device, 0x100c14, 0x00000000, 0x00010000); in mcp77_ram_init()
Dramgt215.c200 nvkm_mask(device, 0x100674, 0x0000ffff, 0x00000000); in gt215_link_train()
201 nvkm_mask(device, 0x1005e4, 0x0000ffff, 0x00000000); in gt215_link_train()
202 nvkm_mask(device, 0x100b0c, 0x000000ff, 0x00000000); in gt215_link_train()
240 nvkm_mask(device, 0x616308, 0x10, 0x10); in gt215_link_train()
241 nvkm_mask(device, 0x616b08, 0x10, 0x10); in gt215_link_train()
309 nvkm_mask(device, 0x10f800, 0x00000001, 0x00000001); in gt215_link_train_init()
891 nvkm_mask(device, 0x001534, 0x2, 0x2); in gt215_ram_prog()
896 nvkm_mask(device, 0x002504, 0x1, 0x0); in gt215_ram_prog()
897 nvkm_mask(device, 0x001534, 0x2, 0x0); in gt215_ram_prog()
899 nvkm_mask(device, 0x616308, 0x10, 0x10); in gt215_ram_prog()
[all …]
Dgk20a.c28 nvkm_mask(device, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */ in gk20a_fb_init()
Dnv40.c49 nvkm_mask(fb->subdev.device, 0x10033c, 0x00008000, 0x00000000); in nv40_fb_init()
Dramgk104.c1173 nvkm_mask(device, 0x10f468, mask, data); in gk104_ram_prog_0()
1179 nvkm_mask(device, 0x10f420, mask, data); in gk104_ram_prog_0()
1185 nvkm_mask(device, 0x10f430, mask, data); in gk104_ram_prog_0()
1191 nvkm_mask(device, 0x10f400, mask, data); in gk104_ram_prog_0()
1197 nvkm_mask(device, 0x10f410, mask, data); in gk104_ram_prog_0()
1207 nvkm_mask(device, 0x10f440, mask, data); in gk104_ram_prog_0()
1221 nvkm_mask(device, 0x10f444, mask, data); in gk104_ram_prog_0()
1420 nvkm_mask(device, 0x10f65c, 0x000000f0, i << 4); in gk104_ram_init()
1429 nvkm_mask(device, 0x10f65c, 0x000000f0, save); in gk104_ram_init()
1430 nvkm_mask(device, 0x10f584, 0x11000000, 0x00000000); in gk104_ram_init()
[all …]
Dgf100.c58 nvkm_mask(device, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */ in gf100_fb_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dgf119.c61 nvkm_mask(device, 0x00d610 + (line * 0x04), 0x000000c0, data); in gf119_fan_pwm_ctrl()
99 nvkm_mask(device, 0x0200d8, 0x1fff, divs); /* keep the high bits */ in gf119_fan_pwm_set()
126 nvkm_mask(device, 0x00e720, 0x00000003, 0x00000002); in gf119_therm_init()
128 nvkm_mask(device, 0x00d79c, 0x000000ff, therm->fan->tach.line); in gf119_therm_init()
130 nvkm_mask(device, 0x00e720, 0x00000001, 0x00000001); in gf119_therm_init()
132 nvkm_mask(device, 0x00e720, 0x00000002, 0x00000000); in gf119_therm_init()
Dgt215.c48 nvkm_mask(device, 0x00e720, 0x00000003, 0x00000002); in gt215_therm_init()
51 nvkm_mask(device, 0x00e720, 0x001f0000, tach->line << 16); in gt215_therm_init()
52 nvkm_mask(device, 0x00e720, 0x00000001, 0x00000001); in gt215_therm_init()
54 nvkm_mask(device, 0x00e720, 0x00000002, 0x00000000); in gt215_therm_init()
Dnv40.c60 nvkm_mask(device, 0x15b8, 0x80000000, 0); in nv40_sensor_setup()
111 if (line == 2) nvkm_mask(device, 0x0010f0, 0x80000000, mask); in nv40_fan_pwm_ctrl()
112 else if (line == 9) nvkm_mask(device, 0x0015f4, 0x80000000, mask); in nv40_fan_pwm_ctrl()
154 nvkm_mask(device, 0x0010f0, 0x7fff7fff, (duty << 16) | divs); in nv40_fan_pwm_set()
158 nvkm_mask(device, 0x0015f4, 0x7fffffff, duty); in nv40_fan_pwm_set()
Dnv50.c61 nvkm_mask(device, ctrl, 0x00010001 << line, data << line); in nv50_fan_pwm_ctrl()
124 nvkm_mask(device, 0x20010, 0x40000000, 0x0); in nv50_sensor_setup()
Dg84.c47 nvkm_mask(device, 0x20008, 0x80008000, 0x80000000); in g84_sensor_setup()
48 nvkm_mask(device, 0x2000c, 0x80000003, 0x00000000); in g84_sensor_setup()
Dgm107.c46 nvkm_mask(device, 0x10eb10, 0x1fff, divs); /* keep the high bits */ in gm107_fan_pwm_set()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
Dgf119.c49 nvkm_mask(device, 0x00d610 + (line * 4), 0xff, unk0); in gf119_gpio_reset()
51 nvkm_mask(device, 0x00d740 + (unk1 * 4), 0xff, line); in gf119_gpio_reset()
60 nvkm_mask(device, 0x00d610 + (line * 4), 0x00003000, data); in gf119_gpio_drive()
61 nvkm_mask(device, 0x00d604, 0x00000001, 0x00000001); /* update? */ in gf119_gpio_drive()
Dnv50.c53 nvkm_mask(device, reg, 0x00010001 << lsh, val << lsh); in nv50_gpio_reset()
79 nvkm_mask(device, reg, 3 << shift, (((dir ^ 1) << 1) | out) << shift); in nv50_gpio_drive()
Dnv10.c78 nvkm_mask(device, reg, mask << line, data << line); in nv10_gpio_drive()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dgf100.c39 nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); in gf100_fifo_uevent_init()
46 nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); in gf100_fifo_uevent_fini()
133 nvkm_mask(device, 0x002630, engm, engm); in gf100_fifo_recover_work()
144 nvkm_mask(device, 0x002630, engm, 0x00000000); in gf100_fifo_recover_work()
159 nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000); in gf100_fifo_recover()
320 nvkm_mask(device, 0x001704, 0x00000000, 0x00000000); in gf100_fifo_intr_fault()
323 nvkm_mask(device, 0x001714, 0x00000000, 0x00000000); in gf100_fifo_intr_fault()
326 nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); in gf100_fifo_intr_fault()
435 nvkm_mask(device, 0x002628, ints, 0); in gf100_fifo_intr_engine_unit()
522 nvkm_mask(device, 0x002140, stat, 0x00000000); in gf100_fifo_intr()
[all …]
Dgk104.c39 nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); in gk104_fifo_uevent_fini()
46 nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); in gk104_fifo_uevent_init()
108 nvkm_mask(device, 0x002630, engm, engm); in gk104_fifo_recover_work()
119 nvkm_mask(device, 0x002630, engm, 0x00000000); in gk104_fifo_recover_work()
134 nvkm_mask(device, 0x800004 + (chid * 0x08), 0x00000800, 0x00000800); in gk104_fifo_recover()
385 nvkm_mask(device, 0x001704, 0x00000000, 0x00000000); in gk104_fifo_intr_fault()
388 nvkm_mask(device, 0x001714, 0x00000000, 0x00000000); in gk104_fifo_intr_fault()
391 nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); in gk104_fifo_intr_fault()
624 nvkm_mask(device, 0x002140, stat, 0x00000000); in gk104_fifo_intr()
636 nvkm_mask(device, 0x002140, 0x10000000, 0x10000000); in gk104_fifo_fini()
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Dg84.c31 nvkm_mask(device, 0x002140, 0x40000000, 0x00000000); in g84_fifo_uevent_fini()
38 nvkm_mask(device, 0x002140, 0x40000000, 0x40000000); in g84_fifo_uevent_init()
Ddmanv40.c71 nvkm_mask(device, 0x002500, 0x00000001, 0x00000000); in nv40_fifo_dma_engine_fini()
80 nvkm_mask(device, 0x002500, 0x00000001, 0x00000001); in nv40_fifo_dma_engine_fini()
102 nvkm_mask(device, 0x002500, 0x00000001, 0x00000000); in nv40_fifo_dma_engine_init()
111 nvkm_mask(device, 0x002500, 0x00000001, 0x00000001); in nv40_fifo_dma_engine_init()
Ddmanv04.c89 nvkm_mask(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0); in nv04_fifo_dma_fini()
91 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); in nv04_fifo_dma_fini()
115 nvkm_mask(device, NV04_PFIFO_MODE, 1 << chan->base.chid, 0); in nv04_fifo_dma_fini()
129 nvkm_mask(device, NV04_PFIFO_MODE, mask, mask); in nv04_fifo_dma_init()
Dnv50.c82 nvkm_mask(device, 0x000200, 0x00000100, 0x00000000); in nv50_fifo_init()
83 nvkm_mask(device, 0x000200, 0x00000100, 0x00000100); in nv50_fifo_init()
Dgpfifogk104.c155 nvkm_mask(device, 0x800004 + coff, 0x00000800, 0x00000800); in gk104_fifo_gpfifo_fini()
171 nvkm_mask(device, 0x800004 + coff, 0x000f0000, chan->engine << 16); in gk104_fifo_gpfifo_init()
176 nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400); in gk104_fifo_gpfifo_init()
178 nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400); in gk104_fifo_gpfifo_init()
Dnv04.c59 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000); in nv04_fifo_pause()
91 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001); in nv04_fifo_start()
289 nvkm_mask(device, NV03_PFIFO_INTR_EN_0, stat, 0x00000000); in nv04_fifo_intr()
Dchannv50.c72 me = nvkm_mask(device, 0x00b860, 0x00000001, 0x00000001); in nv50_fifo_chan_engine_fini()
187 nvkm_mask(device, 0x002600 + (chid * 4), 0x80000000, 0x00000000); in nv50_fifo_chan_fini()
Dchang84.c106 save = nvkm_mask(device, 0x002520, 0x0000003f, 1 << engn); in g84_fifo_chan_engine_fini()
Dgpfifogf100.c142 nvkm_mask(device, 0x003004 + coff, 0x00000001, 0x00000000); in gf100_fifo_gpfifo_fini()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/bus/
Dnv50.c36 nvkm_mask(device, 0x001098, 0x00000008, 0x00000000); in nv50_bus_hwsq_exec()
40 nvkm_mask(device, 0x001098, 0x00000018, 0x00000018); in nv50_bus_hwsq_exec()
81 nvkm_mask(device, 0x001140, stat, 0); in nv50_bus_intr()
Dg94.c35 nvkm_mask(device, 0x001098, 0x00000008, 0x00000000); in g94_bus_hwsq_exec()
40 nvkm_mask(device, 0x001098, 0x00000018, 0x00000018); in g94_bus_hwsq_exec()
Dnv04.c54 nvkm_mask(device, 0x001140, stat, 0x00000000); in nv04_bus_intr()
Dgf100.c53 nvkm_mask(device, 0x001140, stat, 0x00000000); in gf100_bus_intr()
Dnv31.c66 nvkm_mask(device, 0x001140, stat, 0x00000000); in nv31_bus_intr()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/
Dgf100.c35 fuse_enable = nvkm_mask(device, 0x022400, 0x800, 0x800); in gf100_fuse_read()
36 unk = nvkm_mask(device, 0x021000, 0x1, 0x1); in gf100_fuse_read()
Dnv50.c35 fuse_enable = nvkm_mask(device, 0x001084, 0x800, 0x800); in nv50_fuse_read()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv44.c76 nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000000); in nv44_mpeg_chan_fini()
78 nvkm_mask(device, 0x00b318, 0x80000000, 0x00000000); in nv44_mpeg_chan_fini()
79 nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000001); in nv44_mpeg_chan_fini()
170 nvkm_mask(device, 0x00b308, 0x00000000, 0x00000000); in nv44_mpeg_intr()
Dnv40.c47 nvkm_mask(device, 0x00b300, 0x00030000, (dma0 & 0x00030000)); in nv40_mpeg_mthd_dma()
53 nvkm_mask(device, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2); in nv40_mpeg_mthd_dma()
Dnv31.c140 nvkm_mask(device, 0x00b300, 0x00010000, in nv31_mpeg_mthd_dma()
147 nvkm_mask(device, 0x00b300, 0x00020000, in nv31_mpeg_mthd_dma()
196 nvkm_mask(device, 0x00b308, 0x00000000, 0x00000000); in nv31_mpeg_intr()
234 nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000001); in nv31_mpeg_init()
Dnv50.c102 nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000001); in nv50_mpeg_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/
Dgm107.c58 nvkm_mask(device, 0x17e338, 0x0000000f, i); in gm107_ltc_zbc_clear_color()
69 nvkm_mask(device, 0x17e338, 0x0000000f, i); in gm107_ltc_zbc_clear_depth()
128 nvkm_mask(device, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); in gm107_ltc_init()
Dgf100.c59 nvkm_mask(device, 0x17ea44, 0x0000000f, i); in gf100_ltc_zbc_clear_color()
70 nvkm_mask(device, 0x17ea44, 0x0000000f, i); in gf100_ltc_zbc_clear_depth()
232 nvkm_mask(device, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */ in gf100_ltc_init()
235 nvkm_mask(device, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); in gf100_ltc_init()
Dgk104.c35 nvkm_mask(device, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); in gk104_ltc_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
Dagp.c77 save[1] = nvkm_mask(device, 0x000200, 0x00011100, 0x00000000); in nvkm_agp_preinit()
78 nvkm_mask(device, 0x000200, 0x00011100, save[1]); in nvkm_agp_preinit()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/core/
Dsubdev.c103 nvkm_mask(device, 0x000200, pmc_enable, 0x00000000); in nvkm_subdev_fini()
104 nvkm_mask(device, 0x000200, pmc_enable, pmc_enable); in nvkm_subdev_fini()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
Dgf100.c124 nvkm_mask(device, 0x000200, 0x00000100, 0x00000000); in gf100_bar_init()
125 nvkm_mask(device, 0x000200, 0x00000100, 0x00000100); in gf100_bar_init()
Dnv50.c154 nvkm_mask(device, 0x000200, 0x00000100, 0x00000000); in nv50_bar_init()
155 nvkm_mask(device, 0x000200, 0x00000100, 0x00000100); in nv50_bar_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/pm/
Dgf100.c179 nvkm_mask(device, 0x000200, 0x10000000, 0x00000000); in gf100_pm_fini()
180 nvkm_mask(device, 0x000200, 0x10000000, 0x10000000); in gf100_pm_fini()
Dbase.c156 nvkm_mask(device, src->addr, mask, value); in nvkm_perfsrc_enable()
194 nvkm_mask(device, src->addr, mask, 0); in nvkm_perfsrc_disable()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
Dnv41.c114 nvkm_mask(device, 0x10008c, 0x00000100, 0x00000100); in nv41_mmu_init()
Dnv44.c207 nvkm_mask(device, 0x10008c, 0x00000200, 0x00000200); in nv44_mmu_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/
Dxtensa.c74 nvkm_mask(device, xtensa->addr + 0xd94, 0, xtensa->func->fifo_val); in nvkm_xtensa_intr()
Dfalcon.c110 nvkm_mask(device, base + 0x048, 0x00000003, 0x00000000); in nvkm_falcon_fini()
/linux-4.4.14/drivers/gpu/drm/nouveau/include/nvkm/core/
Ddevice.h219 #define nvkm_mask(d,a,m,v) ({ \ macro