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Searched refs:num_levels (Results 1 – 24 of 24) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
Dsumo_dpm.c348 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
355 for (i = 0; i < ps->num_levels - 1; i++) in sumo_program_bsp()
409 for (i = 0; i < ps->num_levels; i++) { in sumo_program_at()
410 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi; in sumo_program_at()
424 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) | in sumo_program_at()
425 CG_L(m_a * l[ps->num_levels - 1] / 100); in sumo_program_at()
671 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1]; in sumo_patch_boost_state()
744 dpm_ctrl4 |= (1 << (new_ps->num_levels - 1)); in sumo_program_wl()
760 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; in sumo_program_power_levels_0_to_n()
762 for (i = 0; i < new_ps->num_levels; i++) { in sumo_program_power_levels_0_to_n()
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Dtrinity_dpm.c845 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; in trinity_program_power_levels_0_to_n()
847 for (i = 0; i < new_ps->num_levels; i++) { in trinity_program_power_levels_0_to_n()
852 for (i = new_ps->num_levels; i < n_current_state_levels; i++) in trinity_program_power_levels_0_to_n()
968 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
969 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
982 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
983 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
1208 if (ps->num_levels <= 1) in trinity_dpm_force_performance_level()
1215 ret = trinity_dpm_n_levels_disabled(rdev, ps->num_levels - 1); in trinity_dpm_force_performance_level()
1219 for (i = 0; i < ps->num_levels; i++) { in trinity_dpm_force_performance_level()
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Dr100_track.h41 unsigned num_levels; member
Dtrinity_dpm.h48 u32 num_levels; member
Dkv_dpm.c1724 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1731 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1750 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1759 new_ps->levels[new_ps->num_levels -1].sclk)) in kv_set_valid_clock_range()
2187 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2193 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2205 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2216 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2578 ps->num_levels = 1; in kv_patch_boot_state()
2623 ps->num_levels = index + 1; in kv_parse_pplib_clock_info()
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Dkv_dpm.h83 u32 num_levels; member
Dsumo_dpm.h46 u32 num_levels; member
Dr200.c419 track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK) in r200_packet0_check()
Dr100.c1811 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) in r100_packet0_check()
2086 DRM_ERROR("num levels %d\n", t->num_levels); in r100_cs_track_texture_print()
2175 for (i = 0; i <= track->textures[u].num_levels; i++) { in r100_cs_track_texture_check()
2427 track->textures[i].num_levels = 12; in r100_cs_track_clear()
Dr300.c1073 track->textures[i].num_levels = tmp; in r300_packet0_check()
Dsi_dpm.c3909 u32 data, num_bits, num_levels; in si_validate_phase_shedding_tables() local
3921 num_levels = (1 << num_bits); in si_validate_phase_shedding_tables()
3923 if (table->count != num_levels) in si_validate_phase_shedding_tables()
3926 if (limits->count != (num_levels - 1)) in si_validate_phase_shedding_tables()
/linux-4.4.14/arch/arm64/kernel/
Dcacheinfo.c102 this_cpu_ci->num_levels = level; in __init_cache_level()
114 for (idx = 0, level = 1; level <= this_cpu_ci->num_levels && in __populate_cache_leaves()
/linux-4.4.14/arch/s390/kernel/
Dcache.c153 this_cpu_ci->num_levels = level; in init_cache_level()
169 for (idx = 0, level = 0; level < this_cpu_ci->num_levels && in populate_cache_leaves()
/linux-4.4.14/include/linux/
Dcacheinfo.h72 unsigned int num_levels; member
/linux-4.4.14/lib/
Ddecompress_unlzma.c201 rc_bit_tree_decode(struct rc *rc, uint16_t *p, int num_levels, int *symbol) in rc_bit_tree_decode() argument
203 int i = num_levels; in rc_bit_tree_decode()
208 *symbol -= 1 << num_levels; in rc_bit_tree_decode()
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Dkv_dpm.h109 u32 num_levels; member
Dcz_dpm.h94 uint32_t num_levels; member
Dkv_dpm.c1820 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1827 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1846 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1855 new_ps->levels[new_ps->num_levels -1].sclk)) in kv_set_valid_clock_range()
2281 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2287 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2299 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2310 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2675 ps->num_levels = 1; in kv_patch_boot_state()
2720 ps->num_levels = index + 1; in kv_parse_pplib_clock_info()
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Dcz_dpm.c226 ps->num_levels = 1; in cz_patch_boot_state()
249 ps->num_levels = index + 1; in cz_parse_pplib_clock_info()
571 for (i = 0; i < ps->num_levels; i++) { in cz_dpm_print_power_state()
1792 return requested_state->levels[requested_state->num_levels - 1].sclk; in cz_dpm_get_sclk()
/linux-4.4.14/drivers/gpu/drm/i915/
Di915_debugfs.c4336 int num_levels; in wm_latency_show() local
4339 num_levels = 3; in wm_latency_show()
4341 num_levels = 1; in wm_latency_show()
4343 num_levels = ilk_wm_max_level(dev) + 1; in wm_latency_show()
4347 for (level = 0; level < num_levels; level++) { in wm_latency_show()
4450 int num_levels; in wm_latency_write() local
4456 num_levels = 3; in wm_latency_write()
4458 num_levels = 1; in wm_latency_write()
4460 num_levels = ilk_wm_max_level(dev) + 1; in wm_latency_write()
4473 if (ret != num_levels) in wm_latency_write()
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Dintel_pm.c1037 for (level = 0; level < wm_state->num_levels; level++) { in vlv_invert_wms()
1077 wm_state->num_levels = to_i915(dev)->wm.max_level + 1; in vlv_compute_wm()
1087 for (level = 0; level < wm_state->num_levels; level++) { in vlv_compute_wm()
1101 for (level = 0; level < wm_state->num_levels; level++) { in vlv_compute_wm()
1127 wm_state->num_levels = level; in vlv_compute_wm()
1136 for (level = 0; level < wm_state->num_levels; level++) in vlv_compute_wm()
1141 for (level = 0; level < wm_state->num_levels; level++) in vlv_compute_wm()
1148 for (level = 0; level < wm_state->num_levels; level++) in vlv_compute_wm()
1157 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) { in vlv_compute_wm()
1274 wm->level = min_t(int, wm->level, wm_state->num_levels - 1); in vlv_merge_wm()
Dintel_drv.h477 uint8_t num_levels; member
/linux-4.4.14/arch/x86/kernel/cpu/
Dintel_cacheinfo.c918 this_cpu_ci->num_levels = 3; in __init_cache_level()
/linux-4.4.14/drivers/net/wireless/brcm80211/brcmsmac/phy/
Dphy_lcn.c3667 wlc_lcnphy_a1(struct brcms_phy *pi, int cal_type, int num_levels, in wlc_lcnphy_a1() argument
3720 if (num_levels == 0) { in wlc_lcnphy_a1()
3722 num_levels = 4; in wlc_lcnphy_a1()
3724 num_levels = 9; in wlc_lcnphy_a1()
3745 for (phy_c8 = 0; phy_c7 != 0 && phy_c8 < num_levels; phy_c8++) { in wlc_lcnphy_a1()