Searched refs:gpc_base (Results 1 - 4 of 4) sorted by relevance

/linux-4.4.14/drivers/irqchip/
H A Dirq-imx-gpcv2.c23 void __iomem *gpc_base; member in struct:gpcv2_irqchip_data
56 reg = cd->gpc_base + cd->cpu2wakeup + i * 4; gpcv2_wakeup_source_save()
75 reg = cd->gpc_base + cd->cpu2wakeup + i * 4; gpcv2_wakeup_source_restore()
94 reg = cd->gpc_base + cd->cpu2wakeup + idx * 4; imx_gpcv2_irq_set_wake()
116 reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4; imx_gpcv2_irq_unmask()
132 reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4; imx_gpcv2_irq_mask()
233 cd->gpc_base = of_iomap(node, 0); imx_gpcv2_irqchip_init()
234 if (!cd->gpc_base) { imx_gpcv2_irqchip_init()
243 iounmap(cd->gpc_base); imx_gpcv2_irqchip_init()
251 writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE0 + i * 4); imx_gpcv2_irqchip_init()
252 writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE1 + i * 4); imx_gpcv2_irqchip_init()
264 writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup); imx_gpcv2_irqchip_init()
/linux-4.4.14/arch/arm/mach-imx/
H A Dgpc.c54 static void __iomem *gpc_base; variable
61 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR); imx_gpc_set_arm_power_up_timing()
67 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR); imx_gpc_set_arm_power_down_timing()
72 writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN); imx_gpc_set_arm_power_in_lpm()
77 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; imx_gpc_pre_suspend()
92 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; imx_gpc_post_resume()
120 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; imx_gpc_mask_all()
132 void __iomem *reg_imr1 = gpc_base + GPC_IMR1; imx_gpc_restore_all()
144 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; imx_gpc_hwirq_unmask()
155 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; imx_gpc_hwirq_mask()
258 gpc_base = of_iomap(node, 0); imx_gpc_init()
259 if (WARN_ON(!gpc_base)) imx_gpc_init()
266 iounmap(gpc_base); imx_gpc_init()
272 writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4); imx_gpc_init()
290 gpc_base = of_iomap(np, 0); imx_gpc_check_dt()
300 val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR); _imx6q_pm_pu_power_off()
305 writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN); _imx6q_pm_pu_power_off()
308 val = readl_relaxed(gpc_base + GPC_CNTR); _imx6q_pm_pu_power_off()
310 writel_relaxed(val, gpc_base + GPC_CNTR); _imx6q_pm_pu_power_off()
346 writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN); imx6q_pm_pu_power_on()
349 val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR); imx6q_pm_pu_power_on()
354 val = readl_relaxed(gpc_base + GPC_CNTR); imx6q_pm_pu_power_on()
356 writel_relaxed(val, gpc_base + GPC_CNTR); imx6q_pm_pu_power_on()
H A Dpm-imx5.c141 static void __iomem *gpc_base; variable
160 arm_srpgcr = __raw_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) & mx5_cpu_lp_set()
162 empgc0 = __raw_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) & mx5_cpu_lp_set()
164 empgc1 = __raw_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) & mx5_cpu_lp_set()
201 __raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR); mx5_cpu_lp_set()
202 __raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR); mx5_cpu_lp_set()
208 __raw_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); mx5_cpu_lp_set()
209 __raw_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); mx5_cpu_lp_set()
231 __raw_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); mx5_suspend_enter()
232 __raw_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); mx5_suspend_enter()
394 gpc_base = ioremap(data->gpc_addr, SZ_16K); imx5_pm_common_init()
395 WARN_ON(!ccm_base || !cortex_base || !gpc_base); imx5_pm_common_init()
H A Dpm-imx6.c214 struct imx6_pm_base gpc_base; member in struct:imx6_cpu_pm_info
529 ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat); imx6q_suspend_init()
564 iounmap(&pm_info->gpc_base.vbase); imx6q_suspend_init()

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