54 static void __iomem *gpc_base;  variable
61 		(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);  in imx_gpc_set_arm_power_up_timing()
67 		(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);  in imx_gpc_set_arm_power_down_timing()
72 	writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);  in imx_gpc_set_arm_power_in_lpm()
77 	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;  in imx_gpc_pre_suspend()
92 	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;  in imx_gpc_post_resume()
120 	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;  in imx_gpc_mask_all()
132 	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;  in imx_gpc_restore_all()
144 	reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;  in imx_gpc_hwirq_unmask()
155 	reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;  in imx_gpc_hwirq_mask()
258 	gpc_base = of_iomap(node, 0);  in imx_gpc_init()
259 	if (WARN_ON(!gpc_base))  in imx_gpc_init()
266 		iounmap(gpc_base);  in imx_gpc_init()
272 		writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);  in imx_gpc_init()
290 		gpc_base = of_iomap(np, 0);  in imx_gpc_check_dt()
300 	val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);  in _imx6q_pm_pu_power_off()
305 	writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);  in _imx6q_pm_pu_power_off()
308 	val = readl_relaxed(gpc_base + GPC_CNTR);  in _imx6q_pm_pu_power_off()
310 	writel_relaxed(val, gpc_base + GPC_CNTR);  in _imx6q_pm_pu_power_off()
346 	writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);  in imx6q_pm_pu_power_on()
349 	val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);  in imx6q_pm_pu_power_on()
354 	val = readl_relaxed(gpc_base + GPC_CNTR);  in imx6q_pm_pu_power_on()
356 	writel_relaxed(val, gpc_base + GPC_CNTR);  in imx6q_pm_pu_power_on()