| /linux-4.4.14/drivers/gpu/drm/nouveau/ |
| D | nouveau_dp.c | 34 nouveau_dp_probe_oui(struct drm_device *dev, struct nvkm_i2c_aux *aux, u8 *dpcd) in nouveau_dp_probe_oui() argument
39 if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in nouveau_dp_probe_oui()
58 u8 *dpcd = nv_encoder->dp.dpcd; in nouveau_dp_detect() local
65 ret = nvkm_rdaux(aux, DP_DPCD_REV, dpcd, 8); in nouveau_dp_detect()
69 nv_encoder->dp.link_bw = 27000 * dpcd[1]; in nouveau_dp_detect()
70 nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; in nouveau_dp_detect()
73 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]); in nouveau_dp_detect()
86 nouveau_dp_probe_oui(dev, aux, dpcd); in nouveau_dp_detect()
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| D | nouveau_encoder.h | 60 u8 dpcd[8]; member
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| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | atombios_dp.c | 269 const u8 dpcd[DP_DPCD_SIZE], in amdgpu_atombios_dp_get_dp_lane_number()
273 int max_link_rate = drm_dp_max_link_rate(dpcd); in amdgpu_atombios_dp_get_dp_lane_number()
274 int max_lane_num = drm_dp_max_lane_count(dpcd); in amdgpu_atombios_dp_get_dp_lane_number()
288 const u8 dpcd[DP_DPCD_SIZE], in amdgpu_atombios_dp_get_dp_link_clock()
298 lane_num = amdgpu_atombios_dp_get_dp_lane_number(connector, dpcd, pix_clock); in amdgpu_atombios_dp_get_dp_link_clock()
311 return drm_dp_max_link_rate(dpcd); in amdgpu_atombios_dp_get_dp_link_clock()
346 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in amdgpu_atombios_dp_probe_oui()
368 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in amdgpu_atombios_dp_get_dpcd()
370 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), in amdgpu_atombios_dp_get_dpcd()
371 dig_connector->dpcd); in amdgpu_atombios_dp_get_dpcd()
[all …]
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| D | amdgpu_mode.h | 453 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
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| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | dport.c | 85 outp->dpcd[DPCD_RC02] & in dp_set_link_config()
98 if (outp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP) in dp_set_link_config()
171 if (outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL]) in dp_link_train_update()
172 mdelay(outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4); in dp_link_train_update()
234 if (outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED) in dp_link_train_eq()
339 outp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED; in nvkm_dp_train()
340 if ((outp->dpcd[2] & 0x1f) > outp->base.info.dpconf.link_nr) { in nvkm_dp_train()
341 outp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT; in nvkm_dp_train()
342 outp->dpcd[2] |= outp->base.info.dpconf.link_nr; in nvkm_dp_train()
344 if (outp->dpcd[1] > outp->base.info.dpconf.link_bw) in nvkm_dp_train()
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| D | outpdp.c | 85 if (outp->dpcd[DPCD_RC00_DPCD_REV] == 0x00) { in nvkm_output_dp_train()
86 outp->dpcd[DPCD_RC01_MAX_LINK_RATE] = in nvkm_output_dp_train()
88 outp->dpcd[DPCD_RC02] = in nvkm_output_dp_train()
119 if (!nvkm_rdaux(aux, DPCD_RC00_DPCD_REV, outp->dpcd, in nvkm_output_dp_enable()
120 sizeof(outp->dpcd))) { in nvkm_output_dp_enable()
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| D | outpdp.h | 30 u8 dpcd[16]; member
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| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| D | atombios_dp.c | 316 const u8 dpcd[DP_DPCD_SIZE]) in radeon_dp_get_max_link_rate()
321 max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000); in radeon_dp_get_max_link_rate()
323 max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000); in radeon_dp_get_max_link_rate()
333 const u8 dpcd[DP_DPCD_SIZE], in radeon_dp_get_dp_lane_number()
337 int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd); in radeon_dp_get_dp_lane_number()
338 int max_lane_num = drm_dp_max_lane_count(dpcd); in radeon_dp_get_dp_lane_number()
352 const u8 dpcd[DP_DPCD_SIZE], in radeon_dp_get_dp_link_clock()
362 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); in radeon_dp_get_dp_link_clock()
375 return radeon_dp_get_max_link_rate(connector, dpcd); in radeon_dp_get_dp_link_clock()
410 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in radeon_dp_probe_oui()
[all …]
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| D | radeon_dp_mst.c | 530 dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd); in radeon_mst_mode_fixup()
532 dig_connector->dpcd); in radeon_mst_mode_fixup()
683 if (dig_connector->dpcd[DP_DPCD_REV] < 0x12) in radeon_dp_mst_probe()
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| D | radeon_mode.h | 489 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
761 const u8 *dpcd);
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| /linux-4.4.14/include/drm/ |
| D | drm_dp_helper.h | 589 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
590 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
623 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_link_rate()
625 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); in drm_dp_max_link_rate()
629 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_lane_count()
631 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in drm_dp_max_lane_count()
635 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_enhanced_frame_cap()
637 return dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_enhanced_frame_cap()
638 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); in drm_dp_enhanced_frame_cap()
642 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_tps3_supported()
[all …]
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| D | drm_dp_mst_helper.h | 436 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
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| /linux-4.4.14/drivers/gpu/drm/gma500/ |
| D | cdv_intel_dp.c | 265 uint8_t dpcd[4]; member
328 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { in cdv_intel_dp_max_lane_count()
329 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; in cdv_intel_dp_max_lane_count()
344 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; in cdv_intel_dp_max_link_bw()
1078 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && in cdv_intel_dp_mode_set()
1079 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { in cdv_intel_dp_mode_set()
1114 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in cdv_intel_dp_sink_dpms()
1708 if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd, in cdv_dp_detect()
1709 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) in cdv_dp_detect()
1711 if (intel_dp->dpcd[DP_DPCD_REV] != 0) in cdv_dp_detect()
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| /linux-4.4.14/drivers/gpu/drm/ |
| D | drm_dp_helper.c | 118 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { in drm_dp_link_train_clock_recovery_delay()
119 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) in drm_dp_link_train_clock_recovery_delay()
122 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); in drm_dp_link_train_clock_recovery_delay()
126 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { in drm_dp_link_train_channel_eq_delay()
127 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) in drm_dp_link_train_channel_eq_delay()
130 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); in drm_dp_link_train_channel_eq_delay()
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| D | drm_dp_mst_topology.c | 2024 ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE); in drm_dp_mst_topology_mgr_set_mst()
2030 if (!drm_dp_get_vc_payload_bw(mgr->dpcd[1], in drm_dp_mst_topology_mgr_set_mst()
2031 mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK, in drm_dp_mst_topology_mgr_set_mst()
2129 sret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE); in drm_dp_mst_topology_mgr_resume()
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| /linux-4.4.14/drivers/gpu/drm/i915/ |
| D | intel_dp.c | 141 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; in intel_dp_max_link_bw()
168 sink_max = drm_dp_max_lane_count(intel_dp->dpcd); in intel_dp_max_lane_count()
1629 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_dp_prepare()
1639 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_dp_prepare()
1655 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_dp_prepare()
2203 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in intel_dp_sink_dpms()
3711 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_dp_link_training_clock_recovery()
3738 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); in intel_dp_link_training_clock_recovery()
3824 drm_dp_tps3_supported(intel_dp->dpcd)) in intel_dp_link_training_channel_equalization()
3848 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); in intel_dp_link_training_channel_equalization()
[all …]
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| D | intel_dp_mst.c | 57 lane_count = drm_dp_max_lane_count(intel_dp->dpcd); in intel_dp_mst_compute_config()
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| D | intel_drv.h | 738 uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; member
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| D | intel_ddi.c | 3071 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_ddi_prepare_link_retrain()
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| D | i915_debugfs.c | 2862 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); in intel_dp_info()
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| /linux-4.4.14/drivers/gpu/drm/msm/edp/ |
| D | edp_ctrl.c | 106 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
625 drm_dp_link_train_clock_recovery_delay(ctrl->dpcd); in edp_start_link_train_1()
682 drm_dp_link_train_channel_eq_delay(ctrl->dpcd); in edp_start_link_train_2()
760 drm_dp_link_train_channel_eq_delay(ctrl->dpcd); in edp_clear_training_pattern()
1201 if (drm_dp_dpcd_read(ctrl->drm_aux, DP_DPCD_REV, ctrl->dpcd, in msm_edp_ctrl_panel_connected()
1204 memset(ctrl->dpcd, 0, DP_RECEIVER_CAP_SIZE); in msm_edp_ctrl_panel_connected()
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| /linux-4.4.14/Documentation/DocBook/ |
| D | gpu.xml.db | 344 API-drm-dp-dpcd-readb
345 API-drm-dp-dpcd-writeb
346 API-drm-dp-dpcd-read
347 API-drm-dp-dpcd-write
348 API-drm-dp-dpcd-read-link-status
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