316 				const u8 dpcd[DP_DPCD_SIZE])  in radeon_dp_get_max_link_rate()
321 		max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000);  in radeon_dp_get_max_link_rate()
323 		max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000);  in radeon_dp_get_max_link_rate()
333 					const u8 dpcd[DP_DPCD_SIZE],  in radeon_dp_get_dp_lane_number()
337 	int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd);  in radeon_dp_get_dp_lane_number()
338 	int max_lane_num = drm_dp_max_lane_count(dpcd);  in radeon_dp_get_dp_lane_number()
352 				       const u8 dpcd[DP_DPCD_SIZE],  in radeon_dp_get_dp_link_clock()
362 	lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);  in radeon_dp_get_dp_link_clock()
375 	return radeon_dp_get_max_link_rate(connector, dpcd);  in radeon_dp_get_dp_link_clock()
410 	if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))  in radeon_dp_probe_oui()
432 			memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);  in radeon_dp_getdpcd()
434 			DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),  in radeon_dp_getdpcd()
435 				      dig_connector->dpcd);  in radeon_dp_getdpcd()
442 	dig_connector->dpcd[0] = 0;  in radeon_dp_getdpcd()
502 			radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);  in radeon_dp_set_link_config()
504 			radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);  in radeon_dp_set_link_config()
524 		radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);  in radeon_dp_mode_valid_helper()
558 	if (dig_connector->dpcd[0] >= 0x11) {  in radeon_dp_set_rx_power_state()
574 	u8 dpcd[DP_RECEIVER_CAP_SIZE];  member
639 	if (dp_info->dpcd[3] & 0x1)  in radeon_dp_link_train_init()
651 	if (drm_dp_enhanced_frame_cap(dp_info->dpcd))  in radeon_dp_link_train_init()
712 		drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);  in radeon_dp_link_train_cr()
775 		drm_dp_link_train_channel_eq_delay(dp_info->dpcd);  in radeon_dp_link_train_ce()
871 	memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);  in radeon_dp_link_train()