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Searched refs:div_reg (Results 1 – 19 of 19) sorted by relevance

/linux-4.4.14/drivers/clk/socfpga/
Dclk-periph.c36 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
37 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
71 u32 div_reg[3]; in __socfpga_periph_init() local
81 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
83 periph_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in __socfpga_periph_init()
84 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
85 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
87 periph_clk->div_reg = NULL; in __socfpga_periph_init()
Dclk-periph-a10.c39 } else if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
40 div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
81 u32 div_reg[3]; in __socfpga_periph_init() local
91 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
93 periph_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_periph_init()
94 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
95 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
97 periph_clk->div_reg = NULL; in __socfpga_periph_init()
Dclk-gate-a10.c40 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
41 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
109 u32 div_reg[3]; in __socfpga_gate_init() local
142 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_gate_init()
144 socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_gate_init()
145 socfpga_clk->shift = div_reg[1]; in __socfpga_gate_init()
146 socfpga_clk->width = div_reg[2]; in __socfpga_gate_init()
148 socfpga_clk->div_reg = NULL; in __socfpga_gate_init()
Dclk-gate.c106 else if (socfpgaclk->div_reg) { in socfpga_clk_recalc_rate()
107 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_recalc_rate()
110 if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_recalc_rate()
183 u32 div_reg[3]; in __socfpga_gate_init() local
215 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_gate_init()
217 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in __socfpga_gate_init()
218 socfpga_clk->shift = div_reg[1]; in __socfpga_gate_init()
219 socfpga_clk->width = div_reg[2]; in __socfpga_gate_init()
221 socfpga_clk->div_reg = NULL; in __socfpga_gate_init()
Dclk.h53 void __iomem *div_reg; member
64 void __iomem *div_reg; member
/linux-4.4.14/sound/soc/jz4740/
Djz4740-i2s.c260 uint32_t ctrl, div_reg; in jz4740_i2s_hw_params() local
265 div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV); in jz4740_i2s_hw_params()
287 div_reg &= ~I2SDIV_DV_MASK; in jz4740_i2s_hw_params()
288 div_reg |= (div - 1) << I2SDIV_DV_SHIFT; in jz4740_i2s_hw_params()
294 div_reg &= ~I2SDIV_IDV_MASK; in jz4740_i2s_hw_params()
295 div_reg |= (div - 1) << I2SDIV_IDV_SHIFT; in jz4740_i2s_hw_params()
297 div_reg &= ~I2SDIV_DV_MASK; in jz4740_i2s_hw_params()
298 div_reg |= (div - 1) << I2SDIV_DV_SHIFT; in jz4740_i2s_hw_params()
303 jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg); in jz4740_i2s_hw_params()
/linux-4.4.14/arch/arm/mach-davinci/
Ddm365.c90 .div_reg = BPDIV
103 .div_reg = PLLDIV1,
110 .div_reg = PLLDIV2,
117 .div_reg = PLLDIV3,
124 .div_reg = PLLDIV4,
131 .div_reg = PLLDIV5,
138 .div_reg = PLLDIV6,
145 .div_reg = PLLDIV7,
152 .div_reg = PLLDIV8,
159 .div_reg = PLLDIV9,
[all …]
Ddm646x.c86 .div_reg = PLLDIV1,
93 .div_reg = PLLDIV2,
100 .div_reg = PLLDIV3,
107 .div_reg = PLLDIV4,
114 .div_reg = PLLDIV5,
121 .div_reg = PLLDIV6,
128 .div_reg = PLLDIV8,
135 .div_reg = PLLDIV9,
142 .div_reg = BPDIV,
162 .div_reg = PLLDIV1,
Ddm644x.c71 .div_reg = PLLDIV1,
78 .div_reg = PLLDIV2,
85 .div_reg = PLLDIV3,
92 .div_reg = PLLDIV5,
105 .div_reg = BPDIV
119 .div_reg = PLLDIV1,
126 .div_reg = PLLDIV2,
133 .div_reg = BPDIV
Ddm355.c80 .div_reg = PLLDIV1,
87 .div_reg = PLLDIV2,
94 .div_reg = PLLDIV3,
101 .div_reg = PLLDIV4,
108 .div_reg = BPDIV
152 .div_reg = PLLDIV1,
159 .div_reg = BPDIV
Dclock.c314 if (!clk->div_reg) in clk_sysclk_recalc()
317 v = __raw_readl(pll->base + clk->div_reg); in clk_sysclk_recalc()
347 if (WARN_ON(!clk->div_reg)) in davinci_set_sysclk_rate()
383 v = __raw_readl(pll->base + clk->div_reg); in davinci_set_sysclk_rate()
386 __raw_writel(v, pll->base + clk->div_reg); in davinci_set_sysclk_rate()
Dda850.c84 .div_reg = PLLDIV1,
91 .div_reg = PLLDIV2,
98 .div_reg = PLLDIV3,
107 .div_reg = PLLDIV4,
114 .div_reg = PLLDIV5,
121 .div_reg = PLLDIV6,
128 .div_reg = PLLDIV7,
154 .div_reg = PLLDIV2,
161 .div_reg = PLLDIV3,
Dclock.h102 u32 div_reg; member
Dda830.c68 .div_reg = PLLDIV2,
75 .div_reg = PLLDIV3,
82 .div_reg = PLLDIV4,
89 .div_reg = PLLDIV5,
96 .div_reg = PLLDIV6,
103 .div_reg = PLLDIV7,
/linux-4.4.14/drivers/clk/bcm/
Dclk-bcm2835.c629 u32 div_reg; member
679 .div_reg = CM_TIMERDIV,
690 .div_reg = CM_OTPDIV,
706 .div_reg = CM_VPUDIV,
717 .div_reg = CM_V3DDIV,
727 .div_reg = CM_ISPDIV,
737 .div_reg = CM_H264DIV,
748 .div_reg = CM_VECDIV,
758 .div_reg = CM_UARTDIV,
769 .div_reg = CM_HSMDIV,
[all …]
/linux-4.4.14/drivers/clk/
Dclk-vt8500.c31 void __iomem *div_reg; member
127 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
198 writel(divisor, cdev->div_reg); in vt8500_dclk_set_rate()
234 u32 en_reg, div_reg; in vtwm_device_clk_init() local
264 rc = of_property_read_u32(node, "divisor-reg", &div_reg); in vtwm_device_clk_init()
266 dev_clk->div_reg = pmc_base + div_reg; in vtwm_device_clk_init()
/linux-4.4.14/drivers/clk/hisilicon/
Dclk-hi3620.c240 u32 div_reg; member
256 void __iomem *div_reg; member
386 val = readl_relaxed(mclk->div_reg); in mmc_clk_set_timing()
388 writel_relaxed(val, mclk->div_reg); in mmc_clk_set_timing()
448 mclk->div_reg = base + mmc_clk->div_reg; in hisi_register_clk_mmc()
/linux-4.4.14/drivers/clk/samsung/
Dclk-cpu.c64 static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask) in wait_until_divider_stable() argument
69 if (!(readl(div_reg) & mask)) in wait_until_divider_stable()
73 if (!(readl(div_reg) & mask)) in wait_until_divider_stable()
/linux-4.4.14/drivers/clk/ingenic/
Dcgu.c319 u32 div_reg, div; in ingenic_clk_recalc_rate() local
324 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
325 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()