1/*
2 * Copyright (C) 2015 Altera Corporation. All rights reserved
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16#include <linux/slab.h>
17#include <linux/clk-provider.h>
18#include <linux/io.h>
19#include <linux/of.h>
20
21#include "clk.h"
22
23#define CLK_MGR_FREE_SHIFT		16
24#define CLK_MGR_FREE_MASK		0x7
25
26#define SOCFPGA_MPU_FREE_CLK		"mpu_free_clk"
27#define SOCFPGA_NOC_FREE_CLK		"noc_free_clk"
28#define SOCFPGA_SDMMC_FREE_CLK		"sdmmc_free_clk"
29#define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
30
31static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
32					     unsigned long parent_rate)
33{
34	struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
35	u32 div;
36
37	if (socfpgaclk->fixed_div) {
38		div = socfpgaclk->fixed_div;
39	} else if (socfpgaclk->div_reg) {
40		div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
41		div &= GENMASK(socfpgaclk->width - 1, 0);
42		div += 1;
43	} else {
44		div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
45	}
46
47	return parent_rate / div;
48}
49
50static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
51{
52	struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
53	u32 clk_src;
54
55	clk_src = readl(socfpgaclk->hw.reg);
56	if (streq(hwclk->init->name, SOCFPGA_MPU_FREE_CLK) ||
57	    streq(hwclk->init->name, SOCFPGA_NOC_FREE_CLK) ||
58	    streq(hwclk->init->name, SOCFPGA_SDMMC_FREE_CLK))
59		return (clk_src >> CLK_MGR_FREE_SHIFT) &
60			CLK_MGR_FREE_MASK;
61	else
62		return 0;
63}
64
65static const struct clk_ops periclk_ops = {
66	.recalc_rate = clk_periclk_recalc_rate,
67	.get_parent = clk_periclk_get_parent,
68};
69
70static __init void __socfpga_periph_init(struct device_node *node,
71	const struct clk_ops *ops)
72{
73	u32 reg;
74	struct clk *clk;
75	struct socfpga_periph_clk *periph_clk;
76	const char *clk_name = node->name;
77	const char *parent_name;
78	struct clk_init_data init;
79	int rc;
80	u32 fixed_div;
81	u32 div_reg[3];
82
83	of_property_read_u32(node, "reg", &reg);
84
85	periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
86	if (WARN_ON(!periph_clk))
87		return;
88
89	periph_clk->hw.reg = clk_mgr_a10_base_addr + reg;
90
91	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
92	if (!rc) {
93		periph_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0];
94		periph_clk->shift = div_reg[1];
95		periph_clk->width = div_reg[2];
96	} else {
97		periph_clk->div_reg = NULL;
98	}
99
100	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
101	if (rc)
102		periph_clk->fixed_div = 0;
103	else
104		periph_clk->fixed_div = fixed_div;
105
106	of_property_read_string(node, "clock-output-names", &clk_name);
107
108	init.name = clk_name;
109	init.ops = ops;
110	init.flags = 0;
111
112	parent_name = of_clk_get_parent_name(node, 0);
113	init.num_parents = 1;
114	init.parent_names = &parent_name;
115
116	periph_clk->hw.hw.init = &init;
117
118	clk = clk_register(NULL, &periph_clk->hw.hw);
119	if (WARN_ON(IS_ERR(clk))) {
120		kfree(periph_clk);
121		return;
122	}
123	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
124	if (rc < 0) {
125		pr_err("Could not register clock provider for node:%s\n",
126		       clk_name);
127		goto err_clk;
128	}
129
130	return;
131
132err_clk:
133	clk_unregister(clk);
134}
135
136void __init socfpga_a10_periph_init(struct device_node *node)
137{
138	__socfpga_periph_init(node, &periclk_ops);
139}
140