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Searched refs:ctl_reg (Results 1 – 25 of 25) sorted by relevance

/linux-4.4.14/drivers/i2c/busses/
Di2c-brcmstb.c81 u32 ctl_reg; /* control register */ member
195 dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK; in brcmstb_i2c_enable_disable_irq()
198 dev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK; in brcmstb_i2c_enable_disable_irq()
201 bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg); in brcmstb_i2c_enable_disable_irq()
207 u32 status_bsc_ctl = bsc_readl(dev, ctl_reg); in brcmstb_i2c_isr()
328 u32 ctl_reg; in brcmstb_i2c_xfer_bsc_data() local
344 ctl_reg = pi2creg->ctl_reg & ~BSC_CTL_REG_DTF_MASK; in brcmstb_i2c_xfer_bsc_data()
346 pi2creg->ctl_reg = ctl_reg | DTF_WR_MASK; in brcmstb_i2c_xfer_bsc_data()
348 pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK; in brcmstb_i2c_xfer_bsc_data()
525 dev->bsc_regmap->ctl_reg &= ~(BSC_CTL_REG_SCL_SEL_MASK in brcmstb_i2c_set_bus_speed()
[all …]
/linux-4.4.14/drivers/pinctrl/qcom/
Dpinctrl-msm.c161 val = readl(pctrl->regs + g->ctl_reg); in msm_pinmux_set_mux()
164 writel(val, pctrl->regs + g->ctl_reg); in msm_pinmux_set_mux()
237 val = readl(pctrl->regs + g->ctl_reg); in msm_config_group_get()
358 val = readl(pctrl->regs + g->ctl_reg); in msm_config_group_set()
361 writel(val, pctrl->regs + g->ctl_reg); in msm_config_group_set()
392 val = readl(pctrl->regs + g->ctl_reg); in msm_gpio_direction_input()
394 writel(val, pctrl->regs + g->ctl_reg); in msm_gpio_direction_input()
419 val = readl(pctrl->regs + g->ctl_reg); in msm_gpio_direction_output()
421 writel(val, pctrl->regs + g->ctl_reg); in msm_gpio_direction_output()
476 u32 ctl_reg; in msm_gpio_dbg_show_one() local
[all …]
Dpinctrl-msm.h73 u32 ctl_reg; member
Dpinctrl-qdf2xxx.c63 groups[i].ctl_reg = 0x10000 * i; in qdf2xxx_pinctrl_probe()
Dpinctrl-ipq8064.c199 .ctl_reg = 0x1000 + 0x10 * id, \
226 .ctl_reg = ctl, \
Dpinctrl-apq8064.c246 .ctl_reg = 0x1000 + 0x10 * id, \
273 .ctl_reg = ctl, \
Dpinctrl-msm8660.c409 .ctl_reg = 0x1000 + 0x10 * id, \
436 .ctl_reg = ctl, \
Dpinctrl-msm8x74.c355 .ctl_reg = 0x1000 + 0x10 * id, \
381 .ctl_reg = ctl, \
Dpinctrl-msm8916.c322 .ctl_reg = 0x1000 * id, \
348 .ctl_reg = ctl, \
Dpinctrl-apq8084.c359 .ctl_reg = 0x1000 + 0x10 * id, \
386 .ctl_reg = ctl, \
Dpinctrl-msm8960.c372 .ctl_reg = 0x1000 + 0x10 * id, \
399 .ctl_reg = ctl, \
/linux-4.4.14/drivers/clk/bcm/
Dclk-bcm2835.c628 u32 ctl_reg; member
678 .ctl_reg = CM_TIMERCTL,
689 .ctl_reg = CM_OTPCTL,
705 .ctl_reg = CM_VPUCTL,
716 .ctl_reg = CM_V3DCTL,
726 .ctl_reg = CM_ISPCTL,
736 .ctl_reg = CM_H264CTL,
747 .ctl_reg = CM_VECCTL,
757 .ctl_reg = CM_UARTCTL,
768 .ctl_reg = CM_HSMCTL,
[all …]
/linux-4.4.14/drivers/spi/
Dspi-bfin-sport.c101 u16 ctl_reg; member
258 bfin_write(&drv_data->regs->tcr1, chip->ctl_reg); in bfin_sport_spi_restore_state()
262 bfin_write(&drv_data->regs->rcr1, chip->ctl_reg & ~(ITCLK | ITFS)); in bfin_sport_spi_restore_state()
521 drv_data->cur_chip->ctl_reg); in bfin_sport_spi_pump_messages()
589 if (chip_info->ctl_reg || chip_info->enable_dma) { in bfin_sport_spi_setup()
604 chip->ctl_reg &= ~TCKFE; in bfin_sport_spi_setup()
606 chip->ctl_reg |= TCKFE; in bfin_sport_spi_setup()
609 chip->ctl_reg |= TLSBIT; in bfin_sport_spi_setup()
611 chip->ctl_reg &= ~TLSBIT; in bfin_sport_spi_setup()
614 chip->ctl_reg |= ITCLK | ITFS | TFSR | LATFS | LTFS; in bfin_sport_spi_setup()
[all …]
Dspi-bfin5xx.c113 u16 ctl_reg; member
214 bfin_write(&drv_data->regs->ctl, chip->ctl_reg); in bfin_spi_restore_state()
912 drv_data->cur_chip->ctl_reg); in bfin_spi_pump_messages()
1008 if (chip_info->ctl_reg & ~bfin_ctl_reg) { in bfin_spi_setup()
1015 chip->ctl_reg = chip_info->ctl_reg; in bfin_spi_setup()
1021 chip->ctl_reg &= bfin_ctl_reg; in bfin_spi_setup()
1026 chip->ctl_reg |= BIT_CTL_CPOL; in bfin_spi_setup()
1028 chip->ctl_reg |= BIT_CTL_CPHA; in bfin_spi_setup()
1030 chip->ctl_reg |= BIT_CTL_LSBF; in bfin_spi_setup()
1032 chip->ctl_reg |= BIT_CTL_MASTER; in bfin_spi_setup()
[all …]
Dspi-adi-v3.c656 u32 ctl_reg = SPI_CTL_ODM | SPI_CTL_PSSE; in adi_spi_setup() local
667 if (chip_info->control & ~ctl_reg) { in adi_spi_setup()
700 chip->control &= ctl_reg; in adi_spi_setup()
/linux-4.4.14/drivers/scsi/csiostor/
Dcsio_mb.c1158 uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A); in csio_mb_debug_cmd_handler() local
1170 MBOWNER_V(CSIO_MBOWNER_FW), ctl_reg); in csio_mb_debug_cmd_handler()
1172 csio_rd_reg32(hw, ctl_reg); in csio_mb_debug_cmd_handler()
1192 uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A); in csio_mb_issue() local
1229 owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg)); in csio_mb_issue()
1234 owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg)); in csio_mb_issue()
1277 MBOWNER_V(CSIO_MBOWNER_FW), ctl_reg); in csio_mb_issue()
1280 ctl_reg); in csio_mb_issue()
1283 csio_rd_reg32(hw, ctl_reg); in csio_mb_issue()
1298 ctl = csio_rd_reg32(hw, ctl_reg); in csio_mb_issue()
[all …]
/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_lvds.c213 u32 ctl_reg, stat_reg; in intel_enable_lvds() local
216 ctl_reg = PCH_PP_CONTROL; in intel_enable_lvds()
219 ctl_reg = PP_CONTROL; in intel_enable_lvds()
225 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); in intel_enable_lvds()
238 u32 ctl_reg, stat_reg; in intel_disable_lvds() local
241 ctl_reg = PCH_PP_CONTROL; in intel_disable_lvds()
244 ctl_reg = PP_CONTROL; in intel_disable_lvds()
248 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); in intel_disable_lvds()
Dintel_psr.c83 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); in intel_psr_write_vsc() local
90 I915_WRITE(ctl_reg, 0); in intel_psr_write_vsc()
91 POSTING_READ(ctl_reg); in intel_psr_write_vsc()
102 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); in intel_psr_write_vsc()
103 POSTING_READ(ctl_reg); in intel_psr_write_vsc()
Dintel_hdmi.c370 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); in hsw_write_infoframe() local
373 u32 val = I915_READ(ctl_reg); in hsw_write_infoframe()
380 I915_WRITE(ctl_reg, val); in hsw_write_infoframe()
395 I915_WRITE(ctl_reg, val); in hsw_write_infoframe()
396 POSTING_READ(ctl_reg); in hsw_write_infoframe()
404 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); in hsw_infoframe_enabled() local
405 u32 val = I915_READ(ctl_reg); in hsw_infoframe_enabled()
/linux-4.4.14/drivers/misc/
Dphantom.c61 u32 ctl_reg; member
120 r.value |= dev->ctl_reg & PHN_CTL_AMP; in phantom_ioctl()
121 dev->ctl_reg = r.value; in phantom_ioctl()
310 dev->ctl_reg ^= PHN_CTL_AMP; in phantom_isr()
311 iowrite32(dev->ctl_reg, dev->iaddr + PHN_CONTROL); in phantom_isr()
/linux-4.4.14/arch/blackfin/include/asm/
Dbfin5xx_spi.h78 u16 ctl_reg; member
/linux-4.4.14/drivers/net/ethernet/
Ddnet.c178 u32 mode_reg, ctl_reg; in dnet_handle_link_change() local
185 ctl_reg = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG); in dnet_handle_link_change()
190 ctl_reg &= in dnet_handle_link_change()
193 ctl_reg |= in dnet_handle_link_change()
238 dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg); in dnet_handle_link_change()
/linux-4.4.14/drivers/scsi/lpfc/
Dlpfc_debugfs.c3112 void __iomem *ctl_reg; in lpfc_idiag_ctlacc_write() local
3148 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write()
3152 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write()
3156 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write()
3160 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write()
3164 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write()
3168 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write()
3178 reg_val = readl(ctl_reg); in lpfc_idiag_ctlacc_write()
3182 reg_val = readl(ctl_reg); in lpfc_idiag_ctlacc_write()
3185 writel(reg_val, ctl_reg); in lpfc_idiag_ctlacc_write()
[all …]
/linux-4.4.14/sound/soc/davinci/
Ddavinci-mcasp.c146 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) in mcasp_set_ctl_reg() argument
150 mcasp_set_bits(mcasp, ctl_reg, val); in mcasp_set_ctl_reg()
155 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) in mcasp_set_ctl_reg()
159 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) in mcasp_set_ctl_reg()
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb4/
Dt4_hw.c276 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A); in t4_wr_mbox_meat_timeout() local
288 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat_timeout()
290 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat_timeout()
298 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW)); in t4_wr_mbox_meat_timeout()
299 t4_read_reg(adap, ctl_reg); /* flush write */ in t4_wr_mbox_meat_timeout()
313 v = t4_read_reg(adap, ctl_reg); in t4_wr_mbox_meat_timeout()
316 t4_write_reg(adap, ctl_reg, 0); in t4_wr_mbox_meat_timeout()
330 t4_write_reg(adap, ctl_reg, 0); in t4_wr_mbox_meat_timeout()