Searched refs:cpsr (Results 1 - 37 of 37) sorted by relevance

/linux-4.4.14/arch/arm64/kvm/
H A Demulate.c70 unsigned long cpsr; kvm_condition_valid32() local
83 cpsr = *vcpu_cpsr(vcpu); kvm_condition_valid32()
89 it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3); kvm_condition_valid32()
99 cpsr_cond = cpsr >> 28; kvm_condition_valid32()
120 unsigned long cpsr = *vcpu_cpsr(vcpu); kvm_adjust_itstate() local
121 bool is_arm = !(cpsr & COMPAT_PSR_T_BIT); kvm_adjust_itstate()
123 BUG_ON(is_arm && (cpsr & COMPAT_PSR_IT_MASK)); kvm_adjust_itstate()
125 if (!(cpsr & COMPAT_PSR_IT_MASK)) kvm_adjust_itstate()
128 cond = (cpsr & 0xe000) >> 13; kvm_adjust_itstate()
129 itbits = (cpsr & 0x1c00) >> (10 - 2); kvm_adjust_itstate()
130 itbits |= (cpsr & (0x3 << 25)) >> 25; kvm_adjust_itstate()
138 cpsr &= ~COMPAT_PSR_IT_MASK; kvm_adjust_itstate()
139 cpsr |= cond << 13; kvm_adjust_itstate()
140 cpsr |= (itbits & 0x1c) << (10 - 2); kvm_adjust_itstate()
141 cpsr |= (itbits & 0x3) << 25; kvm_adjust_itstate()
142 *vcpu_cpsr(vcpu) = cpsr; kvm_adjust_itstate()
H A Dinject_fault.c34 unsigned long cpsr; prepare_fault32() local
40 cpsr = mode | COMPAT_PSR_I_BIT; prepare_fault32()
43 cpsr |= COMPAT_PSR_T_BIT; prepare_fault32()
45 cpsr |= COMPAT_PSR_E_BIT; prepare_fault32()
47 *vcpu_cpsr(vcpu) = cpsr; prepare_fault32()
102 unsigned long cpsr = *vcpu_cpsr(vcpu); inject_abt64() local
108 *vcpu_spsr(vcpu) = cpsr; inject_abt64()
127 if (is_aarch32 || (cpsr & PSR_MODE_MASK) == PSR_MODE_EL0t) inject_abt64()
140 unsigned long cpsr = *vcpu_cpsr(vcpu); inject_undef64() local
143 *vcpu_spsr(vcpu) = cpsr; inject_undef64()
/linux-4.4.14/arch/arm/probes/kprobes/
H A Dactions-arm.c178 unsigned long cpsr = regs->ARM_cpsr; emulate_rd12rn16rm0rs8_rwflags() local
181 "msr cpsr_fs, %[cpsr] \n\t" emulate_rd12rn16rm0rs8_rwflags()
183 "mrs %[cpsr], cpsr \n\t" emulate_rd12rn16rm0rs8_rwflags()
184 : "=r" (rdv), [cpsr] "=r" (cpsr) emulate_rd12rn16rm0rs8_rwflags()
186 "1" (cpsr), [fn] "r" (asi->insn_fn) emulate_rd12rn16rm0rs8_rwflags()
194 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK); emulate_rd12rn16rm0rs8_rwflags()
208 unsigned long cpsr = regs->ARM_cpsr; emulate_rd12rn16rm0_rwflags_nopc() local
211 "msr cpsr_fs, %[cpsr] \n\t" emulate_rd12rn16rm0_rwflags_nopc()
213 "mrs %[cpsr], cpsr \n\t" emulate_rd12rn16rm0_rwflags_nopc()
214 : "=r" (rdv), [cpsr] "=r" (cpsr) emulate_rd12rn16rm0_rwflags_nopc()
216 "1" (cpsr), [fn] "r" (asi->insn_fn) emulate_rd12rn16rm0_rwflags_nopc()
221 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK); emulate_rd12rn16rm0_rwflags_nopc()
238 unsigned long cpsr = regs->ARM_cpsr; emulate_rd16rn12rm0rs8_rwflags_nopc() local
241 "msr cpsr_fs, %[cpsr] \n\t" emulate_rd16rn12rm0rs8_rwflags_nopc()
243 "mrs %[cpsr], cpsr \n\t" emulate_rd16rn12rm0rs8_rwflags_nopc()
244 : "=r" (rdv), [cpsr] "=r" (cpsr) emulate_rd16rn12rm0rs8_rwflags_nopc()
246 "1" (cpsr), [fn] "r" (asi->insn_fn) emulate_rd16rn12rm0rs8_rwflags_nopc()
251 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK); emulate_rd16rn12rm0rs8_rwflags_nopc()
288 unsigned long cpsr = regs->ARM_cpsr; emulate_rdlo12rdhi16rn0rm8_rwflags_nopc() local
291 "msr cpsr_fs, %[cpsr] \n\t" emulate_rdlo12rdhi16rn0rm8_rwflags_nopc()
293 "mrs %[cpsr], cpsr \n\t" emulate_rdlo12rdhi16rn0rm8_rwflags_nopc()
294 : "=r" (rdlov), "=r" (rdhiv), [cpsr] "=r" (cpsr) emulate_rdlo12rdhi16rn0rm8_rwflags_nopc()
296 "2" (cpsr), [fn] "r" (asi->insn_fn) emulate_rdlo12rdhi16rn0rm8_rwflags_nopc()
302 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK); emulate_rdlo12rdhi16rn0rm8_rwflags_nopc()
H A Dactions-thumb.c224 unsigned long cpsr = regs->ARM_cpsr; t32_emulate_rd8rn16rm0_rwflags() local
227 "msr cpsr_fs, %[cpsr] \n\t" t32_emulate_rd8rn16rm0_rwflags()
229 "mrs %[cpsr], cpsr \n\t" t32_emulate_rd8rn16rm0_rwflags()
230 : "=r" (rdv), [cpsr] "=r" (cpsr) t32_emulate_rd8rn16rm0_rwflags()
232 "1" (cpsr), [fn] "r" (asi->insn_fn) t32_emulate_rd8rn16rm0_rwflags()
237 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK); t32_emulate_rd8rn16rm0_rwflags()
391 unsigned long cpsr = regs->ARM_cpsr; t16_simulate_it() local
392 cpsr &= ~PSR_IT_MASK; t16_simulate_it()
393 cpsr |= (insn & 0xfc) << 8; t16_simulate_it()
394 cpsr |= (insn & 0x03) << 25; t16_simulate_it()
395 regs->ARM_cpsr = cpsr; t16_simulate_it()
456 "mrs %[newcpsr], cpsr \n\t" t16_emulate_loregs()
478 unsigned long cpsr = t16_emulate_loregs(insn, asi, regs); t16_emulate_loregs_noitrwflags() local
479 if (!in_it_block(cpsr)) t16_emulate_loregs_noitrwflags()
480 regs->ARM_cpsr = cpsr; t16_emulate_loregs_noitrwflags()
493 unsigned long cpsr = regs->ARM_cpsr; t16_emulate_hiregs() local
499 "msr cpsr_fs, %[cpsr] \n\t" t16_emulate_hiregs()
501 "mrs %[cpsr], cpsr \n\t" t16_emulate_hiregs()
502 : "=r" (rdnv), [cpsr] "=r" (cpsr) t16_emulate_hiregs()
503 : "0" (rdnv), "r" (rmv), "1" (cpsr), [fn] "r" (asi->insn_fn) t16_emulate_hiregs()
511 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK); t16_emulate_hiregs()
H A Dtest-core.c1063 static unsigned long test_check_cc(int cc, unsigned long cpsr) test_check_cc() argument
1065 int ret = arm_check_condition(cc << 28, cpsr); test_check_cc()
1076 unsigned long cpsr; test_context_cpsr() local
1081 cpsr = (scenario & 0xf) << 28; /* N,Z,C,V flags */ test_context_cpsr()
1082 cpsr |= (scenario & 0xf) << 16; /* GE flags */ test_context_cpsr()
1083 cpsr |= (scenario & 0x1) << 27; /* Toggle Q flag */ test_context_cpsr()
1089 probe_should_run = test_check_cc(cc, cpsr) != 0; test_context_cpsr()
1097 probe_should_run = test_check_cc(cc, cpsr) != 0; test_context_cpsr()
1117 cpsr |= cond_base << 13; /* ITSTATE<7:5> */ test_context_cpsr()
1118 cpsr |= (mask & 0x1) << 12; /* ITSTATE<4> */ test_context_cpsr()
1119 cpsr |= (mask & 0x2) << 10; /* ITSTATE<3> */ test_context_cpsr()
1120 cpsr |= (mask & 0x4) << 8; /* ITSTATE<2> */ test_context_cpsr()
1121 cpsr |= (mask & 0x8) << 23; /* ITSTATE<1> */ test_context_cpsr()
1122 cpsr |= (mask & 0x10) << 21; /* ITSTATE<0> */ test_context_cpsr()
1124 probe_should_run = test_check_cc((cpsr >> 12) & 0xf, cpsr) != 0; test_context_cpsr()
1130 cpsr = 0x00000800; test_context_cpsr()
1134 cpsr = 0xf0007800; test_context_cpsr()
1138 cpsr = 0x00009800; test_context_cpsr()
1141 cpsr = 0xf0002800; test_context_cpsr()
1147 return cpsr; test_context_cpsr()
1329 pr_err("cpsr %08lx\n", regs->ARM_cpsr); print_registers()
H A Dcore.c502 long cpsr; setjmp_pre_handler() local
508 cpsr = regs->ARM_cpsr | PSR_I_BIT; setjmp_pre_handler()
510 /* Set correct Thumb state in cpsr */ setjmp_pre_handler()
512 cpsr |= PSR_T_BIT; setjmp_pre_handler()
514 cpsr &= ~PSR_T_BIT; setjmp_pre_handler()
516 regs->ARM_cpsr = cpsr; setjmp_pre_handler()
H A Dtest-arm.c207 TEST_RMASKED("mrs r",0,~PSR_IGNORE_BITS,", cpsr") kprobe_arm_test_cases()
208 TEST_RMASKED("mrspl r",7,~PSR_IGNORE_BITS,", cpsr") kprobe_arm_test_cases()
209 TEST_RMASKED("mrs r",14,~PSR_IGNORE_BITS,", cpsr") kprobe_arm_test_cases()
210 TEST_UNSUPPORTED(__inst_arm(0xe10ff000) " @ mrs r15, cpsr") kprobe_arm_test_cases()
214 TEST_UNSUPPORTED("msr cpsr, r0") kprobe_arm_test_cases()
632 TEST_UNSUPPORTED("msr cpsr, 0x13") kprobe_arm_test_cases()
H A Dopt-arm.c57 " mrs r4, cpsr\n"
H A Dtest-thumb.c757 TEST_UNSUPPORTED("msr cpsr, r0") kprobe_thumb32_test_cases()
781 TEST_RMASKED("mrs r",0,~PSR_IGNORE_BITS,", cpsr") kprobe_thumb32_test_cases()
782 TEST_RMASKED("mrs r",14,~PSR_IGNORE_BITS,", cpsr") kprobe_thumb32_test_cases()
/linux-4.4.14/arch/arm/probes/
H A Ddecode.c87 static unsigned long __kprobes __check_eq(unsigned long cpsr) __check_eq() argument
89 return cpsr & PSR_Z_BIT; __check_eq()
92 static unsigned long __kprobes __check_ne(unsigned long cpsr) __check_ne() argument
94 return (~cpsr) & PSR_Z_BIT; __check_ne()
97 static unsigned long __kprobes __check_cs(unsigned long cpsr) __check_cs() argument
99 return cpsr & PSR_C_BIT; __check_cs()
102 static unsigned long __kprobes __check_cc(unsigned long cpsr) __check_cc() argument
104 return (~cpsr) & PSR_C_BIT; __check_cc()
107 static unsigned long __kprobes __check_mi(unsigned long cpsr) __check_mi() argument
109 return cpsr & PSR_N_BIT; __check_mi()
112 static unsigned long __kprobes __check_pl(unsigned long cpsr) __check_pl() argument
114 return (~cpsr) & PSR_N_BIT; __check_pl()
117 static unsigned long __kprobes __check_vs(unsigned long cpsr) __check_vs() argument
119 return cpsr & PSR_V_BIT; __check_vs()
122 static unsigned long __kprobes __check_vc(unsigned long cpsr) __check_vc() argument
124 return (~cpsr) & PSR_V_BIT; __check_vc()
127 static unsigned long __kprobes __check_hi(unsigned long cpsr) __check_hi() argument
129 cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ __check_hi()
130 return cpsr & PSR_C_BIT; __check_hi()
133 static unsigned long __kprobes __check_ls(unsigned long cpsr) __check_ls() argument
135 cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ __check_ls()
136 return (~cpsr) & PSR_C_BIT; __check_ls()
139 static unsigned long __kprobes __check_ge(unsigned long cpsr) __check_ge() argument
141 cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ __check_ge()
142 return (~cpsr) & PSR_N_BIT; __check_ge()
145 static unsigned long __kprobes __check_lt(unsigned long cpsr) __check_lt() argument
147 cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ __check_lt()
148 return cpsr & PSR_N_BIT; __check_lt()
151 static unsigned long __kprobes __check_gt(unsigned long cpsr) __check_gt() argument
153 unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ __check_gt()
154 temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */ __check_gt()
158 static unsigned long __kprobes __check_le(unsigned long cpsr) __check_le() argument
160 unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ __check_le()
161 temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */ __check_le()
165 static unsigned long __kprobes __check_al(unsigned long cpsr) __check_al() argument
H A Ddecode-thumb.h23 #define in_it_block(cpsr) ((cpsr & 0x06000c00) != 0x00000000)
30 #define current_cond(cpsr) ((cpsr >> 12) & 0xf)
H A Ddecode.h52 static inline unsigned long it_advance(unsigned long cpsr) it_advance() argument
54 if ((cpsr & 0x06000400) == 0) { it_advance()
56 cpsr &= ~PSR_IT_MASK; it_advance()
60 unsigned long it = cpsr & mask; it_advance()
64 cpsr &= ~mask; it_advance()
65 cpsr |= it; it_advance()
67 return cpsr; it_advance()
72 long cpsr = regs->ARM_cpsr; bx_write_pc() local
74 cpsr |= PSR_T_BIT; bx_write_pc()
77 cpsr &= ~PSR_T_BIT; bx_write_pc()
80 regs->ARM_cpsr = cpsr; bx_write_pc()
H A Ddecode-thumb.c839 static unsigned long __kprobes thumb_check_cc(unsigned long cpsr) thumb_check_cc() argument
841 if (unlikely(in_it_block(cpsr))) thumb_check_cc()
842 return probes_condition_checks[current_cond(cpsr)](cpsr); thumb_check_cc()
H A Ddecode-arm.c162 /* MRS cpsr cccc 0001 0000 xxxx xxxx xxxx 0000 xxxx */
/linux-4.4.14/arch/arm/kvm/
H A Demulate.c171 unsigned long cpsr, cond, insn; kvm_condition_valid() local
184 cpsr = *vcpu_cpsr(vcpu); kvm_condition_valid()
193 it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3); kvm_condition_valid()
205 return arm_check_condition(insn, cpsr) != ARM_OPCODE_CONDTEST_FAIL; kvm_condition_valid()
221 unsigned long cpsr = *vcpu_cpsr(vcpu); kvm_adjust_itstate() local
222 bool is_arm = !(cpsr & PSR_T_BIT); kvm_adjust_itstate()
224 BUG_ON(is_arm && (cpsr & PSR_IT_MASK)); kvm_adjust_itstate()
226 if (!(cpsr & PSR_IT_MASK)) kvm_adjust_itstate()
229 cond = (cpsr & 0xe000) >> 13; kvm_adjust_itstate()
230 itbits = (cpsr & 0x1c00) >> (10 - 2); kvm_adjust_itstate()
231 itbits |= (cpsr & (0x3 << 25)) >> 25; kvm_adjust_itstate()
239 cpsr &= ~PSR_IT_MASK; kvm_adjust_itstate()
240 cpsr |= cond << 13; kvm_adjust_itstate()
241 cpsr |= (itbits & 0x1c) << (10 - 2); kvm_adjust_itstate()
242 cpsr |= (itbits & 0x3) << 25; kvm_adjust_itstate()
243 *vcpu_cpsr(vcpu) = cpsr; kvm_adjust_itstate()
291 unsigned long cpsr = *vcpu_cpsr(vcpu); kvm_inject_undefined() local
293 bool is_thumb = (cpsr & PSR_T_BIT); kvm_inject_undefined()
297 new_spsr_value = cpsr; kvm_inject_undefined()
300 *vcpu_cpsr(vcpu) = (cpsr & ~MODE_MASK) | UND_MODE; kvm_inject_undefined()
310 *vcpu_spsr(vcpu) = cpsr; kvm_inject_undefined()
325 unsigned long cpsr = *vcpu_cpsr(vcpu); inject_abt() local
327 bool is_thumb = (cpsr & PSR_T_BIT); inject_abt()
332 new_spsr_value = cpsr; inject_abt()
335 *vcpu_cpsr(vcpu) = (cpsr & ~MODE_MASK) | ABT_MODE; inject_abt()
345 *vcpu_spsr(vcpu) = cpsr; inject_abt()
H A Dtrace.h117 unsigned long cpsr),
118 TP_ARGS(vcpu_pc, instr, cpsr),
123 __field( unsigned long, cpsr )
129 __entry->cpsr = cpsr;
132 TP_printk("Emulate MMIO at: 0x%08lx (instr: %08lx, cpsr: %08lx)",
133 __entry->vcpu_pc, __entry->instr, __entry->cpsr)
H A Dinterrupts.S304 99: mrs r2, cpsr
/linux-4.4.14/arch/arm/include/asm/
H A Dirqflags.h16 #define IRQMASK_REG_NAME_R "cpsr"
76 " mrs %0, cpsr @ arch_local_irq_save\n" arch_local_irq_save()
93 " mrs %0, cpsr @ arch_local_irq_enable\n" arch_local_irq_enable()
109 " mrs %0, cpsr @ arch_local_irq_disable\n" arch_local_irq_disable()
124 "mrs %0, cpsr @ stf\n" \
139 "mrs %0, cpsr @ clf\n" \
H A Dkexec.h41 "mrs %[_ARM_cpsr], cpsr\n\t" crash_setup_regs()
H A Dkgdb.h61 * cpsr: 1 long word
H A Dassembler.h156 mrs \oldcpsr, cpsr
162 mrs \oldcpsr, cpsr
340 mrs \reg , cpsr
/linux-4.4.14/arch/arm/lib/
H A Decard.S17 mrs rt, cpsr; \
/linux-4.4.14/arch/arm/kernel/
H A Dentry-header.S176 mrs \rtemp, cpsr
188 mrs \rtemp, cpsr
228 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
296 ldr r1, [r2, #\offset + S_PSR] @ get calling cpsr
311 movs pc, lr @ return & move spsr_svc into cpsr
324 ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
338 movs pc, lr @ return & move spsr_svc into cpsr
H A Dsignal.c328 unsigned long cpsr = regs->ARM_cpsr & ~(PSR_f | PSR_E_BIT); setup_return() local
330 cpsr |= PSR_ENDSTATE; setup_return()
336 cpsr = (cpsr & ~MODE_MASK) | USR_MODE; setup_return()
357 cpsr &= ~PSR_IT_MASK; setup_return()
360 cpsr |= PSR_T_BIT; setup_return()
362 cpsr &= ~PSR_T_BIT; setup_return()
383 if (cpsr & MODE32_BIT) { setup_return()
411 regs->ARM_cpsr = cpsr; setup_return()
H A Diwmmxt.S199 mrs ip, cpsr
251 mrs ip, cpsr
289 mrs ip, cpsr
356 mrs r2, cpsr
H A Dhyp-stub.S41 mrs \reg1, cpsr
94 mrs r4, cpsr
H A Dkgdb.c47 { "cpsr", 4, offsetof(struct pt_regs, ARM_cpsr)},
H A Dentry-armv.S293 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
1046 mrs r0, cpsr
H A Dptrace.c88 REG_OFFSET_NAME(cpsr),
/linux-4.4.14/drivers/spi/
H A Dspi-ep93xx.c194 * @div_cpsr: pointer to return the cpsr (pre-scaler) divider
202 int cpsr, scr; ep93xx_spi_calc_divisors() local
214 * rate = spi_clock_rate / (cpsr * (1 + scr)) ep93xx_spi_calc_divisors()
216 * cpsr must be even number and starts from 2, scr can be any number ep93xx_spi_calc_divisors()
219 for (cpsr = 2; cpsr <= 254; cpsr += 2) { ep93xx_spi_calc_divisors()
221 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) { ep93xx_spi_calc_divisors()
223 *div_cpsr = (u8)cpsr; ep93xx_spi_calc_divisors()
328 dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n", ep93xx_spi_chip_setup()
H A Dspi-pl022.c421 * @cpsr: Value of Clock prescale register
436 u16 cpsr; member in struct:chip_data
583 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); restore_state()
1966 chip->cpsr = 0; pl022_setup()
1984 chip->cpsr = clk_freq.cpsdvsr; pl022_setup()
/linux-4.4.14/arch/arm/mach-ep93xx/
H A Dcrunch-bits.S212 mrs ip, cpsr
258 mrs ip, cpsr
291 mrs ip, cpsr
/linux-4.4.14/arch/arm/mm/
H A Dproc-feroceon.S261 mrs r2, cpsr
302 mrs r2, cpsr
338 mrs r2, cpsr
369 mrs r2, cpsr
H A Dcache-v6.S41 mrs r1, cpsr
H A Dproc-arm926.S107 mrs r3, cpsr @ Disable FIQs while Icache
/linux-4.4.14/arch/arm/boot/compressed/
H A Dhead.S144 AR_CLASS( mrs r9, cpsr )
157 mrs r2, cpsr @ get current mode
/linux-4.4.14/drivers/net/wireless/brcm80211/brcmfmac/
H A Dsdio.c340 __le32 cpsr; member in struct:brcmf_trap_info
3059 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" brcmf_sdio_trap_info()
3064 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), brcmf_sdio_trap_info()

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