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Searched refs:clk_readl (Results 1 – 30 of 30) sorted by relevance

/linux-4.4.14/drivers/clk/shmobile/
Dclk-div6.c47 val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP)) in cpg_div6_clock_enable()
59 val = clk_readl(clock->reg); in cpg_div6_clock_disable()
76 return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP); in cpg_div6_clock_is_enabled()
83 unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; in cpg_div6_clock_recalc_rate()
117 val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK; in cpg_div6_clock_set_rate()
134 hw_index = (clk_readl(clock->reg) >> clock->src_shift) & in cpg_div6_clock_get_parent()
158 clk_writel((clk_readl(clock->reg) & mask) | in cpg_div6_clock_set_parent()
215 clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; in cpg_div6_clock_init()
Dclk-r8a73a4.c74 u32 ckscr = clk_readl(cpg->reg + CPG_CKSCR); in r8a73a4_cpg_register_clock()
98 u32 value = clk_readl(cpg->reg + CPG_PLL0CR); in r8a73a4_cpg_register_clock()
105 u32 value = clk_readl(cpg->reg + CPG_PLL1CR); in r8a73a4_cpg_register_clock()
128 value = clk_readl(cpg->reg + cr); in r8a73a4_cpg_register_clock()
164 mult = 0x20 - ((clk_readl(cpg->reg + CPG_FRQCRC) >> shift) in r8a73a4_cpg_register_clock()
Dclk-r8a7740.c101 u32 value = clk_readl(cpg->reg + CPG_FRQCRC); in r8a7740_cpg_register_clock()
105 u32 value = clk_readl(cpg->reg + CPG_FRQCRA); in r8a7740_cpg_register_clock()
110 u32 value = clk_readl(cpg->reg + CPG_PLLC2CR); in r8a7740_cpg_register_clock()
114 u32 value = clk_readl(cpg->reg + CPG_USBCKCR); in r8a7740_cpg_register_clock()
Dclk-sh73a0.c88 u32 parent_idx = (clk_readl(cpg->reg + CPG_CKSCR) >> 28) & 3; in sh73a0_cpg_register_clock()
113 if (clk_readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { in sh73a0_cpg_register_clock()
114 mult = ((clk_readl(enable_reg) >> 24) & 0x3f) + 1; in sh73a0_cpg_register_clock()
117 if (clk_readl(enable_reg) & BIT(20)) in sh73a0_cpg_register_clock()
Dclk-rcar-gen2.c64 val = (clk_readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) in cpg_z_clk_recalc_rate()
97 if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK) in cpg_z_clk_set_rate()
100 val = clk_readl(zclk->reg); in cpg_z_clk_set_rate()
109 kick = clk_readl(zclk->kick_reg); in cpg_z_clk_set_rate()
123 if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) in cpg_z_clk_set_rate()
320 u32 value = clk_readl(cpg->reg + CPG_PLL0CR); in rcar_gen2_cpg_register_clock()
Dclk-mstp.c73 value = clk_readl(group->smstpcr); in cpg_mstp_clock_endisable()
86 if (!(clk_readl(group->mstpsr) & bitmask)) in cpg_mstp_clock_endisable()
117 value = clk_readl(group->mstpsr); in cpg_mstp_clock_is_enabled()
119 value = clk_readl(group->smstpcr); in cpg_mstp_clock_is_enabled()
Dclk-rz.c58 val = (clk_readl(cpg->reg + CPG_FRQCR) >> 8) & 3; in rz_cpg_register_clock()
60 val = clk_readl(cpg->reg + CPG_FRQCR2) & 3; in rz_cpg_register_clock()
/linux-4.4.14/drivers/clk/zynq/
Dpll.c93 fbdiv = (clk_readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >> in zynq_pll_recalc_rate()
115 reg = clk_readl(clk->pll_ctrl); in zynq_pll_is_enabled()
141 reg = clk_readl(clk->pll_ctrl); in zynq_pll_enable()
144 while (!(clk_readl(clk->pll_status) & (1 << clk->lockbit))) in zynq_pll_enable()
171 reg = clk_readl(clk->pll_ctrl); in zynq_pll_disable()
226 reg = clk_readl(pll->pll_ctrl); in clk_register_zynq_pll()
Dclkc.c161 enable_reg = clk_readl(fclk_gate_reg) & 1; in zynq_clk_register_fclk()
291 tmp = clk_readl(SLCR_621_TRUE) & 1; in zynq_clk_setup()
514 tmp = clk_readl(SLCR_DBG_CLK_CTRL); in zynq_clk_setup()
/linux-4.4.14/drivers/clk/ti/
Dclkt_dflt.c67 if ((ti_clk_ll_ops->clk_readl(reg) & mask) == ena) in _wait_idlest_generic()
102 if (!(ti_clk_ll_ops->clk_readl(companion_reg) & in _omap2_module_wait_ready()
233 v = ti_clk_ll_ops->clk_readl(clk->enable_reg); in omap2_dflt_clk_enable()
239 v = ti_clk_ll_ops->clk_readl(clk->enable_reg); /* OCP barrier */ in omap2_dflt_clk_enable()
277 v = ti_clk_ll_ops->clk_readl(clk->enable_reg); in omap2_dflt_clk_disable()
303 v = ti_clk_ll_ops->clk_readl(clk->enable_reg); in omap2_dflt_clk_is_enabled()
Dapll.c58 v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); in dra7_apll_enable()
63 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in dra7_apll_enable()
71 v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); in dra7_apll_enable()
102 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in dra7_apll_disable()
116 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in dra7_apll_is_enabled()
233 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in omap2_apll_is_enabled()
259 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in omap2_apll_enable()
265 v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); in omap2_apll_enable()
289 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in omap2_apll_disable()
307 v = ti_clk_ll_ops->clk_readl(ad->autoidle_reg); in omap2_apll_set_autoidle()
Ddpll3xxx.c57 v = ti_clk_ll_ops->clk_readl(dd->control_reg); in _omap3_dpll_write_clken()
76 while (((ti_clk_ll_ops->clk_readl(dd->idlest_reg) & dd->idlest_mask) in _omap3_wait_dpll_status()
154 if ((ti_clk_ll_ops->clk_readl(dd->idlest_reg) & dd->idlest_mask) == in _omap3_noncore_dpll_lock()
319 v = ti_clk_ll_ops->clk_readl(dd->control_reg); in omap3_noncore_dpll_program()
326 v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg); in omap3_noncore_dpll_program()
357 v = ti_clk_ll_ops->clk_readl(dd->control_reg); in omap3_noncore_dpll_program()
635 v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg); in omap3_dpll_autoidle_read()
669 v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg); in omap3_dpll_allow_idle()
694 v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg); in omap3_dpll_deny_idle()
753 v = ti_clk_ll_ops->clk_readl(dd->control_reg) & dd->enable_mask; in omap3_clkoutx2_recalc()
Ddpll44xx.c52 v = ti_clk_ll_ops->clk_readl(clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()
70 v = ti_clk_ll_ops->clk_readl(clk->clksel_reg); in omap4_dpllmx_deny_gatectrl()
131 v = ti_clk_ll_ops->clk_readl(dd->control_reg); in omap4_dpll_regm4xen_recalc()
Dclkt_iclk.c39 v = ti_clk_ll_ops->clk_readl(r); in omap2_clkt_iclk_allow_idle()
53 v = ti_clk_ll_ops->clk_readl(r); in omap2_clkt_iclk_deny_idle()
Dclkt_dpll.c216 v = ti_clk_ll_ops->clk_readl(dd->control_reg); in omap2_init_dpll_parent()
252 v = ti_clk_ll_ops->clk_readl(dd->control_reg); in omap2_get_dpll_rate()
259 v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg); in omap2_get_dpll_rate()
Dautoidle.c76 val = ti_clk_ll_ops->clk_readl(clk->reg); in _allow_autoidle()
90 val = ti_clk_ll_ops->clk_readl(clk->reg); in _deny_autoidle()
Dmux.c44 val = ti_clk_ll_ops->clk_readl(mux->reg) >> mux->shift; in ti_clk_mux_get_parent()
86 val = ti_clk_ll_ops->clk_readl(mux->reg); in ti_clk_mux_set_parent()
Ddivider.c105 val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift; in ti_clk_divider_recalc_rate()
233 val = ti_clk_ll_ops->clk_readl(divider->reg); in ti_clk_divider_set_rate()
Dgate.c81 orig_v = ti_clk_ll_ops->clk_readl(parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
Dclk.c87 ops->clk_readl = clk_memmap_readl; in ti_clk_setup_ll_ops()
/linux-4.4.14/drivers/clk/nxp/
Dclk-lpc18xx-cgu.c355 ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL); in lpc18xx_pll0_recalc_rate()
356 mdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV); in lpc18xx_pll0_recalc_rate()
357 npdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV); in lpc18xx_pll0_recalc_rate()
418 ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL); in lpc18xx_pll0_set_rate()
433 stat = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT); in lpc18xx_pll0_set_rate()
461 stat = clk_readl(pll->reg + LPC18XX_CGU_PLL1_STAT); in lpc18xx_pll1_recalc_rate()
462 ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL1_CTRL); in lpc18xx_pll1_recalc_rate()
Dclk-lpc18xx-ccu.c147 val = clk_readl(gate->reg); in lpc18xx_ccu_gate_endisable()
/linux-4.4.14/drivers/clk/
Dclk-multiplier.c35 val = clk_readl(mult->reg) >> mult->shift; in clk_multiplier_recalc_rate()
112 val = clk_readl(mult->reg); in clk_multiplier_set_rate()
Dclk-gate.c63 reg = clk_readl(gate->reg); in clk_gate_endisable()
96 reg = clk_readl(gate->reg); in clk_gate_is_enabled()
Dclk-fractional-divider.c35 val = clk_readl(fd->reg); in clk_fd_recalc_rate()
101 val = clk_readl(fd->reg); in clk_fd_set_rate()
Dclk-mux.c44 val = clk_readl(mux->reg) >> mux->shift; in clk_mux_get_parent()
93 val = clk_readl(mux->reg); in clk_mux_set_parent()
Dclk-divider.c145 val = clk_readl(divider->reg) >> divider->shift; in clk_divider_recalc_rate()
404 val = clk_readl(divider->reg); in clk_divider_set_rate()
/linux-4.4.14/include/linux/clk/
Dti.h227 u32 (*clk_readl)(void __iomem *reg); member
/linux-4.4.14/include/linux/
Dclk-provider.h756 static inline u32 clk_readl(u32 __iomem *reg) in clk_readl() function
768 static inline u32 clk_readl(u32 __iomem *reg) in clk_readl() function
/linux-4.4.14/drivers/clk/tegra/
Dclk-tegra124.c1568 plld_base = clk_readl(clk_base + PLLD_BASE); in tegra124_132_clock_init_pre()