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Searched refs:cgu (Results 1 – 21 of 21) sorted by relevance

/linux-4.4.14/drivers/clk/ingenic/
Dcgu.c43 ingenic_cgu_gate_get(struct ingenic_cgu *cgu, in ingenic_cgu_gate_get() argument
46 return readl(cgu->base + info->reg) & BIT(info->bit); in ingenic_cgu_gate_get()
60 ingenic_cgu_gate_set(struct ingenic_cgu *cgu, in ingenic_cgu_gate_set() argument
63 u32 clkgr = readl(cgu->base + info->reg); in ingenic_cgu_gate_set()
70 writel(clkgr, cgu->base + info->reg); in ingenic_cgu_gate_set()
81 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_recalc_rate() local
89 clk_info = &cgu->clock_info[ingenic_clk->idx]; in ingenic_pll_recalc_rate()
93 spin_lock_irqsave(&cgu->lock, flags); in ingenic_pll_recalc_rate()
94 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_recalc_rate()
95 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_pll_recalc_rate()
[all …]
Djz4740-cgu.c54 static struct ingenic_cgu *cgu; variable
220 cgu = ingenic_cgu_new(jz4740_cgu_clocks, in jz4740_cgu_init()
222 if (!cgu) { in jz4740_cgu_init()
227 retval = ingenic_cgu_register_clocks(cgu); in jz4740_cgu_init()
235 uint32_t lcr = readl(cgu->base + CGU_REG_LCR); in jz4740_clock_set_wait_mode()
247 writel(lcr, cgu->base + CGU_REG_LCR); in jz4740_clock_set_wait_mode()
252 uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR); in jz4740_clock_udc_disable_auto_suspend()
255 writel(clkgr, cgu->base + CGU_REG_CLKGR); in jz4740_clock_udc_disable_auto_suspend()
261 uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR); in jz4740_clock_udc_enable_auto_suspend()
264 writel(clkgr, cgu->base + CGU_REG_CLKGR); in jz4740_clock_udc_enable_auto_suspend()
[all …]
DMakefile1 obj-y += cgu.o
2 obj-$(CONFIG_MACH_JZ4740) += jz4740-cgu.o
3 obj-$(CONFIG_MACH_JZ4780) += jz4780-cgu.o
Djz4780-cgu.c98 static struct ingenic_cgu *cgu; variable
114 spin_lock_irqsave(&cgu->lock, flags); in jz4780_otg_phy_set_parent()
116 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_parent()
120 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_parent()
122 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_otg_phy_set_parent()
132 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_recalc_rate()
195 spin_lock_irqsave(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
197 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
200 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
202 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
[all …]
Dcgu.h193 struct ingenic_cgu *cgu; member
221 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu);
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Dlpc1850-ccu.txt47 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
48 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
49 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
50 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
61 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
62 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
63 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
64 <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
Dingenic,cgu.txt9 - compatible : Should be "ingenic,<soctype>-cgu".
10 For example "ingenic,jz4740-cgu" or "ingenic,jz4780-cgu".
18 may be found in <dt-bindings/clock/<soctype>-cgu.h>.
23 cgu: jz4740-cgu {
24 compatible = "ingenic,jz4740-cgu";
30 clocks = <&cgu JZ4740_CLK_UART0>;
49 &cgu {
Dlpc1850-cgu.txt23 Should be "nxp,lpc1850-cgu"
116 cgu: clock-controller@40050000 {
117 compatible = "nxp,lpc1850-cgu";
126 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
/linux-4.4.14/arch/mips/boot/dts/ingenic/
Djz4780.dtsi1 #include <dt-bindings/clock/jz4780-cgu.h>
37 cgu: jz4780-cgu@10000000 { label
38 compatible = "ingenic,jz4780-cgu";
54 clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
67 clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
80 clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
93 clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
106 clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
Djz4740.dtsi1 #include <dt-bindings/clock/jz4740-cgu.h>
37 cgu: jz4740-cgu@10000000 { label
38 compatible = "ingenic,jz4740-cgu";
54 clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
65 clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
/linux-4.4.14/arch/arm/boot/dts/
Dlpc18xx.dtsi16 #include "dt-bindings/clock/lpc18xx-cgu.h"
163 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
201 cgu: clock-controller@40050000 { label
202 compatible = "nxp,lpc1850-cgu";
212 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
213 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
214 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
215 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
226 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
227 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/sound/
Dingenic,jz4740-i2s.txt17 clocks = <&cgu JZ4740_CLK_AIC>, <&cgu JZ4740_CLK_I2SPLL>;
/linux-4.4.14/arch/mips/boot/dts/lantiq/
Ddanube.dtsi52 cgu0: cgu@103000 {
53 compatible = "lantiq,cgu-xway";
/linux-4.4.14/drivers/clk/nxp/
DMakefile1 obj-$(CONFIG_ARCH_LPC18XX) += clk-lpc18xx-cgu.o
/linux-4.4.14/Documentation/devicetree/bindings/watchdog/
Dlpc18xx-wdt.txt16 clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>;
/linux-4.4.14/Documentation/devicetree/bindings/serial/
Dingenic,uart.txt21 clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
/linux-4.4.14/Documentation/devicetree/bindings/i2c/
Di2c-jz4780.txt28 clocks = <&cgu JZ4780_CLK_SMB4>;
/linux-4.4.14/Documentation/devicetree/bindings/reset/
Dnxp,lpc1850-rgu.txt68 clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
/linux-4.4.14/Documentation/devicetree/bindings/dma/
Djz4780-dma.txt30 clocks = <&cgu JZ4780_CLK_PDMA>;
/linux-4.4.14/Documentation/devicetree/bindings/memory-controllers/
Dingenic,jz4780-nemc.txt61 clocks = <&cgu JZ4780_CLK_NEMC>;
/linux-4.4.14/Documentation/devicetree/bindings/pinctrl/
Dlantiq,pinctrl-xway.txt50 spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio