43 ingenic_cgu_gate_get(struct ingenic_cgu *cgu,  in ingenic_cgu_gate_get()  argument
46 	return readl(cgu->base + info->reg) & BIT(info->bit);  in ingenic_cgu_gate_get()
60 ingenic_cgu_gate_set(struct ingenic_cgu *cgu,  in ingenic_cgu_gate_set()  argument
63 	u32 clkgr = readl(cgu->base + info->reg);  in ingenic_cgu_gate_set()
70 	writel(clkgr, cgu->base + info->reg);  in ingenic_cgu_gate_set()
81 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_pll_recalc_rate()  local
89 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_pll_recalc_rate()
93 	spin_lock_irqsave(&cgu->lock, flags);  in ingenic_pll_recalc_rate()
94 	ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_recalc_rate()
95 	spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_pll_recalc_rate()
160 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_pll_round_rate()  local
163 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_pll_round_rate()
175 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_pll_set_rate()  local
182 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_pll_set_rate()
192 	spin_lock_irqsave(&cgu->lock, flags);  in ingenic_pll_set_rate()
193 	ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_set_rate()
207 	writel(ctl, cgu->base + pll_info->reg);  in ingenic_pll_set_rate()
211 		ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_set_rate()
217 	spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_pll_set_rate()
238 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_get_parent()  local
243 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_clk_get_parent()
246 		reg = readl(cgu->base + clk_info->mux.reg);  in ingenic_clk_get_parent()
266 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_set_parent()  local
272 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_clk_set_parent()
297 		spin_lock_irqsave(&cgu->lock, flags);  in ingenic_clk_set_parent()
300 		reg = readl(cgu->base + clk_info->mux.reg);  in ingenic_clk_set_parent()
303 		writel(reg, cgu->base + clk_info->mux.reg);  in ingenic_clk_set_parent()
305 		spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_clk_set_parent()
316 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_recalc_rate()  local
321 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_clk_recalc_rate()
324 		div_reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_recalc_rate()
356 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_round_rate()  local
360 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_clk_round_rate()
375 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_set_rate()  local
383 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_clk_set_rate()
392 		spin_lock_irqsave(&cgu->lock, flags);  in ingenic_clk_set_rate()
393 		reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
409 		writel(reg, cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
414 				reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
423 		spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_clk_set_rate()
433 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_enable()  local
437 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_clk_enable()
441 		spin_lock_irqsave(&cgu->lock, flags);  in ingenic_clk_enable()
442 		ingenic_cgu_gate_set(cgu, &clk_info->gate, false);  in ingenic_clk_enable()
443 		spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_clk_enable()
452 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_disable()  local
456 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_clk_disable()
460 		spin_lock_irqsave(&cgu->lock, flags);  in ingenic_clk_disable()
461 		ingenic_cgu_gate_set(cgu, &clk_info->gate, true);  in ingenic_clk_disable()
462 		spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_clk_disable()
469 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_is_enabled()  local
474 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_clk_is_enabled()
477 		spin_lock_irqsave(&cgu->lock, flags);  in ingenic_clk_is_enabled()
478 		enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate);  in ingenic_clk_is_enabled()
479 		spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_clk_is_enabled()
502 static int ingenic_register_clock(struct ingenic_cgu *cgu, unsigned idx)  in ingenic_register_clock()  argument
504 	const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx];  in ingenic_register_clock()
515 		clk = of_clk_get_by_name(cgu->np, clk_info->name);  in ingenic_register_clock()
527 		cgu->clocks.clks[idx] = clk;  in ingenic_register_clock()
544 	ingenic_clk->cgu = cgu;  in ingenic_register_clock()
565 			parent = cgu->clocks.clks[clk_info->parents[i]];  in ingenic_register_clock()
576 		parent = cgu->clocks.clks[clk_info->parents[0]];  in ingenic_register_clock()
638 	cgu->clocks.clks[idx] = clk;  in ingenic_register_clock()
649 	struct ingenic_cgu *cgu;  in ingenic_cgu_new()  local
651 	cgu = kzalloc(sizeof(*cgu), GFP_KERNEL);  in ingenic_cgu_new()
652 	if (!cgu)  in ingenic_cgu_new()
655 	cgu->base = of_iomap(np, 0);  in ingenic_cgu_new()
656 	if (!cgu->base) {  in ingenic_cgu_new()
661 	cgu->np = np;  in ingenic_cgu_new()
662 	cgu->clock_info = clock_info;  in ingenic_cgu_new()
663 	cgu->clocks.clk_num = num_clocks;  in ingenic_cgu_new()
665 	spin_lock_init(&cgu->lock);  in ingenic_cgu_new()
667 	return cgu;  in ingenic_cgu_new()
670 	kfree(cgu);  in ingenic_cgu_new()
675 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu)  in ingenic_cgu_register_clocks()  argument
680 	cgu->clocks.clks = kcalloc(cgu->clocks.clk_num, sizeof(struct clk *),  in ingenic_cgu_register_clocks()
682 	if (!cgu->clocks.clks) {  in ingenic_cgu_register_clocks()
687 	for (i = 0; i < cgu->clocks.clk_num; i++) {  in ingenic_cgu_register_clocks()
688 		err = ingenic_register_clock(cgu, i);  in ingenic_cgu_register_clocks()
693 	err = of_clk_add_provider(cgu->np, of_clk_src_onecell_get,  in ingenic_cgu_register_clocks()
694 				  &cgu->clocks);  in ingenic_cgu_register_clocks()
701 	for (i = 0; i < cgu->clocks.clk_num; i++) {  in ingenic_cgu_register_clocks()
702 		if (!cgu->clocks.clks[i])  in ingenic_cgu_register_clocks()
704 		if (cgu->clock_info[i].type & CGU_CLK_EXT)  in ingenic_cgu_register_clocks()
705 			clk_put(cgu->clocks.clks[i]);  in ingenic_cgu_register_clocks()
707 			clk_unregister(cgu->clocks.clks[i]);  in ingenic_cgu_register_clocks()
709 	kfree(cgu->clocks.clks);  in ingenic_cgu_register_clocks()