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Searched refs:_MASKED_BIT_ENABLE (Results 1 – 9 of 9) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_pm.c299 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : in intel_set_memory_cxsr()
304 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : in intel_set_memory_cxsr()
5479 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in cherryview_enable_rps()
5588 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | in valleyview_enable_rps()
6379 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); in ironlake_init_clock_gating()
6450 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); in gen6_init_clock_gating()
6495 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); in gen6_init_clock_gating()
6503 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); in gen6_init_clock_gating()
6612 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); in broadwell_init_clock_gating()
6652 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); in haswell_init_clock_gating()
[all …]
Dintel_guc_loader.c106 irqs |= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING); in direct_interrupts_to_guc()
266 I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA)); in guc_ucode_xfer_dma()
Dintel_ringbuffer.c535 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | in intel_ring_setup_status_page()
549 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); in stop_ring()
794 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
1050 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); in skl_init_workarounds()
1169 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); in init_render_ring()
1178 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); in init_render_ring()
1184 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); in init_render_ring()
1189 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | in init_render_ring()
1190 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); in init_render_ring()
1203 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); in init_render_ring()
[all …]
Dintel_lrc.c986 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); in intel_logical_ring_stop()
1348 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING)); in gen9_init_perctx_bb()
1483 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); in gen8_init_common_ring()
1531 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); in gen8_init_render_ring()
1533 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); in gen8_init_render_ring()
2274 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | in populate_lr_context()
Dintel_uncore.c1082 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL); in fw_domain_init()
1493 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)); in gen8_do_reset()
Di915_gem_context.c562 intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); in mi_set_context()
Di915_gem_gtt.c1744 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); in gen8_ppgtt_enable()
1770 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in gen7_ppgtt_enable()
1789 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in gen6_ppgtt_enable()
Di915_gem.c4679 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); in i915_gem_init_swizzling()
4681 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); in i915_gem_init_swizzling()
4683 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); in i915_gem_init_swizzling()
Di915_reg.h46 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) macro