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Searched refs:REG (Results 1 – 72 of 72) sorted by relevance

/linux-4.4.14/drivers/net/ethernet/apple/
Dmace.h13 #define REG(x) volatile unsigned char x; char x ## _pad[15] macro
16 REG(rcvfifo); /* receive FIFO */
17 REG(xmtfifo); /* transmit FIFO */
18 REG(xmtfc); /* transmit frame control */
19 REG(xmtfs); /* transmit frame status */
20 REG(xmtrc); /* transmit retry count */
21 REG(rcvfc); /* receive frame control */
22 REG(rcvfs); /* receive frame status (4 bytes) */
23 REG(fifofc); /* FIFO frame count */
24 REG(ir); /* interrupt register */
[all …]
/linux-4.4.14/tools/perf/arch/x86/util/
Dunwind-libdw.c12 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
19 dwarf_regs[0] = REG(AX); in libdw__arch_set_initial_registers()
20 dwarf_regs[1] = REG(CX); in libdw__arch_set_initial_registers()
21 dwarf_regs[2] = REG(DX); in libdw__arch_set_initial_registers()
22 dwarf_regs[3] = REG(BX); in libdw__arch_set_initial_registers()
23 dwarf_regs[4] = REG(SP); in libdw__arch_set_initial_registers()
24 dwarf_regs[5] = REG(BP); in libdw__arch_set_initial_registers()
25 dwarf_regs[6] = REG(SI); in libdw__arch_set_initial_registers()
26 dwarf_regs[7] = REG(DI); in libdw__arch_set_initial_registers()
27 dwarf_regs[8] = REG(IP); in libdw__arch_set_initial_registers()
[all …]
/linux-4.4.14/tools/perf/arch/arm/util/
Dunwind-libdw.c11 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
17 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers()
18 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
19 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
20 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
21 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
22 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
23 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
24 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
25 dwarf_regs[8] = REG(R8); in libdw__arch_set_initial_registers()
[all …]
/linux-4.4.14/arch/m68k/lib/
Dmulsi3.S61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
[all …]
Dmodsi3.S61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
[all …]
Dumodsi3.S61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
[all …]
Ddivsi3.S61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
[all …]
Dudivsi3.S61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
[all …]
/linux-4.4.14/arch/sparc/include/asm/
Dtrap_block.h112 #define __GET_CPUID(REG) \ argument
114 661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
115 srlx REG, 17, REG; \
116 and REG, 0x1f, REG; \
122 ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
123 srlx REG, 17, REG; \
124 and REG, 0x3ff, REG; \
127 ldxa [%g0] ASI_JBUS_CONFIG, REG; \
128 srlx REG, 17, REG; \
129 and REG, 0x1f, REG; \
[all …]
Dasm.h13 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
14 brz,PREDICT REG, DEST
15 #define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \ argument
16 brz,a,PREDICT REG, DEST
17 #define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \ argument
18 brnz,PREDICT REG, DEST
19 #define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \ argument
20 brnz,a,PREDICT REG, DEST
26 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
27 cmp REG, 0; \
[all …]
Dtsb.h76 #define TSB_LOAD_QUAD(TSB, REG) \ argument
77 661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
80 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
81 ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
84 #define TSB_LOAD_TAG_HIGH(TSB, REG) \ argument
85 661: lduwa [TSB] ASI_N, REG; \
88 lduwa [TSB] ASI_PHYS_USE_EC, REG; \
91 #define TSB_LOAD_TAG(TSB, REG) \ argument
92 661: ldxa [TSB] ASI_N, REG; \
95 ldxa [TSB] ASI_PHYS_USE_EC, REG; \
/linux-4.4.14/drivers/gpu/drm/i2c/
Dtda998x_drv.c69 #define REG(page, addr) (((page) << 8) | (addr)) macro
77 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
78 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
85 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
86 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
89 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
90 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
91 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
95 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
97 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
[all …]
/linux-4.4.14/arch/mips/ar7/
Dirq.c46 #define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr)) macro
55 REG(ESR_OFFSET(d->irq - ar7_irq_base))); in ar7_unmask_irq()
61 REG(ECR_OFFSET(d->irq - ar7_irq_base))); in ar7_mask_irq()
67 REG(CR_OFFSET(d->irq - ar7_irq_base))); in ar7_ack_irq()
72 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); in ar7_unmask_sec_irq()
77 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); in ar7_mask_sec_irq()
82 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); in ar7_ack_sec_irq()
111 writel(0xffffffff, REG(ECR_OFFSET(0))); in ar7_irq_init()
112 writel(0xff, REG(ECR_OFFSET(32))); in ar7_irq_init()
113 writel(0xffffffff, REG(SEC_ECR_OFFSET)); in ar7_irq_init()
[all …]
/linux-4.4.14/arch/arm/mach-netx/include/mach/
Duncompress.h29 #define REG(x) (*(volatile unsigned long *)(x)) macro
47 if (REG(UART1_BASE + UART_CR) & CR_UART_EN) in putc()
49 else if (REG(UART2_BASE + UART_CR) & CR_UART_EN) in putc()
54 while (REG(base + UART_FR) & FR_TXFF); in putc()
55 REG(base + UART_DR) = c; in putc()
62 if (REG(UART1_BASE + UART_CR) & CR_UART_EN) in flush()
64 else if (REG(UART2_BASE + UART_CR) & CR_UART_EN) in flush()
69 while (REG(base + UART_FR) & FR_BUSY); in flush()
/linux-4.4.14/drivers/regulator/
Drn5t618-regulator.c31 #define REG(rid, ereg, emask, vreg, vmask, min, max, step) \ macro
51 REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500),
52 REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500),
53 REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500),
55 REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000),
56 REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000),
57 REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000),
58 REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000),
59 REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000),
61 REG(LDORTC1, LDOEN2, BIT(4), LDORTCDAC, 0x7f, 1700000, 3500000, 25000),
[all …]
Dmc13783-regulator.c248 MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
250 MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
259 MC13783_FIXED_DEFINE(REG, VAUDIO, REGULATORMODE0, mc13783_vaudio_val),
260 MC13783_FIXED_DEFINE(REG, VIOHI, REGULATORMODE0, mc13783_viohi_val),
279 MC13783_FIXED_DEFINE(REG, VRFBG, REGULATORMODE1, mc13783_vrfbg_val),
290 MC13783_GPO_DEFINE(REG, GPO1, POWERMISC, mc13783_gpo_val),
291 MC13783_GPO_DEFINE(REG, GPO2, POWERMISC, mc13783_gpo_val),
292 MC13783_GPO_DEFINE(REG, GPO3, POWERMISC, mc13783_gpo_val),
293 MC13783_GPO_DEFINE(REG, GPO4, POWERMISC, mc13783_gpo_val),
294 MC13783_GPO_DEFINE(REG, PWGT1SPI, POWERMISC, mc13783_pwgtdrv_val),
[all …]
/linux-4.4.14/arch/arm64/kernel/
Dhw_breakpoint.c69 #define READ_WB_REG_CASE(OFF, N, REG, VAL) \ argument
71 AARCH64_DBG_READ(N, REG, VAL); \
74 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \ argument
76 AARCH64_DBG_WRITE(N, REG, VAL); \
79 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \ argument
80 READ_WB_REG_CASE(OFF, 0, REG, VAL); \
81 READ_WB_REG_CASE(OFF, 1, REG, VAL); \
82 READ_WB_REG_CASE(OFF, 2, REG, VAL); \
83 READ_WB_REG_CASE(OFF, 3, REG, VAL); \
84 READ_WB_REG_CASE(OFF, 4, REG, VAL); \
[all …]
/linux-4.4.14/drivers/watchdog/
Dit8712f_wdt.c61 #define REG 0x2e /* The register to read/write */ macro
99 outb(reg, REG); in superio_inb()
105 outb(reg, REG); in superio_outb()
112 outb(reg++, REG); in superio_inw()
114 outb(reg, REG); in superio_inw()
121 outb(LDN, REG); in superio_select()
130 if (!request_muxed_region(REG, 2, NAME)) in superio_enter()
133 outb(0x87, REG); in superio_enter()
134 outb(0x01, REG); in superio_enter()
135 outb(0x55, REG); in superio_enter()
[all …]
Dit87_wdt.c64 #define REG 0x2e macro
179 if (!request_muxed_region(REG, 2, WATCHDOG_NAME)) in superio_enter()
182 outb(0x87, REG); in superio_enter()
183 outb(0x01, REG); in superio_enter()
184 outb(0x55, REG); in superio_enter()
185 outb(0x55, REG); in superio_enter()
191 outb(0x02, REG); in superio_exit()
193 release_region(REG, 2); in superio_exit()
198 outb(LDNREG, REG); in superio_select()
204 outb(reg, REG); in superio_inb()
[all …]
/linux-4.4.14/drivers/gpio/
Dgpio-it87.c42 #define REG 0x2e macro
92 if (!request_muxed_region(REG, 2, KBUILD_MODNAME)) in superio_enter()
95 outb(0x87, REG); in superio_enter()
96 outb(0x01, REG); in superio_enter()
97 outb(0x55, REG); in superio_enter()
98 outb(0x55, REG); in superio_enter()
104 outb(0x02, REG); in superio_exit()
106 release_region(REG, 2); in superio_exit()
111 outb(LDNREG, REG); in superio_select()
117 outb(reg, REG); in superio_inb()
[all …]
/linux-4.4.14/sound/oss/
Dpss.c73 #define REG(x) (devc->base+x) macro
168 if (inw(REG(PSS_STATUS)) & PSS_WRITE_EMPTY) in pss_write()
170 outw(data, REG(PSS_DATA)); in pss_write()
195 id = inw(REG(PSS_ID)); in probe_pss()
224 tmp = inw(REG(dev)) & ~0x38; /* Load confreg, mask IRQ bits out */ in set_irq()
231 outw(tmp | bits, REG(dev)); in set_irq()
237 unsigned short tmp = inw(REG(dev)) & 0x003f; in set_io_base()
240 outw(bits | tmp, REG(dev)); in set_io_base()
256 tmp = inw(REG(dev)) & ~0x07; /* Load confreg, mask DMA bits out */ in set_dma()
263 outw(tmp | bits, REG(dev)); in set_dma()
[all …]
/linux-4.4.14/drivers/block/
Dswim.c44 #define REG(x) unsigned char x, x ## _pad[0x200 - 1]; macro
47 REG(write_data)
48 REG(write_mark)
49 REG(write_CRC)
50 REG(write_parameter)
51 REG(write_phase)
52 REG(write_setup)
53 REG(write_mode0)
54 REG(write_mode1)
56 REG(read_data)
[all …]
Dswim3.c59 #define REG(x) unsigned char x; char x ## _pad[15]; macro
66 REG(data);
67 REG(timer); /* counts down at 1MHz */
68 REG(error);
69 REG(mode);
70 REG(select); /* controls CA0, CA1, CA2 and LSTRB signals */
71 REG(setup);
72 REG(control); /* writing bits clears them */
73 REG(status); /* writing bits sets them in control */
74 REG(intr);
[all …]
/linux-4.4.14/drivers/gpu/drm/tilcdc/
Dtilcdc_drv.c446 #define REG(rev, save, reg) { #reg, rev, save, reg } macro
448 REG(1, false, LCDC_PID_REG),
449 REG(1, true, LCDC_CTRL_REG),
450 REG(1, false, LCDC_STAT_REG),
451 REG(1, true, LCDC_RASTER_CTRL_REG),
452 REG(1, true, LCDC_RASTER_TIMING_0_REG),
453 REG(1, true, LCDC_RASTER_TIMING_1_REG),
454 REG(1, true, LCDC_RASTER_TIMING_2_REG),
455 REG(1, true, LCDC_DMA_CTRL_REG),
456 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
[all …]
/linux-4.4.14/arch/sparc/net/
Dbpf_jit_comp.c91 #define SETHI(K, REG) \ argument
92 (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff))
93 #define OR_LO(K, REG) \ argument
94 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
149 #define emit_clear(REG) \ argument
151 *prog++ = OR | RS1(G0) | RS2(G0) | RD(REG); \
154 #define emit_set_const(K, REG) \ argument
156 *prog++ = SETHI(K, REG); \
158 *prog++ = OR_LO(K, REG); \
253 #define emit_load_cpu(REG) \ argument
[all …]
/linux-4.4.14/drivers/scsi/
Dsun3x_esp.c42 #define dma_read32(REG) \
43 readl(esp->dma_regs + (REG))
44 #define dma_write32(VAL, REG) \
45 writel((VAL), esp->dma_regs + (REG))
47 #define dma_read32(REG) \ argument
48 *(volatile u32 *)(esp->dma_regs + (REG))
49 #define dma_write32(VAL, REG) \ argument
50 do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0)
Dncr53c8xx.h911 #define REG(r) REGJ (nc_, r) macro
1101 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1104 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1107 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1173 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1176 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
Dmac_esp.c48 #define esp_read8(REG) mac_esp_read8(esp, REG) argument
49 #define esp_write8(VAL, REG) mac_esp_write8(esp, VAL, REG) argument
Dsun_esp.c30 #define dma_read32(REG) \ argument
31 sbus_readl(esp->dma_regs + (REG))
32 #define dma_write32(VAL, REG) \ argument
33 sbus_writel((VAL), esp->dma_regs + (REG))
Desp_scsi.c115 #define esp_read8(REG) esp->ops->esp_read8(esp, REG) argument
116 #define esp_write8(VAL,REG) esp->ops->esp_write8(esp, VAL, REG) argument
Dncr53c8xx.c2001 #define RADDR(label) (RELOC_REGISTER | REG(label))
2002 #define FADDR(label,ofs)(RELOC_REGISTER | ((REG(label))+(ofs)))
/linux-4.4.14/arch/arm64/include/asm/
Dhw_breakpoint.h99 #define AARCH64_DBG_READ(N, REG, VAL) do {\ argument
100 asm volatile("mrs %0, dbg" REG #N "_el1" : "=r" (VAL));\
103 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\ argument
104 asm volatile("msr dbg" REG #N "_el1, %0" :: "r" (VAL));\
/linux-4.4.14/fs/proc/
Dbase.c131 #define REG(NAME, MODE, fops) \ macro
2412 REG("current", S_IRUGO|S_IWUGO, proc_pid_attr_operations),
2413 REG("prev", S_IRUGO, proc_pid_attr_operations),
2414 REG("exec", S_IRUGO|S_IWUGO, proc_pid_attr_operations),
2415 REG("fscreate", S_IRUGO|S_IWUGO, proc_pid_attr_operations),
2416 REG("keycreate", S_IRUGO|S_IWUGO, proc_pid_attr_operations),
2417 REG("sockcreate", S_IRUGO|S_IWUGO, proc_pid_attr_operations),
2742 REG("environ", S_IRUSR, proc_environ_operations),
2748 REG("sched", S_IRUGO|S_IWUSR, proc_pid_sched_operations),
2751 REG("autogroup", S_IRUGO|S_IWUSR, proc_pid_sched_autogroup_operations),
[all …]
/linux-4.4.14/drivers/iio/magnetometer/
Dmmc35240.c75 #define MMC35240_OTP_CONVERT_Y(REG) (((REG) >= 32 ? (32 - (REG)) : (REG)) * 6) argument
78 #define MMC35240_OTP_CONVERT_Z(REG) (((REG) >= 32 ? (32 - (REG)) : (REG)) * 81) argument
/linux-4.4.14/drivers/net/ethernet/freescale/fs_enet/
Dmii-fec.c46 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) argument
47 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) argument
Dmac-fcc.c73 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) argument
74 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) argument
/linux-4.4.14/arch/sparc/kernel/
Dpsycho_common.h14 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \ argument
17 ((unsigned long)(REG)))
Dprom_irqtrans.c101 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \ argument
104 ((unsigned long)(REG)))
Dpci_schizo.c73 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \ argument
76 ((unsigned long)(REG)))
/linux-4.4.14/drivers/hwmon/
Dsmsc47b397.c54 #define REG 0x2e /* The register to read/write */ macro
59 outb(reg, REG); in superio_outb()
65 outb(reg, REG); in superio_inb()
77 outb(0x55, REG); in superio_enter()
82 outb(0xAA, REG); in superio_exit()
Dsmsc47m1.c56 #define REG 0x2e /* The register to read/write */ macro
62 outb(reg, REG); in superio_outb()
69 outb(reg, REG); in superio_inb()
79 outb(0x55, REG); in superio_enter()
85 outb(0xAA, REG); in superio_exit()
Dit87.c83 #define REG 0x2e /* The register to read/write */ macro
96 outb(reg, REG); in superio_inb()
102 outb(reg, REG); in superio_outb()
109 outb(reg++, REG); in superio_inw()
111 outb(reg, REG); in superio_inw()
118 outb(DEV, REG); in superio_select()
127 if (!request_muxed_region(REG, 2, DRVNAME)) in superio_enter()
130 outb(0x87, REG); in superio_enter()
131 outb(0x01, REG); in superio_enter()
132 outb(0x55, REG); in superio_enter()
[all …]
Dasb100.c261 #define set_in_reg(REG, reg) \ argument
274 asb100_write_value(client, ASB100_REG_IN_##REG(nr), \
443 #define set_temp_reg(REG, reg) \ argument
463 asb100_write_value(client, ASB100_REG_TEMP_##REG(nr+1), \
Dw83781d.c272 #define store_in_reg(REG, reg) \ argument
285 w83781d_write_value(data, W83781D_REG_IN_##REG(nr), \
377 #define store_temp_reg(REG, reg) \ argument
392 w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \
396 w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \
Dw83l786ng.c249 #define store_in_reg(REG, reg) \ argument
263 w83l786ng_write_value(client, W83L786NG_REG_IN_##REG(nr), \
Dw83627ehf.c952 #define store_in_reg(REG, reg) \ in show_in_reg() argument
968 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \ in show_in_reg()
1618 #define fan_functions(reg, REG) \ argument
1644 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
1654 #define fan_time_functions(reg, REG) \ in fan_functions() argument
1683 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
Dw83791d.c381 #define store_in_reg(REG, reg) \ argument
397 w83791d_write(client, W83791D_REG_IN_##REG[nr], data->in_##reg[nr]); \
Dw83792d.c381 #define store_in_reg(REG, reg) \ argument
397 w83792d_write_value(client, W83792D_REG_IN_##REG[nr], \
/linux-4.4.14/arch/powerpc/xmon/
Dxmon.c176 #define REG "%.16lx" macro
178 #define REG "%.8lx" macro
1144 printf("csum stopped at "REG"\n", adrs+i); in csum()
1282 printf(" data "REG" [", dabr.address); in bpt_cmds()
1417 printf("["REG"] ", sp); in xmon_show_stack()
1423 printf("["REG"] ", sp); in xmon_show_stack()
1542 printf("*** Error reading registers from "REG"\n", in prregs()
1553 printf("R%.2ld = "REG" R%.2ld = "REG"\n", in prregs()
1557 printf("R%.2ld = "REG" R%.2ld = "REG"\n", in prregs()
1578 printf("msr = "REG" cr = %.8lx\n", fp->msr, fp->ccr); in prregs()
[all …]
/linux-4.4.14/arch/powerpc/kernel/
Dprocess.c1002 #define REG "%016lx" macro
1006 #define REG "%08lx" macro
1017 printk("NIP: "REG" LR: "REG" CTR: "REG"\n", in show_regs()
1021 printk("MSR: "REG" ", regs->msr); in show_regs()
1026 printk("CFAR: "REG" ", regs->orig_gpr3); in show_regs()
1029 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); in show_regs()
1031 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); in show_regs()
1044 printk(REG " ", regs->gpr[i]); in show_regs()
1054 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); in show_regs()
1055 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); in show_regs()
[all …]
/linux-4.4.14/drivers/scsi/sym53c8xx_2/
Dsym_defs.h385 #define REG(r) REGJ (nc_, r) macro
585 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
588 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
591 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
657 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
660 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
Dsym_fw.h197 #define RADDR_1(label) (RELOC_REGISTER | REG(label))
198 #define RADDR_2(label,ofs) (RELOC_REGISTER | ((REG(label))+(ofs)))
/linux-4.4.14/drivers/media/dvb-frontends/
Dstb0899_priv.h255 #define STB0899_READ_S2REG(DEVICE, REG) (_stb0899_read_s2reg(state, DEVICE, STB0899_BASE_##REG, ST… argument
/linux-4.4.14/Documentation/metag/
Dkernel-ABI.txt49 REG (ALIAS) PURPOSE
59 D0 REG (ALIAS) PURPOSE D1 REG (ALIAS) PURPOSE
70 A0 REG (ALIAS) PURPOSE A1 REG (ALIAS) PURPOSE
154 D0 REG (ALIAS) VALUE D1 REG (ALIAS) VALUE
/linux-4.4.14/Documentation/ABI/testing/
Dsysfs-driver-pciback7 the format of DDDD:BB:DD.F-REG:SIZE:MASK will allow the guest
/linux-4.4.14/drivers/isdn/hardware/eicon/
Ddebuglib.h143 DBG_DECL(REG)
197 #define DBG_REG(args) DBG_TEST(REG, args)
Ddebuglib.c61 DBG_FUNC(REG)
/linux-4.4.14/arch/powerpc/include/asm/
Dreg.h1079 #define MTFSF_L(REG) \ argument
1080 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
1082 #define MTFSF_L(REG) mtfsf 0xff, (REG) argument
/linux-4.4.14/sound/isa/wss/
Dwss_lib.c195 wss_outb(chip, CS4231P(REG), value); in snd_wss_dout()
208 wss_outb(chip, CS4231P(REG), value); in snd_wss_out()
226 return wss_inb(chip, CS4231P(REG)); in snd_wss_in()
234 wss_outb(chip, CS4231P(REG), in snd_cs4236_ext_out()
236 wss_outb(chip, CS4231P(REG), val); in snd_cs4236_ext_out()
247 wss_outb(chip, CS4231P(REG), in snd_cs4236_ext_in()
250 return wss_inb(chip, CS4231P(REG)); in snd_cs4236_ext_in()
254 res = wss_inb(chip, CS4231P(REG)); in snd_cs4236_ext_in()
/linux-4.4.14/Documentation/trace/
Duprobetracer.txt33 %REG : Fetch register REG
Dkprobetrace.txt37 %REG : Fetch register REG
/linux-4.4.14/tools/perf/Documentation/
Dperf-probe.txt155 [NAME=]LOCALVAR|$retval|%REG|@SYMBOL[:TYPE]
161 On x86 systems %REG is always the short form of the register: for example %AX. %RAX or %EAX is not …
/linux-4.4.14/Documentation/sound/alsa/soc/
Ddapm.txt104 SND_SOC_DAPM_DAC("HiFi DAC", "HiFi Playback", REG, 3, 1),
105 SND_SOC_DAPM_ADC("HiFi ADC", "HiFi Capture", REG, 2, 1),
/linux-4.4.14/drivers/video/fbdev/
Dcontrolfb.c119 #define CNTRL_REG(INFO,REG) (&(((INFO)->control_regs->REG).r)) argument
/linux-4.4.14/arch/arc/kernel/
Dentry-compact.S348 ; Restore REG File. In case multiple Events outstanding,
/linux-4.4.14/arch/m68k/ifpsp060/src/
Disp.S916 # MODE and REG are taken from the EXC_OPWORD.
923 # jump to the corresponding function for each {MODE,REG} pair.
Dpfpsp.S4575 # currently, MODE and REG are taken from the EXC_OPWORD. this could be
4583 # jump to the corresponding function for each {MODE,REG} pair.
Dfpsp.S18526 # currently, MODE and REG are taken from the EXC_OPWORD. this could be
18534 # jump to the corresponding function for each {MODE,REG} pair.
/linux-4.4.14/sound/sparc/
Dcs4231.c301 __cs4231_writeb(chip, value, CS4231U(chip, REG)); in snd_cs4231_dout()
333 return __cs4231_readb(chip, CS4231U(chip, REG)); in snd_cs4231_in()
/linux-4.4.14/drivers/net/ethernet/sun/
Dniu.c130 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ argument
132 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
169 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ argument
171 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
189 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \ argument
191 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
209 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ argument
211 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
/linux-4.4.14/drivers/mmc/host/
Dvub300.c224 #define REG(c) (0x01FFFF & (c->arg>>9)) macro
1865 u32 reg = REG(cmd); in satisfy_request_from_offloaded_data()
/linux-4.4.14/drivers/net/ethernet/broadcom/
Dtg3.c10829 #define TG3_STAT_ADD32(PSTAT, REG) \ argument
10830 do { u32 __val = tr32(REG); \