Lines Matching refs:REG
69 #define REG(page, addr) (((page) << 8) | (addr)) macro
77 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
78 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
85 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
86 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
89 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
90 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
91 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
95 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
97 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
98 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
99 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
101 #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
102 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
103 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
104 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
105 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
106 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
111 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
116 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
121 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
130 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
137 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
140 #define REG_MUX_AP REG(0x00, 0x26) /* read/write */
143 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
144 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
147 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
148 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
149 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
150 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
151 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
152 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
153 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
154 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
155 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
156 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
157 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
158 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
159 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
160 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
161 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
162 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
163 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
164 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
165 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
166 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
167 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
168 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
169 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
170 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
171 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
172 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
173 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
174 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
175 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
176 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
177 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
178 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
179 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
180 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
181 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
182 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
183 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
184 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
185 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
186 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
187 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
188 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
196 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
204 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
205 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
210 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
216 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
217 #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
219 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
227 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
231 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
234 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
238 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
239 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
240 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
241 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
242 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
243 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
244 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
245 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
246 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
253 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
257 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
261 #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
263 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
264 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
265 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
266 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
267 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
271 #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
272 #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
273 #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
274 #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
275 #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
279 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
285 #define REG_CA_I2S REG(0x11, 0x01) /* read/write */
288 #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
289 #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
290 #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
291 #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
292 #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
293 #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
294 #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
295 #define REG_CTS_N REG(0x11, 0x0c) /* read/write */
298 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
302 #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
305 #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
311 #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
315 #define REG_TX3 REG(0x12, 0x9a) /* read/write */
316 #define REG_TX4 REG(0x12, 0x9b) /* read/write */
318 #define REG_TX33 REG(0x12, 0xb8) /* read/write */