Searched refs:RADEON_READ (Results 1 – 5 of 5) sorted by relevance
84 return RADEON_READ(R600_CP_RB_RPTR); in radeon_get_ring_head()86 return RADEON_READ(RADEON_CP_RB_RPTR); in radeon_get_ring_head()115 return RADEON_READ(R600_SCRATCH_REG0 + 4*index); in radeon_get_scratch()117 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index); in radeon_get_scratch()125 ret = RADEON_READ(R520_MC_IND_DATA); in R500_READ_MCIND()134 ret = RADEON_READ(RS480_NB_MC_DATA); in RS480_READ_MCIND()143 ret = RADEON_READ(RS690_MC_DATA); in RS690_READ_MCIND()153 ret = RADEON_READ(RS600_MC_DATA); in RS600_READ_MCIND()172 return RADEON_READ(R700_MC_VM_FB_LOCATION); in radeon_read_fb_location()174 return RADEON_READ(R600_MC_VM_FB_LOCATION); in radeon_read_fb_location()[all …]
135 u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS); in radeon_acknowledge_irqs()146 disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS); in radeon_acknowledge_irqs()247 if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr) in radeon_wait_irq()253 RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr); in radeon_wait_irq()274 return RADEON_READ(R500_D1CRTC_FRAME_COUNT); in radeon_get_vblank_counter()276 return RADEON_READ(R500_D2CRTC_FRAME_COUNT); in radeon_get_vblank_counter()279 return RADEON_READ(RADEON_CRTC_CRNT_FRAME); in radeon_get_vblank_counter()281 return RADEON_READ(RADEON_CRTC2_CRNT_FRAME); in radeon_get_vblank_counter()
111 slots = (RADEON_READ(R600_GRBM_STATUS) in r600_do_wait_for_fifo()114 slots = (RADEON_READ(R600_GRBM_STATUS) in r600_do_wait_for_fifo()121 RADEON_READ(R600_GRBM_STATUS), in r600_do_wait_for_fifo()122 RADEON_READ(R600_GRBM_STATUS2)); in r600_do_wait_for_fifo()140 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE)) in r600_do_wait_for_idle()145 RADEON_READ(R600_GRBM_STATUS), in r600_do_wait_for_idle()146 RADEON_READ(R600_GRBM_STATUS2)); in r600_do_wait_for_idle()241 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE); in r600_vm_flush_gart_range()410 RADEON_READ(R600_GRBM_SOFT_RESET); in r600_cp_load_microcode()503 RADEON_READ(R600_GRBM_SOFT_RESET); in r700_cp_load_microcode()[all …]
2194 OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) | in radeon_do_init_pageflip()2197 OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) | in radeon_do_init_pageflip()
1848 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) macro