111 			slots = (RADEON_READ(R600_GRBM_STATUS)  in r600_do_wait_for_fifo()
114 			slots = (RADEON_READ(R600_GRBM_STATUS)  in r600_do_wait_for_fifo()
121 		 RADEON_READ(R600_GRBM_STATUS),  in r600_do_wait_for_fifo()
122 		 RADEON_READ(R600_GRBM_STATUS2));  in r600_do_wait_for_fifo()
140 		if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))  in r600_do_wait_for_idle()
145 		 RADEON_READ(R600_GRBM_STATUS),  in r600_do_wait_for_idle()
146 		 RADEON_READ(R600_GRBM_STATUS2));  in r600_do_wait_for_idle()
241 		resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);  in r600_vm_flush_gart_range()
410 	RADEON_READ(R600_GRBM_SOFT_RESET);  in r600_cp_load_microcode()
503 	RADEON_READ(R600_GRBM_SOFT_RESET);  in r700_cp_load_microcode()
566 			     RADEON_READ(R600_CP_RB_CNTL) |  in r600_test_writeback()
579 	cp_ptr = RADEON_READ(R600_CP_RB_WPTR);  in r600_do_engine_reset()
580 	cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);  in r600_do_engine_reset()
584 	RADEON_READ(R600_GRBM_SOFT_RESET);  in r600_do_engine_reset()
587 	RADEON_READ(R600_GRBM_SOFT_RESET);  in r600_do_engine_reset()
590 	cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);  in r600_do_engine_reset()
837 	ramcfg = RADEON_READ(R600_RAMCFG);  in r600_gfx_init()
872 	cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000;  in r600_gfx_init()
876 	cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;  in r600_gfx_init()
928 	sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);  in r600_gfx_init()
954 	sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);  in r600_gfx_init()
973 	sq_config = RADEON_READ(R600_SQ_CONFIG);  in r600_gfx_init()
1167 	hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);  in r600_gfx_init()
1170 	arb_pop = RADEON_READ(R600_ARB_POP);  in r600_gfx_init()
1487 	mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);  in r700_gfx_init()
1525 	cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000;  in r700_gfx_init()
1529 	cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;  in r700_gfx_init()
1582 	ta_aux_cntl = RADEON_READ(R600_TA_CNTL_AUX);  in r700_gfx_init()
1585 	sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);  in r700_gfx_init()
1589 	smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);  in r700_gfx_init()
1600 	db_debug3 = RADEON_READ(R700_DB_DEBUG3);  in r700_gfx_init()
1616 		db_debug4 = RADEON_READ(RV700_DB_DEBUG4);  in r700_gfx_init()
1658 	sq_config = RADEON_READ(R600_SQ_CONFIG);  in r700_gfx_init()
1771 	hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);  in r700_gfx_init()
1795 	RADEON_READ(R600_GRBM_SOFT_RESET);  in r600_cp_init_ring_buffer()
1902 		scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR) & 0xFFFFFFFC;  in r600_cp_init_ring_buffer()
1903 		scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;  in r600_cp_init_ring_buffer()
2361 	cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);  in r600_do_cp_reset()