84 			return RADEON_READ(R600_CP_RB_RPTR);  in radeon_get_ring_head()
86 			return RADEON_READ(RADEON_CP_RB_RPTR);  in radeon_get_ring_head()
115 			return RADEON_READ(R600_SCRATCH_REG0 + 4*index);  in radeon_get_scratch()
117 			return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);  in radeon_get_scratch()
125 	ret = RADEON_READ(R520_MC_IND_DATA);  in R500_READ_MCIND()
134 	ret = RADEON_READ(RS480_NB_MC_DATA);  in RS480_READ_MCIND()
143 	ret = RADEON_READ(RS690_MC_DATA);  in RS690_READ_MCIND()
153 	ret = RADEON_READ(RS600_MC_DATA);  in RS600_READ_MCIND()
172 		return RADEON_READ(R700_MC_VM_FB_LOCATION);  in radeon_read_fb_location()
174 		return RADEON_READ(R600_MC_VM_FB_LOCATION);  in radeon_read_fb_location()
185 		return RADEON_READ(RADEON_MC_FB_LOCATION);  in radeon_read_fb_location()
271 		tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;  in radeon_enable_bm()
278 		tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;  in radeon_enable_bm()
288 	return RADEON_READ(RADEON_CLOCK_CNTL_DATA);  in RADEON_READ_PLL()
294 	return RADEON_READ(RADEON_PCIE_DATA);  in RADEON_READ_PCIE()
302 	       (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));  in radeon_status()
304 	       (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));  in radeon_status()
306 	       (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));  in radeon_status()
308 	       (unsigned int)RADEON_READ(RADEON_AIC_CNTL));  in radeon_status()
310 	       (unsigned int)RADEON_READ(RADEON_AIC_STAT));  in radeon_status()
312 	       (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));  in radeon_status()
314 	       (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));  in radeon_status()
316 	       (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));  in radeon_status()
332 		tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);  in radeon_do_pixcache_flush()
337 			if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)  in radeon_do_pixcache_flush()
362 		int slots = (RADEON_READ(RADEON_RBBM_STATUS)  in radeon_do_wait_for_fifo()
369 		 RADEON_READ(RADEON_RBBM_STATUS),  in radeon_do_wait_for_fifo()
370 		 RADEON_READ(R300_VAP_CNTL_STATUS));  in radeon_do_wait_for_fifo()
390 		if (!(RADEON_READ(RADEON_RBBM_STATUS)  in radeon_do_wait_for_idle()
398 		 RADEON_READ(RADEON_RBBM_STATUS),  in radeon_do_wait_for_idle()
399 		 RADEON_READ(R300_VAP_CNTL_STATUS));  in radeon_do_wait_for_idle()
414 		uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);  in radeon_init_pipes()
424 		gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);  in radeon_init_pipes()
460 	RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);  in radeon_init_pipes()
461 	RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |  in radeon_init_pipes()
577 	tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);  in radeon_do_cp_flush()
651 	cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);  in radeon_do_cp_reset()
693 		clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);  in radeon_do_engine_reset()
705 	rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);  in radeon_do_engine_reset()
715 	RADEON_READ(RADEON_RBBM_SOFT_RESET);  in radeon_do_engine_reset()
724 	RADEON_READ(RADEON_RBBM_SOFT_RESET);  in radeon_do_engine_reset()
789 	cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);  in radeon_cp_init_ring_buffer()
830 	RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)  in radeon_cp_init_ring_buffer()
902 		RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |  in radeon_test_writeback()
1106 	tmp = RADEON_READ(RADEON_AIC_CNTL);  in radeon_set_pcigart()
1424 			RADEON_READ(RADEON_CONFIG_APER_SIZE);  in radeon_do_init_cp()
1509 		sctrl = RADEON_READ(RADEON_SURFACE_CNTL);  in radeon_do_init_cp()
2237 		RADEON_READ(R600_CP_RB_RPTR);  in radeon_commit_ring()
2241 		RADEON_READ(RADEON_CP_RB_RPTR);  in radeon_commit_ring()