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Searched refs:PIPE_B (Results 1 – 19 of 19) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_pm.c350 case PIPE_B: in vlv_get_fifo_size()
833 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) | in vlv_write_wm_values()
834 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | in vlv_write_wm_values()
845 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | in vlv_write_wm_values()
846 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); in vlv_write_wm_values()
858 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
859 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
860 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | in vlv_write_wm_values()
866 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | in vlv_write_wm_values()
867 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); in vlv_write_wm_values()
[all …]
Dintel_hdmi.c1110 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { in intel_disable_hdmi()
1702 if (ch == DPIO_CH0 && pipe == PIPE_B) in chv_hdmi_pre_pll_enable()
1714 if (pipe != PIPE_B) { in chv_hdmi_pre_pll_enable()
1735 if (pipe != PIPE_B) in chv_hdmi_pre_pll_enable()
1743 if (pipe != PIPE_B) in chv_hdmi_pre_pll_enable()
1755 if (pipe != PIPE_B) in chv_hdmi_pre_pll_enable()
1773 if (pipe != PIPE_B) { in chv_hdmi_post_pll_disable()
Dintel_dp.c330 else if (pipe == PIPE_B) in vlv_power_sequencer_kick()
377 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_power_sequencer_pipe()
462 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
1660 else if (crtc->pipe == PIPE_B) in intel_dp_prepare()
2677 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_steal_power_sequencer()
2914 if (ch == DPIO_CH0 && pipe == PIPE_B) in chv_dp_pre_pll_enable()
2926 if (pipe != PIPE_B) { in chv_dp_pre_pll_enable()
2947 if (pipe != PIPE_B) in chv_dp_pre_pll_enable()
2956 if (pipe != PIPE_B) in chv_dp_pre_pll_enable()
2969 if (pipe != PIPE_B) in chv_dp_pre_pll_enable()
[all …]
Di915_irq.c598 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
1646 case PIPE_B: in valleyview_pipestat_irq_handler()
3214 if (pipe_mask & 1 << PIPE_B) in gen8_irq_power_well_post_enable()
3215 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, in gen8_irq_power_well_post_enable()
3216 dev_priv->de_irq_mask[PIPE_B], in gen8_irq_power_well_post_enable()
3217 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); in gen8_irq_power_well_post_enable()
3658 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; in gen8_de_irq_postinstall()
3808 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
3990 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
4193 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
Dintel_panel.c522 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in _vlv_get_backlight()
627 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_set_backlight()
792 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_disable_backlight()
1021 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_enable_backlight()
1578 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_setup_backlight()
Dintel_dsi.c681 dpi_enabled = I915_READ(PIPECONF(PIPE_B)) & in intel_dsi_get_hw_state()
686 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1174 intel_encoder->crtc_mask = (1 << PIPE_B); in intel_dsi_init()
Dintel_runtime_pm.c221 1 << PIPE_C | 1 << PIPE_B); in hsw_power_well_post_enable()
245 1 << PIPE_C | 1 << PIPE_B); in skl_power_well_post_enable()
1044 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
1166 assert_pll_disabled(dev_priv, PIPE_B); in chv_dpio_cmn_power_well_disable()
Dintel_display.c1305 panel_pipe = PIPE_B; in assert_panel_unlocked()
1314 panel_pipe = PIPE_B; in assert_panel_unlocked()
1354 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in assert_pipe()
1773 I915_WRITE(DPLL(PIPE_B), in i9xx_disable_pll()
1774 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll()
1781 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in i9xx_disable_pll()
1803 if (pipe == PIPE_B) in vlv_disable_pll()
2151 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); in intel_enable_pipe()
2201 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in intel_disable_pipe()
2722 if (intel_crtc->pipe == PIPE_B) in i9xx_update_primary_plane()
[all …]
Di915_cmd_parser.c486 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)),
Di915_dma.c781 info->num_sprites[PIPE_B] = 2; in intel_device_info_runtime_init()
Dintel_sprite.c448 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) in vlv_update_plane()
Dintel_drv.h846 case PIPE_B: in vlv_pipe_to_channel()
Dintel_ddi.c1902 case PIPE_B: in intel_ddi_enable_transcoder_func()
2038 *pipe = PIPE_B; in intel_ddi_get_hw_state()
Di915_debugfs.c3451 .pipe = PIPE_B,
3642 case PIPE_B: in vlv_pipe_crc_ctl_reg()
3743 case PIPE_B: in vlv_undo_pipe_scramble_reset()
Dintel_sdvo.c1466 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { in intel_disable_sdvo()
Di915_drv.h117 PIPE_B, enumerator
Di915_reg.h33 (pipe) == PIPE_B ? (b) : (c))
/linux-4.4.14/drivers/video/fbdev/intelfb/
Dintelfbhw.h183 #define PIPE_B 1 macro
Dintelfbhw.c1062 if (pipe == PIPE_B) { in intelfbhw_mode_to_hw()
1305 if (dinfo->pipe == PIPE_B) { in intelfbhw_program_mode()