1305 			panel_pipe = PIPE_B;  in assert_panel_unlocked()
1314 			panel_pipe = PIPE_B;  in assert_panel_unlocked()
1354 	    (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))  in assert_pipe()
1773 		I915_WRITE(DPLL(PIPE_B),  in i9xx_disable_pll()
1774 			   I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);  in i9xx_disable_pll()
1781 	    (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))  in i9xx_disable_pll()
1803 	if (pipe == PIPE_B)  in vlv_disable_pll()
2151 			  (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));  in intel_enable_pipe()
2201 	    !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))  in intel_disable_pipe()
2722 		if (intel_crtc->pipe == PIPE_B)  in i9xx_update_primary_plane()
4103 	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);  in cpt_set_fdi_bc_bifurcation()
4122 	case PIPE_B:  in ivybridge_update_fdi_bc_bifurcation()
6154 	if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {  in valleyview_crtc_enable()
6527 	case PIPE_B:  in ironlake_check_fdi_lanes()
6550 		other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));  in ironlake_check_fdi_lanes()
7315 	if (crtc->pipe == PIPE_B)  in vlv_compute_dpll()
7346 	if (pipe == PIPE_B)  in vlv_prepare_pll()
7753 	    (pipe == PIPE_B || pipe == PIPE_C))  in intel_set_pipe_timings()
7839 	    (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))  in i9xx_set_pipeconf()
7989 		if (crtc->pipe != PIPE_B)  in i9xx_get_pfit_config()
9873 			trans_edp_pipe = PIPE_B;  in haswell_get_pipe_config()
12779 		    (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))  in check_crtc_state()