Searched refs:PCI_PM_CTRL_STATE_MASK (Results 1 – 12 of 12) sorted by relevance
124 old_state = (pci_power_t)(old_value & PCI_PM_CTRL_STATE_MASK); in pm_ctrl_write()125 new_state = (pci_power_t)(new_value & PCI_PM_CTRL_STATE_MASK); in pm_ctrl_write()
629 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; in pci_raw_set_power_state()635 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot in pci_raw_set_power_state()655 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); in pci_raw_set_power_state()704 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); in pci_update_current_state()1335 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); in pci_enable_device_flags()3498 csr &= ~PCI_PM_CTRL_STATE_MASK; in pci_pm_reset()3503 csr &= ~PCI_PM_CTRL_STATE_MASK; in pci_pm_reset()
1979 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) in quirk_e100_interrupt()
244 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ macro
630 switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) { in vfio_pm_config_write()670 p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK); in init_pci_cap_pm_perm()
3179 ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) | in bnx2x_set_power_state()3182 if (pmcsr & PCI_PM_CTRL_STATE_MASK) in bnx2x_set_power_state()3196 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; in bnx2x_set_power_state()
1430 (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0))) in bnx2x_is_nvm_accessible()
828 if (tmp & PCI_PM_CTRL_STATE_MASK) { in natsemi_probe1()830 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK; in natsemi_probe1()
4576 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; in cciss_controller_hard_reset()4583 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; in cciss_controller_hard_reset()
2527 pwr_cmd = (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | state; in radeonfb_whack_power_state()
3526 data &= ~PCI_PM_CTRL_STATE_MASK; in hw_cfg_wol_pme()
16478 pm_reg &= ~PCI_PM_CTRL_STATE_MASK; in tg3_get_invariants()