1/* 2 * VFIO PCI config space virtualization 3 * 4 * Copyright (C) 2012 Red Hat, Inc. All rights reserved. 5 * Author: Alex Williamson <alex.williamson@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Derived from original vfio: 12 * Copyright 2010 Cisco Systems, Inc. All rights reserved. 13 * Author: Tom Lyon, pugs@cisco.com 14 */ 15 16/* 17 * This code handles reading and writing of PCI configuration registers. 18 * This is hairy because we want to allow a lot of flexibility to the 19 * user driver, but cannot trust it with all of the config fields. 20 * Tables determine which fields can be read and written, as well as 21 * which fields are 'virtualized' - special actions and translations to 22 * make it appear to the user that he has control, when in fact things 23 * must be negotiated with the underlying OS. 24 */ 25 26#include <linux/fs.h> 27#include <linux/pci.h> 28#include <linux/uaccess.h> 29#include <linux/vfio.h> 30#include <linux/slab.h> 31 32#include "vfio_pci_private.h" 33 34#define PCI_CFG_SPACE_SIZE 256 35 36/* Useful "pseudo" capabilities */ 37#define PCI_CAP_ID_BASIC 0 38#define PCI_CAP_ID_INVALID 0xFF 39 40#define is_bar(offset) \ 41 ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \ 42 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4)) 43 44/* 45 * Lengths of PCI Config Capabilities 46 * 0: Removed from the user visible capability list 47 * FF: Variable length 48 */ 49static const u8 pci_cap_length[PCI_CAP_ID_MAX + 1] = { 50 [PCI_CAP_ID_BASIC] = PCI_STD_HEADER_SIZEOF, /* pci config header */ 51 [PCI_CAP_ID_PM] = PCI_PM_SIZEOF, 52 [PCI_CAP_ID_AGP] = PCI_AGP_SIZEOF, 53 [PCI_CAP_ID_VPD] = PCI_CAP_VPD_SIZEOF, 54 [PCI_CAP_ID_SLOTID] = 0, /* bridge - don't care */ 55 [PCI_CAP_ID_MSI] = 0xFF, /* 10, 14, 20, or 24 */ 56 [PCI_CAP_ID_CHSWP] = 0, /* cpci - not yet */ 57 [PCI_CAP_ID_PCIX] = 0xFF, /* 8 or 24 */ 58 [PCI_CAP_ID_HT] = 0xFF, /* hypertransport */ 59 [PCI_CAP_ID_VNDR] = 0xFF, /* variable */ 60 [PCI_CAP_ID_DBG] = 0, /* debug - don't care */ 61 [PCI_CAP_ID_CCRC] = 0, /* cpci - not yet */ 62 [PCI_CAP_ID_SHPC] = 0, /* hotswap - not yet */ 63 [PCI_CAP_ID_SSVID] = 0, /* bridge - don't care */ 64 [PCI_CAP_ID_AGP3] = 0, /* AGP8x - not yet */ 65 [PCI_CAP_ID_SECDEV] = 0, /* secure device not yet */ 66 [PCI_CAP_ID_EXP] = 0xFF, /* 20 or 44 */ 67 [PCI_CAP_ID_MSIX] = PCI_CAP_MSIX_SIZEOF, 68 [PCI_CAP_ID_SATA] = 0xFF, 69 [PCI_CAP_ID_AF] = PCI_CAP_AF_SIZEOF, 70}; 71 72/* 73 * Lengths of PCIe/PCI-X Extended Config Capabilities 74 * 0: Removed or masked from the user visible capabilty list 75 * FF: Variable length 76 */ 77static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = { 78 [PCI_EXT_CAP_ID_ERR] = PCI_ERR_ROOT_COMMAND, 79 [PCI_EXT_CAP_ID_VC] = 0xFF, 80 [PCI_EXT_CAP_ID_DSN] = PCI_EXT_CAP_DSN_SIZEOF, 81 [PCI_EXT_CAP_ID_PWR] = PCI_EXT_CAP_PWR_SIZEOF, 82 [PCI_EXT_CAP_ID_RCLD] = 0, /* root only - don't care */ 83 [PCI_EXT_CAP_ID_RCILC] = 0, /* root only - don't care */ 84 [PCI_EXT_CAP_ID_RCEC] = 0, /* root only - don't care */ 85 [PCI_EXT_CAP_ID_MFVC] = 0xFF, 86 [PCI_EXT_CAP_ID_VC9] = 0xFF, /* same as CAP_ID_VC */ 87 [PCI_EXT_CAP_ID_RCRB] = 0, /* root only - don't care */ 88 [PCI_EXT_CAP_ID_VNDR] = 0xFF, 89 [PCI_EXT_CAP_ID_CAC] = 0, /* obsolete */ 90 [PCI_EXT_CAP_ID_ACS] = 0xFF, 91 [PCI_EXT_CAP_ID_ARI] = PCI_EXT_CAP_ARI_SIZEOF, 92 [PCI_EXT_CAP_ID_ATS] = PCI_EXT_CAP_ATS_SIZEOF, 93 [PCI_EXT_CAP_ID_SRIOV] = PCI_EXT_CAP_SRIOV_SIZEOF, 94 [PCI_EXT_CAP_ID_MRIOV] = 0, /* not yet */ 95 [PCI_EXT_CAP_ID_MCAST] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF, 96 [PCI_EXT_CAP_ID_PRI] = PCI_EXT_CAP_PRI_SIZEOF, 97 [PCI_EXT_CAP_ID_AMD_XXX] = 0, /* not yet */ 98 [PCI_EXT_CAP_ID_REBAR] = 0xFF, 99 [PCI_EXT_CAP_ID_DPA] = 0xFF, 100 [PCI_EXT_CAP_ID_TPH] = 0xFF, 101 [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF, 102 [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */ 103 [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */ 104 [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */ 105}; 106 107/* 108 * Read/Write Permission Bits - one bit for each bit in capability 109 * Any field can be read if it exists, but what is read depends on 110 * whether the field is 'virtualized', or just pass thru to the 111 * hardware. Any virtualized field is also virtualized for writes. 112 * Writes are only permitted if they have a 1 bit here. 113 */ 114struct perm_bits { 115 u8 *virt; /* read/write virtual data, not hw */ 116 u8 *write; /* writeable bits */ 117 int (*readfn)(struct vfio_pci_device *vdev, int pos, int count, 118 struct perm_bits *perm, int offset, __le32 *val); 119 int (*writefn)(struct vfio_pci_device *vdev, int pos, int count, 120 struct perm_bits *perm, int offset, __le32 val); 121}; 122 123#define NO_VIRT 0 124#define ALL_VIRT 0xFFFFFFFFU 125#define NO_WRITE 0 126#define ALL_WRITE 0xFFFFFFFFU 127 128static int vfio_user_config_read(struct pci_dev *pdev, int offset, 129 __le32 *val, int count) 130{ 131 int ret = -EINVAL; 132 u32 tmp_val = 0; 133 134 switch (count) { 135 case 1: 136 { 137 u8 tmp; 138 ret = pci_user_read_config_byte(pdev, offset, &tmp); 139 tmp_val = tmp; 140 break; 141 } 142 case 2: 143 { 144 u16 tmp; 145 ret = pci_user_read_config_word(pdev, offset, &tmp); 146 tmp_val = tmp; 147 break; 148 } 149 case 4: 150 ret = pci_user_read_config_dword(pdev, offset, &tmp_val); 151 break; 152 } 153 154 *val = cpu_to_le32(tmp_val); 155 156 return pcibios_err_to_errno(ret); 157} 158 159static int vfio_user_config_write(struct pci_dev *pdev, int offset, 160 __le32 val, int count) 161{ 162 int ret = -EINVAL; 163 u32 tmp_val = le32_to_cpu(val); 164 165 switch (count) { 166 case 1: 167 ret = pci_user_write_config_byte(pdev, offset, tmp_val); 168 break; 169 case 2: 170 ret = pci_user_write_config_word(pdev, offset, tmp_val); 171 break; 172 case 4: 173 ret = pci_user_write_config_dword(pdev, offset, tmp_val); 174 break; 175 } 176 177 return pcibios_err_to_errno(ret); 178} 179 180static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos, 181 int count, struct perm_bits *perm, 182 int offset, __le32 *val) 183{ 184 __le32 virt = 0; 185 186 memcpy(val, vdev->vconfig + pos, count); 187 188 memcpy(&virt, perm->virt + offset, count); 189 190 /* Any non-virtualized bits? */ 191 if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) { 192 struct pci_dev *pdev = vdev->pdev; 193 __le32 phys_val = 0; 194 int ret; 195 196 ret = vfio_user_config_read(pdev, pos, &phys_val, count); 197 if (ret) 198 return ret; 199 200 *val = (phys_val & ~virt) | (*val & virt); 201 } 202 203 return count; 204} 205 206static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos, 207 int count, struct perm_bits *perm, 208 int offset, __le32 val) 209{ 210 __le32 virt = 0, write = 0; 211 212 memcpy(&write, perm->write + offset, count); 213 214 if (!write) 215 return count; /* drop, no writable bits */ 216 217 memcpy(&virt, perm->virt + offset, count); 218 219 /* Virtualized and writable bits go to vconfig */ 220 if (write & virt) { 221 __le32 virt_val = 0; 222 223 memcpy(&virt_val, vdev->vconfig + pos, count); 224 225 virt_val &= ~(write & virt); 226 virt_val |= (val & (write & virt)); 227 228 memcpy(vdev->vconfig + pos, &virt_val, count); 229 } 230 231 /* Non-virtualzed and writable bits go to hardware */ 232 if (write & ~virt) { 233 struct pci_dev *pdev = vdev->pdev; 234 __le32 phys_val = 0; 235 int ret; 236 237 ret = vfio_user_config_read(pdev, pos, &phys_val, count); 238 if (ret) 239 return ret; 240 241 phys_val &= ~(write & ~virt); 242 phys_val |= (val & (write & ~virt)); 243 244 ret = vfio_user_config_write(pdev, pos, phys_val, count); 245 if (ret) 246 return ret; 247 } 248 249 return count; 250} 251 252/* Allow direct read from hardware, except for capability next pointer */ 253static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos, 254 int count, struct perm_bits *perm, 255 int offset, __le32 *val) 256{ 257 int ret; 258 259 ret = vfio_user_config_read(vdev->pdev, pos, val, count); 260 if (ret) 261 return pcibios_err_to_errno(ret); 262 263 if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */ 264 if (offset < 4) 265 memcpy(val, vdev->vconfig + pos, count); 266 } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */ 267 if (offset == PCI_CAP_LIST_ID && count > 1) 268 memcpy(val, vdev->vconfig + pos, 269 min(PCI_CAP_FLAGS, count)); 270 else if (offset == PCI_CAP_LIST_NEXT) 271 memcpy(val, vdev->vconfig + pos, 1); 272 } 273 274 return count; 275} 276 277/* Raw access skips any kind of virtualization */ 278static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos, 279 int count, struct perm_bits *perm, 280 int offset, __le32 val) 281{ 282 int ret; 283 284 ret = vfio_user_config_write(vdev->pdev, pos, val, count); 285 if (ret) 286 return ret; 287 288 return count; 289} 290 291static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos, 292 int count, struct perm_bits *perm, 293 int offset, __le32 *val) 294{ 295 int ret; 296 297 ret = vfio_user_config_read(vdev->pdev, pos, val, count); 298 if (ret) 299 return pcibios_err_to_errno(ret); 300 301 return count; 302} 303 304/* Default capability regions to read-only, no-virtualization */ 305static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = { 306 [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read } 307}; 308static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = { 309 [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read } 310}; 311/* 312 * Default unassigned regions to raw read-write access. Some devices 313 * require this to function as they hide registers between the gaps in 314 * config space (be2net). Like MMIO and I/O port registers, we have 315 * to trust the hardware isolation. 316 */ 317static struct perm_bits unassigned_perms = { 318 .readfn = vfio_raw_config_read, 319 .writefn = vfio_raw_config_write 320}; 321 322static void free_perm_bits(struct perm_bits *perm) 323{ 324 kfree(perm->virt); 325 kfree(perm->write); 326 perm->virt = NULL; 327 perm->write = NULL; 328} 329 330static int alloc_perm_bits(struct perm_bits *perm, int size) 331{ 332 /* 333 * Round up all permission bits to the next dword, this lets us 334 * ignore whether a read/write exceeds the defined capability 335 * structure. We can do this because: 336 * - Standard config space is already dword aligned 337 * - Capabilities are all dword alinged (bits 0:1 of next reserved) 338 * - Express capabilities defined as dword aligned 339 */ 340 size = round_up(size, 4); 341 342 /* 343 * Zero state is 344 * - All Readable, None Writeable, None Virtualized 345 */ 346 perm->virt = kzalloc(size, GFP_KERNEL); 347 perm->write = kzalloc(size, GFP_KERNEL); 348 if (!perm->virt || !perm->write) { 349 free_perm_bits(perm); 350 return -ENOMEM; 351 } 352 353 perm->readfn = vfio_default_config_read; 354 perm->writefn = vfio_default_config_write; 355 356 return 0; 357} 358 359/* 360 * Helper functions for filling in permission tables 361 */ 362static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write) 363{ 364 p->virt[off] = virt; 365 p->write[off] = write; 366} 367 368/* Handle endian-ness - pci and tables are little-endian */ 369static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write) 370{ 371 *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt); 372 *(__le16 *)(&p->write[off]) = cpu_to_le16(write); 373} 374 375/* Handle endian-ness - pci and tables are little-endian */ 376static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write) 377{ 378 *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt); 379 *(__le32 *)(&p->write[off]) = cpu_to_le32(write); 380} 381 382/* 383 * Restore the *real* BARs after we detect a FLR or backdoor reset. 384 * (backdoor = some device specific technique that we didn't catch) 385 */ 386static void vfio_bar_restore(struct vfio_pci_device *vdev) 387{ 388 struct pci_dev *pdev = vdev->pdev; 389 u32 *rbar = vdev->rbar; 390 int i; 391 392 if (pdev->is_virtfn) 393 return; 394 395 pr_info("%s: %s reset recovery - restoring bars\n", 396 __func__, dev_name(&pdev->dev)); 397 398 for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++) 399 pci_user_write_config_dword(pdev, i, *rbar); 400 401 pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar); 402} 403 404static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar) 405{ 406 unsigned long flags = pci_resource_flags(pdev, bar); 407 u32 val; 408 409 if (flags & IORESOURCE_IO) 410 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO); 411 412 val = PCI_BASE_ADDRESS_SPACE_MEMORY; 413 414 if (flags & IORESOURCE_PREFETCH) 415 val |= PCI_BASE_ADDRESS_MEM_PREFETCH; 416 417 if (flags & IORESOURCE_MEM_64) 418 val |= PCI_BASE_ADDRESS_MEM_TYPE_64; 419 420 return cpu_to_le32(val); 421} 422 423/* 424 * Pretend we're hardware and tweak the values of the *virtual* PCI BARs 425 * to reflect the hardware capabilities. This implements BAR sizing. 426 */ 427static void vfio_bar_fixup(struct vfio_pci_device *vdev) 428{ 429 struct pci_dev *pdev = vdev->pdev; 430 int i; 431 __le32 *bar; 432 u64 mask; 433 434 bar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0]; 435 436 for (i = PCI_STD_RESOURCES; i <= PCI_STD_RESOURCE_END; i++, bar++) { 437 if (!pci_resource_start(pdev, i)) { 438 *bar = 0; /* Unmapped by host = unimplemented to user */ 439 continue; 440 } 441 442 mask = ~(pci_resource_len(pdev, i) - 1); 443 444 *bar &= cpu_to_le32((u32)mask); 445 *bar |= vfio_generate_bar_flags(pdev, i); 446 447 if (*bar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) { 448 bar++; 449 *bar &= cpu_to_le32((u32)(mask >> 32)); 450 i++; 451 } 452 } 453 454 bar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS]; 455 456 /* 457 * NB. we expose the actual BAR size here, regardless of whether 458 * we can read it. When we report the REGION_INFO for the ROM 459 * we report what PCI tells us is the actual ROM size. 460 */ 461 if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) { 462 mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1); 463 mask |= PCI_ROM_ADDRESS_ENABLE; 464 *bar &= cpu_to_le32((u32)mask); 465 } else 466 *bar = 0; 467 468 vdev->bardirty = false; 469} 470 471static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos, 472 int count, struct perm_bits *perm, 473 int offset, __le32 *val) 474{ 475 if (is_bar(offset)) /* pos == offset for basic config */ 476 vfio_bar_fixup(vdev); 477 478 count = vfio_default_config_read(vdev, pos, count, perm, offset, val); 479 480 /* Mask in virtual memory enable for SR-IOV devices */ 481 if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) { 482 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]); 483 u32 tmp_val = le32_to_cpu(*val); 484 485 tmp_val |= cmd & PCI_COMMAND_MEMORY; 486 *val = cpu_to_le32(tmp_val); 487 } 488 489 return count; 490} 491 492static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos, 493 int count, struct perm_bits *perm, 494 int offset, __le32 val) 495{ 496 struct pci_dev *pdev = vdev->pdev; 497 __le16 *virt_cmd; 498 u16 new_cmd = 0; 499 int ret; 500 501 virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND]; 502 503 if (offset == PCI_COMMAND) { 504 bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io; 505 u16 phys_cmd; 506 507 ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd); 508 if (ret) 509 return ret; 510 511 new_cmd = le32_to_cpu(val); 512 513 phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY); 514 virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY); 515 new_mem = !!(new_cmd & PCI_COMMAND_MEMORY); 516 517 phys_io = !!(phys_cmd & PCI_COMMAND_IO); 518 virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO); 519 new_io = !!(new_cmd & PCI_COMMAND_IO); 520 521 /* 522 * If the user is writing mem/io enable (new_mem/io) and we 523 * think it's already enabled (virt_mem/io), but the hardware 524 * shows it disabled (phys_mem/io, then the device has 525 * undergone some kind of backdoor reset and needs to be 526 * restored before we allow it to enable the bars. 527 * SR-IOV devices will trigger this, but we catch them later 528 */ 529 if ((new_mem && virt_mem && !phys_mem) || 530 (new_io && virt_io && !phys_io)) 531 vfio_bar_restore(vdev); 532 } 533 534 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 535 if (count < 0) 536 return count; 537 538 /* 539 * Save current memory/io enable bits in vconfig to allow for 540 * the test above next time. 541 */ 542 if (offset == PCI_COMMAND) { 543 u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO; 544 545 *virt_cmd &= cpu_to_le16(~mask); 546 *virt_cmd |= cpu_to_le16(new_cmd & mask); 547 } 548 549 /* Emulate INTx disable */ 550 if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) { 551 bool virt_intx_disable; 552 553 virt_intx_disable = !!(le16_to_cpu(*virt_cmd) & 554 PCI_COMMAND_INTX_DISABLE); 555 556 if (virt_intx_disable && !vdev->virq_disabled) { 557 vdev->virq_disabled = true; 558 vfio_pci_intx_mask(vdev); 559 } else if (!virt_intx_disable && vdev->virq_disabled) { 560 vdev->virq_disabled = false; 561 vfio_pci_intx_unmask(vdev); 562 } 563 } 564 565 if (is_bar(offset)) 566 vdev->bardirty = true; 567 568 return count; 569} 570 571/* Permissions for the Basic PCI Header */ 572static int __init init_pci_cap_basic_perm(struct perm_bits *perm) 573{ 574 if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF)) 575 return -ENOMEM; 576 577 perm->readfn = vfio_basic_config_read; 578 perm->writefn = vfio_basic_config_write; 579 580 /* Virtualized for SR-IOV functions, which just have FFFF */ 581 p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE); 582 p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE); 583 584 /* 585 * Virtualize INTx disable, we use it internally for interrupt 586 * control and can emulate it for non-PCI 2.3 devices. 587 */ 588 p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE); 589 590 /* Virtualize capability list, we might want to skip/disable */ 591 p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE); 592 593 /* No harm to write */ 594 p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE); 595 p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE); 596 p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE); 597 598 /* Virtualize all bars, can't touch the real ones */ 599 p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE); 600 p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE); 601 p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE); 602 p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE); 603 p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE); 604 p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE); 605 p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE); 606 607 /* Allow us to adjust capability chain */ 608 p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE); 609 610 /* Sometimes used by sw, just virtualize */ 611 p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE); 612 613 /* Virtualize interrupt pin to allow hiding INTx */ 614 p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE); 615 616 return 0; 617} 618 619static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos, 620 int count, struct perm_bits *perm, 621 int offset, __le32 val) 622{ 623 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 624 if (count < 0) 625 return count; 626 627 if (offset == PCI_PM_CTRL) { 628 pci_power_t state; 629 630 switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) { 631 case 0: 632 state = PCI_D0; 633 break; 634 case 1: 635 state = PCI_D1; 636 break; 637 case 2: 638 state = PCI_D2; 639 break; 640 case 3: 641 state = PCI_D3hot; 642 break; 643 } 644 645 pci_set_power_state(vdev->pdev, state); 646 } 647 648 return count; 649} 650 651/* Permissions for the Power Management capability */ 652static int __init init_pci_cap_pm_perm(struct perm_bits *perm) 653{ 654 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM])) 655 return -ENOMEM; 656 657 perm->writefn = vfio_pm_config_write; 658 659 /* 660 * We always virtualize the next field so we can remove 661 * capabilities from the chain if we want to. 662 */ 663 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 664 665 /* 666 * Power management is defined *per function*, so we can let 667 * the user change power state, but we trap and initiate the 668 * change ourselves, so the state bits are read-only. 669 */ 670 p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK); 671 return 0; 672} 673 674static int vfio_vpd_config_write(struct vfio_pci_device *vdev, int pos, 675 int count, struct perm_bits *perm, 676 int offset, __le32 val) 677{ 678 struct pci_dev *pdev = vdev->pdev; 679 __le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR); 680 __le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA); 681 u16 addr; 682 u32 data; 683 684 /* 685 * Write through to emulation. If the write includes the upper byte 686 * of PCI_VPD_ADDR, then the PCI_VPD_ADDR_F bit is written and we 687 * have work to do. 688 */ 689 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 690 if (count < 0 || offset > PCI_VPD_ADDR + 1 || 691 offset + count <= PCI_VPD_ADDR + 1) 692 return count; 693 694 addr = le16_to_cpu(*paddr); 695 696 if (addr & PCI_VPD_ADDR_F) { 697 data = le32_to_cpu(*pdata); 698 if (pci_write_vpd(pdev, addr & ~PCI_VPD_ADDR_F, 4, &data) != 4) 699 return count; 700 } else { 701 if (pci_read_vpd(pdev, addr, 4, &data) != 4) 702 return count; 703 *pdata = cpu_to_le32(data); 704 } 705 706 /* 707 * Toggle PCI_VPD_ADDR_F in the emulated PCI_VPD_ADDR register to 708 * signal completion. If an error occurs above, we assume that not 709 * toggling this bit will induce a driver timeout. 710 */ 711 addr ^= PCI_VPD_ADDR_F; 712 *paddr = cpu_to_le16(addr); 713 714 return count; 715} 716 717/* Permissions for Vital Product Data capability */ 718static int __init init_pci_cap_vpd_perm(struct perm_bits *perm) 719{ 720 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD])) 721 return -ENOMEM; 722 723 perm->writefn = vfio_vpd_config_write; 724 725 /* 726 * We always virtualize the next field so we can remove 727 * capabilities from the chain if we want to. 728 */ 729 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 730 731 /* 732 * Both the address and data registers are virtualized to 733 * enable access through the pci_vpd_read/write functions 734 */ 735 p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE); 736 p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE); 737 738 return 0; 739} 740 741/* Permissions for PCI-X capability */ 742static int __init init_pci_cap_pcix_perm(struct perm_bits *perm) 743{ 744 /* Alloc 24, but only 8 are used in v0 */ 745 if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2)) 746 return -ENOMEM; 747 748 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 749 750 p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE); 751 p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE); 752 return 0; 753} 754 755/* Permissions for PCI Express capability */ 756static int __init init_pci_cap_exp_perm(struct perm_bits *perm) 757{ 758 /* Alloc larger of two possible sizes */ 759 if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2)) 760 return -ENOMEM; 761 762 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 763 764 /* 765 * Allow writes to device control fields (includes FLR!) 766 * but not to devctl_phantom which could confuse IOMMU 767 * or to the ARI bit in devctl2 which is set at probe time 768 */ 769 p_setw(perm, PCI_EXP_DEVCTL, NO_VIRT, ~PCI_EXP_DEVCTL_PHANTOM); 770 p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI); 771 return 0; 772} 773 774/* Permissions for Advanced Function capability */ 775static int __init init_pci_cap_af_perm(struct perm_bits *perm) 776{ 777 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF])) 778 return -ENOMEM; 779 780 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 781 p_setb(perm, PCI_AF_CTRL, NO_VIRT, PCI_AF_CTRL_FLR); 782 return 0; 783} 784 785/* Permissions for Advanced Error Reporting extended capability */ 786static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm) 787{ 788 u32 mask; 789 790 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR])) 791 return -ENOMEM; 792 793 /* 794 * Virtualize the first dword of all express capabilities 795 * because it includes the next pointer. This lets us later 796 * remove capabilities from the chain if we need to. 797 */ 798 p_setd(perm, 0, ALL_VIRT, NO_WRITE); 799 800 /* Writable bits mask */ 801 mask = PCI_ERR_UNC_UND | /* Undefined */ 802 PCI_ERR_UNC_DLP | /* Data Link Protocol */ 803 PCI_ERR_UNC_SURPDN | /* Surprise Down */ 804 PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */ 805 PCI_ERR_UNC_FCP | /* Flow Control Protocol */ 806 PCI_ERR_UNC_COMP_TIME | /* Completion Timeout */ 807 PCI_ERR_UNC_COMP_ABORT | /* Completer Abort */ 808 PCI_ERR_UNC_UNX_COMP | /* Unexpected Completion */ 809 PCI_ERR_UNC_RX_OVER | /* Receiver Overflow */ 810 PCI_ERR_UNC_MALF_TLP | /* Malformed TLP */ 811 PCI_ERR_UNC_ECRC | /* ECRC Error Status */ 812 PCI_ERR_UNC_UNSUP | /* Unsupported Request */ 813 PCI_ERR_UNC_ACSV | /* ACS Violation */ 814 PCI_ERR_UNC_INTN | /* internal error */ 815 PCI_ERR_UNC_MCBTLP | /* MC blocked TLP */ 816 PCI_ERR_UNC_ATOMEG | /* Atomic egress blocked */ 817 PCI_ERR_UNC_TLPPRE; /* TLP prefix blocked */ 818 p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask); 819 p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask); 820 p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask); 821 822 mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */ 823 PCI_ERR_COR_BAD_TLP | /* Bad TLP Status */ 824 PCI_ERR_COR_BAD_DLLP | /* Bad DLLP Status */ 825 PCI_ERR_COR_REP_ROLL | /* REPLAY_NUM Rollover */ 826 PCI_ERR_COR_REP_TIMER | /* Replay Timer Timeout */ 827 PCI_ERR_COR_ADV_NFAT | /* Advisory Non-Fatal */ 828 PCI_ERR_COR_INTERNAL | /* Corrected Internal */ 829 PCI_ERR_COR_LOG_OVER; /* Header Log Overflow */ 830 p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask); 831 p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask); 832 833 mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */ 834 PCI_ERR_CAP_ECRC_CHKE; /* ECRC Check Enable */ 835 p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask); 836 return 0; 837} 838 839/* Permissions for Power Budgeting extended capability */ 840static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm) 841{ 842 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR])) 843 return -ENOMEM; 844 845 p_setd(perm, 0, ALL_VIRT, NO_WRITE); 846 847 /* Writing the data selector is OK, the info is still read-only */ 848 p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE); 849 return 0; 850} 851 852/* 853 * Initialize the shared permission tables 854 */ 855void vfio_pci_uninit_perm_bits(void) 856{ 857 free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]); 858 859 free_perm_bits(&cap_perms[PCI_CAP_ID_PM]); 860 free_perm_bits(&cap_perms[PCI_CAP_ID_VPD]); 861 free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]); 862 free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]); 863 free_perm_bits(&cap_perms[PCI_CAP_ID_AF]); 864 865 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]); 866 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]); 867} 868 869int __init vfio_pci_init_perm_bits(void) 870{ 871 int ret; 872 873 /* Basic config space */ 874 ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]); 875 876 /* Capabilities */ 877 ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]); 878 ret |= init_pci_cap_vpd_perm(&cap_perms[PCI_CAP_ID_VPD]); 879 ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]); 880 cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write; 881 ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]); 882 ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]); 883 884 /* Extended capabilities */ 885 ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]); 886 ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]); 887 ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write; 888 889 if (ret) 890 vfio_pci_uninit_perm_bits(); 891 892 return ret; 893} 894 895static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos) 896{ 897 u8 cap; 898 int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE : 899 PCI_STD_HEADER_SIZEOF; 900 cap = vdev->pci_config_map[pos]; 901 902 if (cap == PCI_CAP_ID_BASIC) 903 return 0; 904 905 /* XXX Can we have to abutting capabilities of the same type? */ 906 while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap) 907 pos--; 908 909 return pos; 910} 911 912static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos, 913 int count, struct perm_bits *perm, 914 int offset, __le32 *val) 915{ 916 /* Update max available queue size from msi_qmax */ 917 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) { 918 __le16 *flags; 919 int start; 920 921 start = vfio_find_cap_start(vdev, pos); 922 923 flags = (__le16 *)&vdev->vconfig[start]; 924 925 *flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK); 926 *flags |= cpu_to_le16(vdev->msi_qmax << 1); 927 } 928 929 return vfio_default_config_read(vdev, pos, count, perm, offset, val); 930} 931 932static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos, 933 int count, struct perm_bits *perm, 934 int offset, __le32 val) 935{ 936 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 937 if (count < 0) 938 return count; 939 940 /* Fixup and write configured queue size and enable to hardware */ 941 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) { 942 __le16 *pflags; 943 u16 flags; 944 int start, ret; 945 946 start = vfio_find_cap_start(vdev, pos); 947 948 pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS]; 949 950 flags = le16_to_cpu(*pflags); 951 952 /* MSI is enabled via ioctl */ 953 if (!is_msi(vdev)) 954 flags &= ~PCI_MSI_FLAGS_ENABLE; 955 956 /* Check queue size */ 957 if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) { 958 flags &= ~PCI_MSI_FLAGS_QSIZE; 959 flags |= vdev->msi_qmax << 4; 960 } 961 962 /* Write back to virt and to hardware */ 963 *pflags = cpu_to_le16(flags); 964 ret = pci_user_write_config_word(vdev->pdev, 965 start + PCI_MSI_FLAGS, 966 flags); 967 if (ret) 968 return pcibios_err_to_errno(ret); 969 } 970 971 return count; 972} 973 974/* 975 * MSI determination is per-device, so this routine gets used beyond 976 * initialization time. Don't add __init 977 */ 978static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags) 979{ 980 if (alloc_perm_bits(perm, len)) 981 return -ENOMEM; 982 983 perm->readfn = vfio_msi_config_read; 984 perm->writefn = vfio_msi_config_write; 985 986 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 987 988 /* 989 * The upper byte of the control register is reserved, 990 * just setup the lower byte. 991 */ 992 p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE); 993 p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE); 994 if (flags & PCI_MSI_FLAGS_64BIT) { 995 p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE); 996 p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE); 997 if (flags & PCI_MSI_FLAGS_MASKBIT) { 998 p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE); 999 p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE); 1000 } 1001 } else { 1002 p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE); 1003 if (flags & PCI_MSI_FLAGS_MASKBIT) { 1004 p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE); 1005 p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE); 1006 } 1007 } 1008 return 0; 1009} 1010 1011/* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */ 1012static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos) 1013{ 1014 struct pci_dev *pdev = vdev->pdev; 1015 int len, ret; 1016 u16 flags; 1017 1018 ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags); 1019 if (ret) 1020 return pcibios_err_to_errno(ret); 1021 1022 len = 10; /* Minimum size */ 1023 if (flags & PCI_MSI_FLAGS_64BIT) 1024 len += 4; 1025 if (flags & PCI_MSI_FLAGS_MASKBIT) 1026 len += 10; 1027 1028 if (vdev->msi_perm) 1029 return len; 1030 1031 vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL); 1032 if (!vdev->msi_perm) 1033 return -ENOMEM; 1034 1035 ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags); 1036 if (ret) 1037 return ret; 1038 1039 return len; 1040} 1041 1042/* Determine extended capability length for VC (2 & 9) and MFVC */ 1043static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos) 1044{ 1045 struct pci_dev *pdev = vdev->pdev; 1046 u32 tmp; 1047 int ret, evcc, phases, vc_arb; 1048 int len = PCI_CAP_VC_BASE_SIZEOF; 1049 1050 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp); 1051 if (ret) 1052 return pcibios_err_to_errno(ret); 1053 1054 evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */ 1055 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp); 1056 if (ret) 1057 return pcibios_err_to_errno(ret); 1058 1059 if (tmp & PCI_VC_CAP2_128_PHASE) 1060 phases = 128; 1061 else if (tmp & PCI_VC_CAP2_64_PHASE) 1062 phases = 64; 1063 else if (tmp & PCI_VC_CAP2_32_PHASE) 1064 phases = 32; 1065 else 1066 phases = 0; 1067 1068 vc_arb = phases * 4; 1069 1070 /* 1071 * Port arbitration tables are root & switch only; 1072 * function arbitration tables are function 0 only. 1073 * In either case, we'll never let user write them so 1074 * we don't care how big they are 1075 */ 1076 len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF; 1077 if (vc_arb) { 1078 len = round_up(len, 16); 1079 len += vc_arb / 8; 1080 } 1081 return len; 1082} 1083 1084static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos) 1085{ 1086 struct pci_dev *pdev = vdev->pdev; 1087 u32 dword; 1088 u16 word; 1089 u8 byte; 1090 int ret; 1091 1092 switch (cap) { 1093 case PCI_CAP_ID_MSI: 1094 return vfio_msi_cap_len(vdev, pos); 1095 case PCI_CAP_ID_PCIX: 1096 ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word); 1097 if (ret) 1098 return pcibios_err_to_errno(ret); 1099 1100 if (PCI_X_CMD_VERSION(word)) { 1101 /* Test for extended capabilities */ 1102 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword); 1103 vdev->extended_caps = (dword != 0); 1104 return PCI_CAP_PCIX_SIZEOF_V2; 1105 } else 1106 return PCI_CAP_PCIX_SIZEOF_V0; 1107 case PCI_CAP_ID_VNDR: 1108 /* length follows next field */ 1109 ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte); 1110 if (ret) 1111 return pcibios_err_to_errno(ret); 1112 1113 return byte; 1114 case PCI_CAP_ID_EXP: 1115 /* Test for extended capabilities */ 1116 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword); 1117 vdev->extended_caps = (dword != 0); 1118 1119 /* length based on version */ 1120 if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1) 1121 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1; 1122 else 1123 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2; 1124 case PCI_CAP_ID_HT: 1125 ret = pci_read_config_byte(pdev, pos + 3, &byte); 1126 if (ret) 1127 return pcibios_err_to_errno(ret); 1128 1129 return (byte & HT_3BIT_CAP_MASK) ? 1130 HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG; 1131 case PCI_CAP_ID_SATA: 1132 ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte); 1133 if (ret) 1134 return pcibios_err_to_errno(ret); 1135 1136 byte &= PCI_SATA_REGS_MASK; 1137 if (byte == PCI_SATA_REGS_INLINE) 1138 return PCI_SATA_SIZEOF_LONG; 1139 else 1140 return PCI_SATA_SIZEOF_SHORT; 1141 default: 1142 pr_warn("%s: %s unknown length for pci cap 0x%x@0x%x\n", 1143 dev_name(&pdev->dev), __func__, cap, pos); 1144 } 1145 1146 return 0; 1147} 1148 1149static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos) 1150{ 1151 struct pci_dev *pdev = vdev->pdev; 1152 u8 byte; 1153 u32 dword; 1154 int ret; 1155 1156 switch (ecap) { 1157 case PCI_EXT_CAP_ID_VNDR: 1158 ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword); 1159 if (ret) 1160 return pcibios_err_to_errno(ret); 1161 1162 return dword >> PCI_VSEC_HDR_LEN_SHIFT; 1163 case PCI_EXT_CAP_ID_VC: 1164 case PCI_EXT_CAP_ID_VC9: 1165 case PCI_EXT_CAP_ID_MFVC: 1166 return vfio_vc_cap_len(vdev, epos); 1167 case PCI_EXT_CAP_ID_ACS: 1168 ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte); 1169 if (ret) 1170 return pcibios_err_to_errno(ret); 1171 1172 if (byte & PCI_ACS_EC) { 1173 int bits; 1174 1175 ret = pci_read_config_byte(pdev, 1176 epos + PCI_ACS_EGRESS_BITS, 1177 &byte); 1178 if (ret) 1179 return pcibios_err_to_errno(ret); 1180 1181 bits = byte ? round_up(byte, 32) : 256; 1182 return 8 + (bits / 8); 1183 } 1184 return 8; 1185 1186 case PCI_EXT_CAP_ID_REBAR: 1187 ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte); 1188 if (ret) 1189 return pcibios_err_to_errno(ret); 1190 1191 byte &= PCI_REBAR_CTRL_NBAR_MASK; 1192 byte >>= PCI_REBAR_CTRL_NBAR_SHIFT; 1193 1194 return 4 + (byte * 8); 1195 case PCI_EXT_CAP_ID_DPA: 1196 ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte); 1197 if (ret) 1198 return pcibios_err_to_errno(ret); 1199 1200 byte &= PCI_DPA_CAP_SUBSTATE_MASK; 1201 return PCI_DPA_BASE_SIZEOF + byte + 1; 1202 case PCI_EXT_CAP_ID_TPH: 1203 ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword); 1204 if (ret) 1205 return pcibios_err_to_errno(ret); 1206 1207 if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) { 1208 int sts; 1209 1210 sts = dword & PCI_TPH_CAP_ST_MASK; 1211 sts >>= PCI_TPH_CAP_ST_SHIFT; 1212 return PCI_TPH_BASE_SIZEOF + (sts * 2) + 2; 1213 } 1214 return PCI_TPH_BASE_SIZEOF; 1215 default: 1216 pr_warn("%s: %s unknown length for pci ecap 0x%x@0x%x\n", 1217 dev_name(&pdev->dev), __func__, ecap, epos); 1218 } 1219 1220 return 0; 1221} 1222 1223static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev, 1224 int offset, int size) 1225{ 1226 struct pci_dev *pdev = vdev->pdev; 1227 int ret = 0; 1228 1229 /* 1230 * We try to read physical config space in the largest chunks 1231 * we can, assuming that all of the fields support dword access. 1232 * pci_save_state() makes this same assumption and seems to do ok. 1233 */ 1234 while (size) { 1235 int filled; 1236 1237 if (size >= 4 && !(offset % 4)) { 1238 __le32 *dwordp = (__le32 *)&vdev->vconfig[offset]; 1239 u32 dword; 1240 1241 ret = pci_read_config_dword(pdev, offset, &dword); 1242 if (ret) 1243 return ret; 1244 *dwordp = cpu_to_le32(dword); 1245 filled = 4; 1246 } else if (size >= 2 && !(offset % 2)) { 1247 __le16 *wordp = (__le16 *)&vdev->vconfig[offset]; 1248 u16 word; 1249 1250 ret = pci_read_config_word(pdev, offset, &word); 1251 if (ret) 1252 return ret; 1253 *wordp = cpu_to_le16(word); 1254 filled = 2; 1255 } else { 1256 u8 *byte = &vdev->vconfig[offset]; 1257 ret = pci_read_config_byte(pdev, offset, byte); 1258 if (ret) 1259 return ret; 1260 filled = 1; 1261 } 1262 1263 offset += filled; 1264 size -= filled; 1265 } 1266 1267 return ret; 1268} 1269 1270static int vfio_cap_init(struct vfio_pci_device *vdev) 1271{ 1272 struct pci_dev *pdev = vdev->pdev; 1273 u8 *map = vdev->pci_config_map; 1274 u16 status; 1275 u8 pos, *prev, cap; 1276 int loops, ret, caps = 0; 1277 1278 /* Any capabilities? */ 1279 ret = pci_read_config_word(pdev, PCI_STATUS, &status); 1280 if (ret) 1281 return ret; 1282 1283 if (!(status & PCI_STATUS_CAP_LIST)) 1284 return 0; /* Done */ 1285 1286 ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos); 1287 if (ret) 1288 return ret; 1289 1290 /* Mark the previous position in case we want to skip a capability */ 1291 prev = &vdev->vconfig[PCI_CAPABILITY_LIST]; 1292 1293 /* We can bound our loop, capabilities are dword aligned */ 1294 loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF; 1295 while (pos && loops--) { 1296 u8 next; 1297 int i, len = 0; 1298 1299 ret = pci_read_config_byte(pdev, pos, &cap); 1300 if (ret) 1301 return ret; 1302 1303 ret = pci_read_config_byte(pdev, 1304 pos + PCI_CAP_LIST_NEXT, &next); 1305 if (ret) 1306 return ret; 1307 1308 if (cap <= PCI_CAP_ID_MAX) { 1309 len = pci_cap_length[cap]; 1310 if (len == 0xFF) { /* Variable length */ 1311 len = vfio_cap_len(vdev, cap, pos); 1312 if (len < 0) 1313 return len; 1314 } 1315 } 1316 1317 if (!len) { 1318 pr_info("%s: %s hiding cap 0x%x\n", 1319 __func__, dev_name(&pdev->dev), cap); 1320 *prev = next; 1321 pos = next; 1322 continue; 1323 } 1324 1325 /* Sanity check, do we overlap other capabilities? */ 1326 for (i = 0; i < len; i++) { 1327 if (likely(map[pos + i] == PCI_CAP_ID_INVALID)) 1328 continue; 1329 1330 pr_warn("%s: %s pci config conflict @0x%x, was cap 0x%x now cap 0x%x\n", 1331 __func__, dev_name(&pdev->dev), 1332 pos + i, map[pos + i], cap); 1333 } 1334 1335 memset(map + pos, cap, len); 1336 ret = vfio_fill_vconfig_bytes(vdev, pos, len); 1337 if (ret) 1338 return ret; 1339 1340 prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT]; 1341 pos = next; 1342 caps++; 1343 } 1344 1345 /* If we didn't fill any capabilities, clear the status flag */ 1346 if (!caps) { 1347 __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS]; 1348 *vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST); 1349 } 1350 1351 return 0; 1352} 1353 1354static int vfio_ecap_init(struct vfio_pci_device *vdev) 1355{ 1356 struct pci_dev *pdev = vdev->pdev; 1357 u8 *map = vdev->pci_config_map; 1358 u16 epos; 1359 __le32 *prev = NULL; 1360 int loops, ret, ecaps = 0; 1361 1362 if (!vdev->extended_caps) 1363 return 0; 1364 1365 epos = PCI_CFG_SPACE_SIZE; 1366 1367 loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF; 1368 1369 while (loops-- && epos >= PCI_CFG_SPACE_SIZE) { 1370 u32 header; 1371 u16 ecap; 1372 int i, len = 0; 1373 bool hidden = false; 1374 1375 ret = pci_read_config_dword(pdev, epos, &header); 1376 if (ret) 1377 return ret; 1378 1379 ecap = PCI_EXT_CAP_ID(header); 1380 1381 if (ecap <= PCI_EXT_CAP_ID_MAX) { 1382 len = pci_ext_cap_length[ecap]; 1383 if (len == 0xFF) { 1384 len = vfio_ext_cap_len(vdev, ecap, epos); 1385 if (len < 0) 1386 return ret; 1387 } 1388 } 1389 1390 if (!len) { 1391 pr_info("%s: %s hiding ecap 0x%x@0x%x\n", 1392 __func__, dev_name(&pdev->dev), ecap, epos); 1393 1394 /* If not the first in the chain, we can skip over it */ 1395 if (prev) { 1396 u32 val = epos = PCI_EXT_CAP_NEXT(header); 1397 *prev &= cpu_to_le32(~(0xffcU << 20)); 1398 *prev |= cpu_to_le32(val << 20); 1399 continue; 1400 } 1401 1402 /* 1403 * Otherwise, fill in a placeholder, the direct 1404 * readfn will virtualize this automatically 1405 */ 1406 len = PCI_CAP_SIZEOF; 1407 hidden = true; 1408 } 1409 1410 for (i = 0; i < len; i++) { 1411 if (likely(map[epos + i] == PCI_CAP_ID_INVALID)) 1412 continue; 1413 1414 pr_warn("%s: %s pci config conflict @0x%x, was ecap 0x%x now ecap 0x%x\n", 1415 __func__, dev_name(&pdev->dev), 1416 epos + i, map[epos + i], ecap); 1417 } 1418 1419 /* 1420 * Even though ecap is 2 bytes, we're currently a long way 1421 * from exceeding 1 byte capabilities. If we ever make it 1422 * up to 0xFF we'll need to up this to a two-byte, byte map. 1423 */ 1424 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID); 1425 1426 memset(map + epos, ecap, len); 1427 ret = vfio_fill_vconfig_bytes(vdev, epos, len); 1428 if (ret) 1429 return ret; 1430 1431 /* 1432 * If we're just using this capability to anchor the list, 1433 * hide the real ID. Only count real ecaps. XXX PCI spec 1434 * indicates to use cap id = 0, version = 0, next = 0 if 1435 * ecaps are absent, hope users check all the way to next. 1436 */ 1437 if (hidden) 1438 *(__le32 *)&vdev->vconfig[epos] &= 1439 cpu_to_le32((0xffcU << 20)); 1440 else 1441 ecaps++; 1442 1443 prev = (__le32 *)&vdev->vconfig[epos]; 1444 epos = PCI_EXT_CAP_NEXT(header); 1445 } 1446 1447 if (!ecaps) 1448 *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0; 1449 1450 return 0; 1451} 1452 1453/* 1454 * For each device we allocate a pci_config_map that indicates the 1455 * capability occupying each dword and thus the struct perm_bits we 1456 * use for read and write. We also allocate a virtualized config 1457 * space which tracks reads and writes to bits that we emulate for 1458 * the user. Initial values filled from device. 1459 * 1460 * Using shared stuct perm_bits between all vfio-pci devices saves 1461 * us from allocating cfg_size buffers for virt and write for every 1462 * device. We could remove vconfig and allocate individual buffers 1463 * for each area requring emulated bits, but the array of pointers 1464 * would be comparable in size (at least for standard config space). 1465 */ 1466int vfio_config_init(struct vfio_pci_device *vdev) 1467{ 1468 struct pci_dev *pdev = vdev->pdev; 1469 u8 *map, *vconfig; 1470 int ret; 1471 1472 /* 1473 * Config space, caps and ecaps are all dword aligned, so we could 1474 * use one byte per dword to record the type. However, there are 1475 * no requiremenst on the length of a capability, so the gap between 1476 * capabilities needs byte granularity. 1477 */ 1478 map = kmalloc(pdev->cfg_size, GFP_KERNEL); 1479 if (!map) 1480 return -ENOMEM; 1481 1482 vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL); 1483 if (!vconfig) { 1484 kfree(map); 1485 return -ENOMEM; 1486 } 1487 1488 vdev->pci_config_map = map; 1489 vdev->vconfig = vconfig; 1490 1491 memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF); 1492 memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID, 1493 pdev->cfg_size - PCI_STD_HEADER_SIZEOF); 1494 1495 ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF); 1496 if (ret) 1497 goto out; 1498 1499 vdev->bardirty = true; 1500 1501 /* 1502 * XXX can we just pci_load_saved_state/pci_restore_state? 1503 * may need to rebuild vconfig after that 1504 */ 1505 1506 /* For restore after reset */ 1507 vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]); 1508 vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]); 1509 vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]); 1510 vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]); 1511 vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]); 1512 vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]); 1513 vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]); 1514 1515 if (pdev->is_virtfn) { 1516 *(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor); 1517 *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device); 1518 } 1519 1520 if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX)) 1521 vconfig[PCI_INTERRUPT_PIN] = 0; 1522 1523 ret = vfio_cap_init(vdev); 1524 if (ret) 1525 goto out; 1526 1527 ret = vfio_ecap_init(vdev); 1528 if (ret) 1529 goto out; 1530 1531 return 0; 1532 1533out: 1534 kfree(map); 1535 vdev->pci_config_map = NULL; 1536 kfree(vconfig); 1537 vdev->vconfig = NULL; 1538 return pcibios_err_to_errno(ret); 1539} 1540 1541void vfio_config_free(struct vfio_pci_device *vdev) 1542{ 1543 kfree(vdev->vconfig); 1544 vdev->vconfig = NULL; 1545 kfree(vdev->pci_config_map); 1546 vdev->pci_config_map = NULL; 1547 kfree(vdev->msi_perm); 1548 vdev->msi_perm = NULL; 1549} 1550 1551/* 1552 * Find the remaining number of bytes in a dword that match the given 1553 * position. Stop at either the end of the capability or the dword boundary. 1554 */ 1555static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_device *vdev, 1556 loff_t pos) 1557{ 1558 u8 cap = vdev->pci_config_map[pos]; 1559 size_t i; 1560 1561 for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++) 1562 /* nop */; 1563 1564 return i; 1565} 1566 1567static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf, 1568 size_t count, loff_t *ppos, bool iswrite) 1569{ 1570 struct pci_dev *pdev = vdev->pdev; 1571 struct perm_bits *perm; 1572 __le32 val = 0; 1573 int cap_start = 0, offset; 1574 u8 cap_id; 1575 ssize_t ret; 1576 1577 if (*ppos < 0 || *ppos >= pdev->cfg_size || 1578 *ppos + count > pdev->cfg_size) 1579 return -EFAULT; 1580 1581 /* 1582 * Chop accesses into aligned chunks containing no more than a 1583 * single capability. Caller increments to the next chunk. 1584 */ 1585 count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos)); 1586 if (count >= 4 && !(*ppos % 4)) 1587 count = 4; 1588 else if (count >= 2 && !(*ppos % 2)) 1589 count = 2; 1590 else 1591 count = 1; 1592 1593 ret = count; 1594 1595 cap_id = vdev->pci_config_map[*ppos]; 1596 1597 if (cap_id == PCI_CAP_ID_INVALID) { 1598 perm = &unassigned_perms; 1599 cap_start = *ppos; 1600 } else { 1601 if (*ppos >= PCI_CFG_SPACE_SIZE) { 1602 WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX); 1603 1604 perm = &ecap_perms[cap_id]; 1605 cap_start = vfio_find_cap_start(vdev, *ppos); 1606 } else { 1607 WARN_ON(cap_id > PCI_CAP_ID_MAX); 1608 1609 perm = &cap_perms[cap_id]; 1610 1611 if (cap_id == PCI_CAP_ID_MSI) 1612 perm = vdev->msi_perm; 1613 1614 if (cap_id > PCI_CAP_ID_BASIC) 1615 cap_start = vfio_find_cap_start(vdev, *ppos); 1616 } 1617 } 1618 1619 WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC); 1620 WARN_ON(cap_start > *ppos); 1621 1622 offset = *ppos - cap_start; 1623 1624 if (iswrite) { 1625 if (!perm->writefn) 1626 return ret; 1627 1628 if (copy_from_user(&val, buf, count)) 1629 return -EFAULT; 1630 1631 ret = perm->writefn(vdev, *ppos, count, perm, offset, val); 1632 } else { 1633 if (perm->readfn) { 1634 ret = perm->readfn(vdev, *ppos, count, 1635 perm, offset, &val); 1636 if (ret < 0) 1637 return ret; 1638 } 1639 1640 if (copy_to_user(buf, &val, count)) 1641 return -EFAULT; 1642 } 1643 1644 return ret; 1645} 1646 1647ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf, 1648 size_t count, loff_t *ppos, bool iswrite) 1649{ 1650 size_t done = 0; 1651 int ret = 0; 1652 loff_t pos = *ppos; 1653 1654 pos &= VFIO_PCI_OFFSET_MASK; 1655 1656 while (count) { 1657 ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite); 1658 if (ret < 0) 1659 return ret; 1660 1661 count -= ret; 1662 done += ret; 1663 buf += ret; 1664 pos += ret; 1665 } 1666 1667 *ppos += done; 1668 1669 return done; 1670} 1671