/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
H A D | gfx_v7_0.c | 2388 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); gfx_v7_0_ring_test_ring() 2438 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); gfx_v7_0_ring_emit_hdp_flush() 2466 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); gfx_v7_0_ring_emit_fence_gfx() 2478 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); gfx_v7_0_ring_emit_fence_gfx() 2507 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); gfx_v7_0_ring_emit_fence_compute() 2536 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); gfx_v7_0_ring_emit_semaphore() 2542 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); gfx_v7_0_ring_emit_semaphore() 2579 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); gfx_v7_0_ring_emit_ib_gfx() 2587 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); gfx_v7_0_ring_emit_ib_gfx() 2592 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); gfx_v7_0_ring_emit_ib_gfx() 2594 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); gfx_v7_0_ring_emit_ib_gfx() 2617 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); gfx_v7_0_ring_emit_ib_compute() 2623 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); gfx_v7_0_ring_emit_ib_compute() 2669 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); gfx_v7_0_ring_test_ib() 2852 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); gfx_v7_0_cp_gfx_start() 2858 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); gfx_v7_0_cp_gfx_start() 2861 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); gfx_v7_0_cp_gfx_start() 2869 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); gfx_v7_0_cp_gfx_start() 2877 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); gfx_v7_0_cp_gfx_start() 2903 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); gfx_v7_0_cp_gfx_start() 2906 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); gfx_v7_0_cp_gfx_start() 2909 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); gfx_v7_0_cp_gfx_start() 3634 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); gfx_v7_0_ring_emit_vm_flush() 3646 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); gfx_v7_0_ring_emit_vm_flush() 3648 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); gfx_v7_0_ring_emit_vm_flush() 3652 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); gfx_v7_0_ring_emit_vm_flush() 3666 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); gfx_v7_0_ring_emit_vm_flush() 3674 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); gfx_v7_0_ring_emit_vm_flush() 3687 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); gfx_v7_0_ring_emit_vm_flush() 3691 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); gfx_v7_0_ring_emit_vm_flush() 3693 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); gfx_v7_0_ring_emit_vm_flush() 4583 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); gfx_v7_0_get_csb_buffer() 4586 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); gfx_v7_0_get_csb_buffer() 4594 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); gfx_v7_0_get_csb_buffer() 4604 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); gfx_v7_0_get_csb_buffer() 4630 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); gfx_v7_0_get_csb_buffer() 4633 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); gfx_v7_0_get_csb_buffer() 4709 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); gfx_v7_0_ring_emit_gds_switch() 4717 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); gfx_v7_0_ring_emit_gds_switch() 4725 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); gfx_v7_0_ring_emit_gds_switch() 4733 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); gfx_v7_0_ring_emit_gds_switch() 4801 PACKET3(PACKET3_NOP, 0x3FFF), 0xf, gfx_v7_0_sw_init() 4828 PACKET3(PACKET3_NOP, 0x3FFF), 0xf, gfx_v7_0_sw_init()
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H A D | gfx_v8_0.c | 641 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); gfx_v8_0_ring_test_ring() 686 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); gfx_v8_0_ring_test_ib() 1242 PACKET3(PACKET3_NOP, 0x3FFF), 0xf, gfx_v8_0_sw_init() 1269 PACKET3(PACKET3_NOP, 0x3FFF), 0xf, gfx_v8_0_sw_init() 3234 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); gfx_v8_0_cp_gfx_start() 3237 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); gfx_v8_0_cp_gfx_start() 3245 PACKET3(PACKET3_SET_CONTEXT_REG, gfx_v8_0_cp_gfx_start() 3255 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); gfx_v8_0_cp_gfx_start() 3279 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); gfx_v8_0_cp_gfx_start() 3282 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); gfx_v8_0_cp_gfx_start() 3286 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); gfx_v8_0_cp_gfx_start() 4416 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); gfx_v8_0_ring_emit_gds_switch() 4424 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); gfx_v8_0_ring_emit_gds_switch() 4432 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); gfx_v8_0_ring_emit_gds_switch() 4440 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); gfx_v8_0_ring_emit_gds_switch() 4531 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); gfx_v8_0_ring_emit_hdp_flush() 4557 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); gfx_v8_0_ring_emit_ib_gfx() 4565 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); gfx_v8_0_ring_emit_ib_gfx() 4570 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); gfx_v8_0_ring_emit_ib_gfx() 4572 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); gfx_v8_0_ring_emit_ib_gfx() 4596 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); gfx_v8_0_ring_emit_ib_compute() 4602 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); gfx_v8_0_ring_emit_ib_compute() 4624 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); gfx_v8_0_ring_emit_fence_gfx() 4660 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2)); gfx_v8_0_ring_emit_semaphore() 4668 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); gfx_v8_0_ring_emit_semaphore() 4682 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); gfx_v8_0_ring_emit_vm_flush() 4694 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); gfx_v8_0_ring_emit_vm_flush() 4696 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); gfx_v8_0_ring_emit_vm_flush() 4700 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); gfx_v8_0_ring_emit_vm_flush() 4716 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); gfx_v8_0_ring_emit_vm_flush() 4724 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); gfx_v8_0_ring_emit_vm_flush() 4737 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); gfx_v8_0_ring_emit_vm_flush() 4739 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); gfx_v8_0_ring_emit_vm_flush() 4741 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); gfx_v8_0_ring_emit_vm_flush() 4773 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); gfx_v8_0_ring_emit_fence_compute()
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H A D | vid.h | 106 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 110 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | cikd.h | 220 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 224 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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/linux-4.4.14/drivers/gpu/drm/radeon/ |
H A D | ni.c | 1417 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); cayman_fence_ring_emit() 1423 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); cayman_fence_ring_emit() 1439 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); cayman_ring_ib_execute() 1444 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); cayman_ring_ib_execute() 1450 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); cayman_ring_ib_execute() 1460 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); cayman_ring_ib_execute() 1566 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); cayman_cp_start() 1584 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); cayman_cp_start() 1590 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); cayman_cp_start() 1594 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); cayman_cp_start() 2618 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); cayman_vm_flush() 2628 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); cayman_vm_flush()
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H A D | r300d.h | 45 /* PACKET3 op code */ 64 #define PACKET3(op, n) (CP_PACKET3 | \ macro
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H A D | si.c | 3378 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); si_fence_ring_emit() 3381 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); si_fence_ring_emit() 3390 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); si_fence_ring_emit() 3409 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); si_ring_ib_execute() 3412 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); si_ring_ib_execute() 3417 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); si_ring_ib_execute() 3423 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); si_ring_ib_execute() 3430 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); si_ring_ib_execute() 3444 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); si_ring_ib_execute() 3447 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); si_ring_ib_execute() 3569 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); si_cp_start() 3578 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); si_cp_start() 3593 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); si_cp_start() 3599 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); si_cp_start() 3603 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); si_cp_start() 3606 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); si_cp_start() 5067 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); si_vm_flush() 5082 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); si_vm_flush() 5090 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); si_vm_flush() 5098 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); si_vm_flush() 5108 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); si_vm_flush() 5713 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); si_get_csb_buffer() 5716 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); si_get_csb_buffer() 5724 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); si_get_csb_buffer() 5734 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); si_get_csb_buffer() 5755 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); si_get_csb_buffer() 5758 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); si_get_csb_buffer()
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H A D | cik.c | 3886 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); cik_ring_test() 3942 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); cik_hdp_flush_cp_ring_emit() 3971 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); cik_fence_gfx_ring_emit() 3983 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); cik_fence_gfx_ring_emit() 4010 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); cik_fence_compute_ring_emit() 4041 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); cik_semaphore_ring_emit() 4047 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); cik_semaphore_ring_emit() 4102 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); cik_copy_cpdma() 4149 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); cik_ring_ib_execute() 4152 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); cik_ring_ib_execute() 4157 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); cik_ring_ib_execute() 4163 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); cik_ring_ib_execute() 4170 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); cik_ring_ib_execute() 4211 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); cik_ib_test() 4405 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); cik_cp_gfx_start() 4411 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); cik_cp_gfx_start() 4414 radeon_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); cik_cp_gfx_start() 4421 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); cik_cp_gfx_start() 4425 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); cik_cp_gfx_start() 4428 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); cik_cp_gfx_start() 6115 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); cik_vm_flush() 6129 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); cik_vm_flush() 6136 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); cik_vm_flush() 6147 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); cik_vm_flush() 6158 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); cik_vm_flush() 6166 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); cik_vm_flush() 6179 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); cik_vm_flush() 7155 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); cik_get_csb_buffer() 7158 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); cik_get_csb_buffer() 7166 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); cik_get_csb_buffer() 7176 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); cik_get_csb_buffer() 7202 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); cik_get_csb_buffer() 7205 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); cik_get_csb_buffer() 8640 nop = PACKET3(PACKET3_NOP, 0x3FFF); cik_startup() 8644 nop = PACKET3(PACKET3_NOP, 0x3FFF); cik_startup()
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H A D | r600.c | 2694 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); r600_cp_start() 2839 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); r600_ring_test() 2877 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); r600_fence_ring_emit() 2883 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); r600_fence_ring_emit() 2891 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); r600_fence_ring_emit() 2896 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); r600_fence_ring_emit() 2899 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); r600_fence_ring_emit() 2903 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); r600_fence_ring_emit() 2934 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); r600_semaphore_ring_emit() 2941 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); r600_semaphore_ring_emit() 2988 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); r600_copy_cpdma() 2999 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); r600_copy_cpdma() 3008 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); r600_copy_cpdma() 3333 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); r600_ring_ib_execute() 3339 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); r600_ring_ib_execute() 3346 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); r600_ring_ib_execute() 3375 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); r600_ib_test()
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H A D | rv515d.h | 188 /* PACKET3 op code */ 204 #define PACKET3(op, n) (CP_PACKET3 | \ macro
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H A D | r200.c | 172 /* FIXME: only allow PACKET3 blit? easier to check for out of r200_packet0_check()
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H A D | evergreen.c | 3025 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); evergreen_ring_ib_execute() 3030 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); evergreen_ring_ib_execute() 3036 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); evergreen_ring_ib_execute() 3043 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); evergreen_ring_ib_execute() 3097 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); evergreen_cp_start() 3116 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); evergreen_cp_start() 3122 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); evergreen_cp_start() 3126 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); evergreen_cp_start()
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H A D | r100d.h | 45 /* PACKET3 op code */ 63 #define PACKET3(op, n) (CP_PACKET3 | \ macro
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H A D | rv770d.h | 987 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
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H A D | sid.h | 1593 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro 1597 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | cikd.h | 1693 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 1697 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | nid.h | 1156 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
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H A D | r100.c | 921 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); r100_copy_blit() 1579 /* FIXME: only allow PACKET3 blit? easier to check for out of r100_packet0_check() 1902 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " r100_cs_track_check_pkt3_indx_buffer()
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H A D | evergreend.h | 1542 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
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H A D | r600_cs.c | 811 * PACKET3 - WAIT_REG_MEM poll vline status reg
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H A D | r600d.h | 1586 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
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