Searched refs:MXR_CFG (Results 1 - 4 of 4) sorted by relevance
/linux-4.4.14/drivers/media/platform/s5p-tv/ |
H A D | regs-mixer.h | 18 #define MXR_CFG 0x0004 macro 67 /* bits for MXR_CFG */
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H A D | mixer_reg.c | 93 mxr_write(mdev, MXR_CFG, MXR_CFG_OUT_RGB888); mxr_reg_reset() 223 mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP0_ENABLE); mxr_reg_graph_buffer() 225 mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP1_ENABLE); mxr_reg_graph_buffer() 241 mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_VP_ENABLE); mxr_reg_vp_buffer() 300 if (~mxr_read(mdev, MXR_CFG) & MXR_CFG_SCAN_PROGRASSIVE) mxr_irq_handler() 328 mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_DST_MASK); mxr_reg_s_output() 406 mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_SCAN_MASK | mxr_reg_set_mbus_fmt() 487 DUMPREG(MXR_CFG); mxr_reg_mxr_dump()
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/linux-4.4.14/drivers/gpu/drm/exynos/ |
H A D | regs-mixer.h | 21 #define MXR_CFG 0x0004 macro 84 /* bits for MXR_CFG */
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H A D | exynos_mixer.c | 192 DUMPREG(MXR_CFG); mixer_regs_dump() 308 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK); mixer_cfg_scan() 349 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK); mixer_cfg_rgb_fmt() 360 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE); mixer_cfg_layer() 363 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE); mixer_cfg_layer() 368 mixer_reg_writemask(res, MXR_CFG, val, mixer_cfg_layer() 505 mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE); mixer_layer_update() 668 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK); mixer_win_reset() 671 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK); mixer_win_reset() 718 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE); mixer_win_reset() 719 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE); mixer_win_reset() 721 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE); mixer_win_reset()
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