Lines Matching refs:MXR_CFG
192 DUMPREG(MXR_CFG); in mixer_regs_dump()
308 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK); in mixer_cfg_scan()
349 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK); in mixer_cfg_rgb_fmt()
360 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE); in mixer_cfg_layer()
363 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE); in mixer_cfg_layer()
368 mixer_reg_writemask(res, MXR_CFG, val, in mixer_cfg_layer()
505 mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE); in mixer_layer_update()
668 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK); in mixer_win_reset()
671 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK); in mixer_win_reset()
718 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE); in mixer_win_reset()
719 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE); in mixer_win_reset()
721 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE); in mixer_win_reset()