Searched refs:IS_SKYLAKE (Results 1 – 18 of 18) sorted by relevance
194 if (IS_SKYLAKE(dev) && (dev->pdev->revision < in intel_get_stepping()206 if (IS_SKYLAKE(dev) && (dev->pdev->revision < in intel_get_substepping()432 if (IS_SKYLAKE(dev)) in intel_csr_ucode_init()
466 } else if (IS_SKYLAKE(dev)) { in intel_virt_detect_pch()529 WARN_ON(!IS_SKYLAKE(dev)); in intel_detect_pch()533 WARN_ON(!IS_SKYLAKE(dev)); in intel_detect_pch()844 else if (IS_SKYLAKE(dev_priv)) in i915_drm_resume_early()1578 else if (IS_SKYLAKE(dev)) in intel_runtime_resume()1622 else if (IS_SKYLAKE(dev_priv)) in intel_suspend_complete()
325 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || in guc_ucode_xfer()560 } else if (IS_SKYLAKE(dev)) { in intel_guc_ucode_init()
53 #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)468 WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n"); in assert_can_enable_dc5()531 WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n"); in assert_can_enable_dc6()661 if (IS_SKYLAKE(dev) && in skl_set_power_well()1823 if (IS_SKYLAKE(dev_priv)) { in sanitize_disable_power_well_option()1862 } else if (IS_SKYLAKE(dev_priv->dev)) { in intel_power_domains_init()
146 if (IS_SKYLAKE(dev)) { in get_mocs_settings()
77 else if (IS_SKYLAKE(dev_priv)) in get_gmbus_pin()92 else if (IS_SKYLAKE(dev_priv)) in intel_gmbus_is_valid_pin()
451 } else if (IS_SKYLAKE(dev)) { in intel_prepare_ddi_buffers()1195 else if (IS_SKYLAKE(dev)) in intel_ddi_clock_get()1792 if (IS_SKYLAKE(dev)) in intel_ddi_pll_select()2275 if (IS_SKYLAKE(dev)) in ddi_signal_levels()2298 if (IS_SKYLAKE(dev)) { in intel_ddi_pre_enable()2393 if (IS_SKYLAKE(dev)) in intel_ddi_post_disable()3004 if (IS_SKYLAKE(dev)) in intel_ddi_pll_init()3011 if (IS_SKYLAKE(dev)) { in intel_ddi_pll_init()
929 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 || in gen9_init_workarounds()937 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || in gen9_init_workarounds()949 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) || in gen9_init_workarounds()966 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) || in gen9_init_workarounds()973 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) || in gen9_init_workarounds()979 if (IS_SKYLAKE(dev) || in gen9_init_workarounds()1062 if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) { in skl_init_workarounds()1150 if (IS_SKYLAKE(dev)) in init_workarounds_ring()
594 if (!IS_SKYLAKE(dev_priv)) in i915_audio_component_codec_wake_override()646 if (!IS_SKYLAKE(dev_priv) && in i915_audio_component_sync_audio_rate()
287 return ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || in disable_lite_restore_wa()1152 if (IS_SKYLAKE(ring->dev) && INTEL_REVID(ring->dev) <= SKL_REVID_E0) in gen8_emit_flush_coherentl3_wa()1317 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) || in gen9_init_indirectctx_bb()1343 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) || in gen9_init_perctx_bb()1353 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) || in gen9_init_perctx_bb()
2473 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) macro2502 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \2504 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \2590 IS_SKYLAKE(dev))2593 IS_SKYLAKE(dev))
436 if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) in i915_gem_init_stolen()
1255 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); in i915_frequency_info()1260 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); in i915_frequency_info()1266 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); in i915_frequency_info()1804 if (IS_SKYLAKE(dev)) { in i915_ring_freq_table()1824 (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))), in i915_ring_freq_table()5028 if (IS_SKYLAKE(dev)) in gen9_sseu_device_status()
584 if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) in find_compression_threshold()
4694 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { in gen6_init_rps_frequencies()4706 if (IS_SKYLAKE(dev)) { in gen6_init_rps_frequencies()4787 if (IS_SKYLAKE(dev)) in gen9_enable_rc6()4811 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) || in gen9_enable_rc6()5060 if (IS_SKYLAKE(dev)) { in __gen6_update_ring_freq()5078 if (IS_SKYLAKE(dev)) { in __gen6_update_ring_freq()6206 if (IS_SKYLAKE(dev)) in intel_gen6_powersave_work()
669 info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1)); in gen9_sseu_info_init()
1023 if (IS_SKYLAKE(dev) && port == PORT_E) { in intel_dp_aux_init()1192 if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) in intel_dp_source_supports_hbr2()1210 } else if (IS_SKYLAKE(dev)) { in intel_dp_source_rates()1530 if (IS_SKYLAKE(dev) && is_edp(intel_dp)) in intel_dp_compute_config()
5398 if (IS_SKYLAKE(dev)) { in intel_update_max_cdclk()9816 if (IS_SKYLAKE(dev)) in haswell_get_ddi_port_state()12077 } else if (IS_SKYLAKE(dev)) { in intel_dump_pipe_config()14101 if (found || IS_SKYLAKE(dev)) in intel_setup_outputs()14117 if (IS_SKYLAKE(dev) && in intel_setup_outputs()14563 if (IS_SKYLAKE(dev)) in intel_init_display()