Searched refs:DSPCLK_GATE_D (Results 1 – 7 of 7) sorted by relevance
493 tmp = I915_READ(DSPCLK_GATE_D); in intel_dsi_pre_enable()495 I915_WRITE(DSPCLK_GATE_D, tmp); in intel_dsi_pre_enable()638 val = I915_READ(DSPCLK_GATE_D); in intel_dsi_post_disable()640 I915_WRITE(DSPCLK_GATE_D, val); in intel_dsi_post_disable()
129 val = I915_READ(DSPCLK_GATE_D); in intel_i2c_quirk_set()134 I915_WRITE(DSPCLK_GATE_D, val); in intel_i2c_quirk_set()
6799 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); in vlv_init_display_clock_gating()6938 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); in g4x_init_clock_gating()6956 I915_WRITE(DSPCLK_GATE_D, 0); in crestline_init_clock_gating()7026 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); in i830_init_clock_gating()
2372 #define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200) macro
274 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D); in cdv_save_display_registers()327 REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D); in cdv_restore_display_registers()
1311 #define DSPCLK_GATE_D 0x6200 macro
1981 reg_value = REG_READ(DSPCLK_GATE_D); in cdv_disable_intel_clock_gating()1990 REG_WRITE(DSPCLK_GATE_D, reg_value); in cdv_disable_intel_clock_gating()