Searched refs:B2 (Results 1 - 118 of 118) sorted by relevance

/linux-4.4.14/arch/c6x/kernel/
H A Dhead.S45 MVC .S2 CSR,B2
46 CLR .S2 B2,0,1,B2
47 MVC .S2 B2,CSR
48 MVC .S2 TSR,B2
49 CLR .S2 B2,0,1,B2
50 MVC .S2 B2,TSR
51 MVC .S2 ITSR,B2
52 CLR .S2 B2,0,1,B2
53 MVC .S2 B2,ITSR
54 MVC .S2 NTSR,B2
55 CLR .S2 B2,0,1,B2
56 MVC .S2 B2,NTSR
H A Dentry.S89 STDW .D2T2 B3:B2,*SP--[1]
155 || LDDW .D2T2 *++SP[1],B3:B2
268 MASK_INT B2
281 UNMASK_INT B2
294 MASK_INT B2
310 MASK_INT B2
327 MVK .L2 1,B2
328 STW .D2T2 B2,*+SP(REGS__END+8) ; set syscall flag
329 MVC .S2 B2,ECR ; ack the software exception
331 UNMASK_INT B2 ; re-enable global IT
374 MASK_INT B2
520 MVC .S2 EFR,B2
521 CMPEQ .L2 1,B2,B2
526 [!B2] MVKL .S1 process_exception,A0
527 [!B2] MVKH .S1 process_exception,A0
528 [!B2] B .S2X A0
530 [!B2] B .S2 process_exception
532 [B2] B .S2 system_call_saved
533 [!B2] ADDAW .D2 SP,2,B1
534 [!B2] MV .D1X B1,A4
H A Dtraps.c39 pr_err("A2: %08lx B2: %08lx\n", regs->a2, regs->b2); show_regs()
/linux-4.4.14/arch/c6x/lib/
H A Dremi.S22 ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
23 ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
24 ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
25 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
30 ;; divu does not clobber B2 either, which is taken advantage of
34 ;; remi uses B2 and A5 to hold the input values during the
42 || cmpgt .l2 0, B4, B2
47 || [B2] neg .l2 B4, B4
48 || xor .s2x B2, A1, B0
49 || mv .d2 B4, B2
59 mpy32 .m1x A4, B2, A6
H A Ddivremi.S24 || cmpgt .l2 0, B4, B2
29 || [B2] neg .l2 B4, B4
30 || xor .s2x B2, A1, B0
31 || mv .d2 B4, B2
41 mpy32 .m1x A4, B2, A6
H A Ddivi.S22 ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
23 ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
24 ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
25 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
30 ;; divu does not clobber B2 either, which is taken advantage of
34 ;; remi uses B2 and A5 to hold the input values during the
H A Dremu.S22 ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
23 ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
24 ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
25 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
30 ;; divu does not clobber B2 either, which is taken advantage of
34 ;; remi uses B2 and A5 to hold the input values during the
H A Ddivu.S22 ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
23 ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
24 ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
25 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
30 ;; divu does not clobber B2 either, which is taken advantage of
34 ;; remi uses B2 and A5 to hold the input values during the
H A Dstrasgi.S28 || mvk .s2 20, B2
36 || cmpltu .l2 B2, B7, B0
71 || cmpltu .l2 B2, B7, B0
H A Dcsum_64plus.S40 || MVK .D2 1,B2
53 || MPYU .M2 B7,B2,B8
/linux-4.4.14/arch/blackfin/kernel/cplb-mpu/
H A DMakefile10 -ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3
/linux-4.4.14/arch/blackfin/kernel/cplb-nompu/
H A DMakefile10 -ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3
/linux-4.4.14/drivers/media/usb/dvb-usb/
H A Ddigitv.h20 * <cmdbyte> VV <len> B0 B1 B2 B3
/linux-4.4.14/arch/arm/mach-pxa/include/mach/
H A Dhardware.h68 * PXA210 B2 0x69052924 0x4926C013
75 * PXA250 B2 0x69052904 0x49264013
96 * PXA32x B2 0x69056826 0x6E642013
100 * PXA930 B2 0x69056838 0x8E643013
/linux-4.4.14/arch/m68k/fpsp040/
H A Dssin.S42 | 1 + r*r*(B1+s*(B2+ ... + s*B8)), s = r*r.
288 |--SGN + S'*(B1 + S(B2 + S(B3 + S(B4 + ... + SB8)))), WHERE
290 |--SGN + S'*([B1+T(B3+T(B5+TB7))] + [S(B2+T(B4+T(B6+TB8)))])
293 |--WHILE B2 AND B3 ARE IN DOUBLE-EXTENDED FORMAT, B1 IS -1/2
331 faddx COSB2,%fp2 | ...B2+T(B4+T(B6+TB8))
334 fmulx %fp2,%fp0 | ...S(B2+T(B4+T(B6+TB8)))
638 faddx COSB2,%fp2 | ...B2+S(B3+...)
641 fmulx %fp2,%fp0 | ...S(B2+...)
646 fadds COSB1,%fp0 | ...B1+S(B2...)
647 fmulx SPRIME(%a6),%fp0 | ...S'(B1+S(B2+...))
705 faddx COSB2,%fp1 | ...B2+S(B3+...)
708 fmulx %fp0,%fp1 | ...S(B2+...)
713 fadds COSB1,%fp1 | ...B1+S(B2...)
715 fmulx SPRIME(%a6),%fp1 | ...S'(B1+S(B2+...))
H A Dsatan.S349 |--ATAN(X) BY X + X*Y*(B1+Y*(B2+Y*(B3+Y*(B4+Y*(B5+Y*B6)))))
350 |--WHICH IS X + X*Y*( [B1+Z*(B3+Z*B5)] + [Y*(B2+Z*(B4+Z*B6)] )
376 faddd ATANB2,%fp2 | ...B2+Z*(B4+Z*B6)
379 fmulx %fp0,%fp2 | ...Y*(B2+Z*(B4+Z*B6))
382 faddx %fp2,%fp1 | ...[B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))]
385 fmulx %fp1,%fp0 | ...X*Y*([B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))])
444 | ... +[Y*(B2+Z*(B4+Z*B6))])
H A Dslogn.S437 |--U + U*V*(B1 + V*(B2 + V*(B3 + V*(B4 + V*B5)))) BY
438 |--U + U*V*( [B1 + W*(B3 + W*B5)] + [V*(B2 + W*B4)] )
452 faddd LOGB2,%fp2 | ...B2+W*B4
456 fmulx %fp0,%fp2 | ...V*(B2+W*B4)
461 faddx %fp2,%fp1 | ...B1+W*(B3+W*B5) + V*(B2+W*B4), FP2 RELEASED
464 fmulx %fp1,%fp0 | ...U*V*( [B1+W*(B3+W*B5)] + [V*(B2+W*B4)] )
H A Dsetox.S302 | p = X + X*X*(B1 + X*(B2 + ... + X*B12))
306 | B2 is double extended.
313 | Q = X*S*(B2 + X*(B3 + ... + X*B12))
316 | Q = [ X*S*(B2 + S*(B4 + ... + S*B12)) ] +
830 faddx EM1B2,%fp1 | ...fp1 is B2+S*...
833 fmulx %fp0,%fp1 | ...fp1 is S*(B2+...
836 fmulx (%a0),%fp1 | ...fp1 is X*S*(B2...
/linux-4.4.14/drivers/isdn/hisax/
H A Dst5481.h30 #define EP_B2_OUT 0x04U /* B2 channel out */
31 #define EP_B2_IN 0x05U /* B2 channel in */
67 #define IN_B2_COUNTER 0x3a /* B2 receive channel fifo counter */
68 #define OUT_B2_COUNTER 0x3b /* B2 transmit channel fifo counter */
77 #define FFCTRL_IN_B2 0x44 /* B2 receive channel fifo threshold low */
78 #define FFCTRH_IN_B2 0x45 /* B2 receive channel fifo threshold high */
79 #define FFCTRL_OUT_B2 0x46 /* B2 transmit channel fifo threshold low */
80 #define FFCTRH_OUT_B2 0x47 /* B2 transmit channel fifo threshold high */
84 #define FFMSK_B2 0x50 /* B2 fifo interrupt MASK register */
H A Dhfc_sx.c400 /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */ reset_hfcsx()
401 /* STIO2 is used as data input, B1+B2 from IOM->ST */ reset_hfcsx()
407 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */ reset_hfcsx()
409 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */ reset_hfcsx()
577 debugl1(cs, "PH_TEST_LOOP B2"); dch_nt_l2l1()
635 cs->hw.hfcsx.conn |= 0x10; /* B2-IOM -> B2-ST */ hfcsx_auxcmd()
1043 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcsx()
1048 cs->hw.hfcsx.bswapped = 1; /* B1 and B2 exchanged */ mode_hfcsx()
1051 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcsx()
1056 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcsx()
H A Dhfc_pci.c147 /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */ reset_hfcpci()
148 /* STIO2 is used as data input, B1+B2 from IOM->ST */ reset_hfcpci()
154 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */ reset_hfcpci()
156 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */ reset_hfcpci()
751 debugl1(cs, "PH_TEST_LOOP B2"); dch_nt_l2l1()
812 cs->hw.hfcpci.conn |= 0x10; /* B2-IOM -> B2-ST */ hfcpci_auxcmd()
1280 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcpci()
1285 cs->hw.hfcpci.bswapped = 1; /* B1 and B2 exchanged */ mode_hfcpci()
1288 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcpci()
1293 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcpci()
H A Dhfc4s8s_l1.c1150 /* B2 RX Fifo has data to read */ hfc4s8s_bh()
1155 /* B2 TX Fifo has send completed */ hfc4s8s_bh()
H A Dipacx.c173 if ((long)arg & 2) { // loop B2 dch_l2l1()
176 else { // B2 off dch_l2l1()
H A Dhisax_isac.c41 "2085 B2",
H A Dicc.c29 {"2070 A1/A3", "2070 B1", "2070 B2/B3", "2070 V2.4"};
H A Disac.c28 {"2086/2186 V1.1", "2085 B1", "2085 B2",
H A Disdnl1.c826 debugl1(cs, "PH_TEST_LOOP B2"); dch_l2l1()
/linux-4.4.14/arch/mips/sibyte/sb1250/
H A Dsetup.c65 pass_str = "B2"; setup_bcm1250()
227 printk("@@@@ This is a BCM1250 B1/B2. board, and the " sb1250_setup()
234 printk("@@@@ This is a BCM1250 B1/B2, but the kernel is " sb1250_setup()
/linux-4.4.14/arch/x86/include/asm/
H A Dolpc.h56 * order) were created: A1, B1, B2, B3, B4, C1. The A1 through B2 models
/linux-4.4.14/arch/powerpc/include/asm/
H A Dreg_fsl_emb.h45 #define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
78 #define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
/linux-4.4.14/arch/blackfin/mach-bf518/include/mach/
H A DdefBF512.h873 #define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
874 #define B2RDYPOL 0x00000002 /* B2 RDY Active High */
875 #define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
876 #define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
877 #define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
878 #define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
879 #define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
880 #define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
881 #define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
882 #define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
883 #define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
884 #define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
885 #define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
886 #define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
887 #define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
888 #define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
889 #define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
890 #define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
891 #define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
892 #define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
893 #define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
894 #define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
895 #define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
896 #define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
897 #define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
898 #define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
899 #define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
900 #define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
901 #define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
902 #define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
903 #define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
904 #define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
905 #define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
906 #define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
907 #define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
908 #define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
909 #define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
910 #define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
911 #define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
912 #define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
913 #define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
914 #define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
915 #define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
916 #define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
/linux-4.4.14/arch/blackfin/mach-bf527/include/mach/
H A DdefBF522.h874 #define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
875 #define B2RDYPOL 0x00000002 /* B2 RDY Active High */
876 #define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
877 #define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
878 #define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
879 #define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
880 #define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
881 #define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
882 #define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
883 #define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
884 #define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
885 #define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
886 #define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
887 #define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
888 #define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
889 #define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
890 #define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
891 #define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
892 #define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
893 #define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
894 #define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
895 #define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
896 #define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
897 #define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
898 #define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
899 #define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
900 #define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
901 #define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
902 #define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
903 #define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
904 #define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
905 #define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
906 #define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
907 #define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
908 #define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
909 #define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
910 #define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
911 #define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
912 #define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
913 #define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
914 #define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
915 #define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
916 #define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
917 #define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
/linux-4.4.14/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h1196 #define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
1197 #define B2RDYPOL 0x00000002 /* B2 RDY Active High */
1198 #define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
1199 #define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
1200 #define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
1201 #define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
1202 #define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
1203 #define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
1204 #define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
1205 #define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
1206 #define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1207 #define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1208 #define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1209 #define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1210 #define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
1211 #define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
1212 #define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
1213 #define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
1214 #define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
1215 #define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
1216 #define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
1217 #define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
1218 #define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
1219 #define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
1220 #define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
1221 #define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
1222 #define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
1223 #define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
1224 #define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
1225 #define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
1226 #define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
1227 #define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
1228 #define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
1229 #define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
1230 #define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
1231 #define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
1232 #define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
1233 #define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
1234 #define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
1235 #define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
1236 #define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
1237 #define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
1238 #define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
1239 #define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
/linux-4.4.14/include/uapi/linux/
H A Dsonet.h11 __HANDLE_ITEM(line_bip); /* line parity errors (B2) */ \
H A Dcapi.h70 __u32 support2; /* B2 protocols support */
/linux-4.4.14/sound/soc/codecs/
H A Dmax98090.c109 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
110 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
111 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
125 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
126 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
127 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
141 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
142 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
143 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
157 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
158 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
159 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
173 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
174 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
175 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
189 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
190 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
191 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
205 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
206 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
207 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
218 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
221 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
222 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
223 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
H A Dwm8997.c180 SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT,
192 SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT,
204 SOC_SINGLE_TLV("EQ3 B2 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B2_GAIN_SHIFT,
216 SOC_SINGLE_TLV("EQ4 B2 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B2_GAIN_SHIFT,
H A Dwm8998.c281 SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT,
294 SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT,
307 SOC_SINGLE_TLV("EQ3 B2 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B2_GAIN_SHIFT,
320 SOC_SINGLE_TLV("EQ4 B2 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B2_GAIN_SHIFT,
H A Dwm5102.c794 SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT,
806 SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT,
818 SOC_SINGLE_TLV("EQ3 B2 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B2_GAIN_SHIFT,
830 SOC_SINGLE_TLV("EQ4 B2 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B2_GAIN_SHIFT,
H A Dwm5110.c648 SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT,
660 SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT,
672 SOC_SINGLE_TLV("EQ3 B2 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B2_GAIN_SHIFT,
684 SOC_SINGLE_TLV("EQ4 B2 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B2_GAIN_SHIFT,
H A Dwm8996.c556 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
567 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
H A Dmax98088.c234 { 0xb2, 0x00 }, /* B2 DAI2 EQ5 */
/linux-4.4.14/drivers/atm/
H A DuPD98402.h23 #define uPD98402_B2ECT 0x0a /* B2 Error Count Register */
86 #define uPD98402_PFM_B2E 0x08 /* B2 error */
/linux-4.4.14/drivers/usb/serial/
H A Dftdi_sio.h256 * B2..7 Reserved
288 * B2 Xon/Xoff handshaking
516 * B2 Reserved - must be 0
528 * B2 Parity Error (PE)
562 * B2..7 Length of message - (not including Byte 0)
H A Dftdi_sio.c1988 * B2..7 length of message excluding byte 0
/linux-4.4.14/arch/blackfin/include/asm/
H A Ddpmc.h373 B2 = I0;
380 B2.L = lo(IMASK);
403 FP = B2;
515 B2 = I0;
522 B2.L = lo(IPRIO);
631 FP = B2;
/linux-4.4.14/drivers/net/wireless/cw1200/
H A Dcw1200_spi.c52 LE: B0 B1 B2 B3
53 BE: B3 B2 B1 B0
57 B1 B0 B3 B2
/linux-4.4.14/arch/powerpc/platforms/powernv/
H A Dopal-lpc.c234 * IE. If the LPC transaction has bytes B0, B1, B2 and B3 in that lpc_debug_read()
239 * 32-bit: B0 B1 B2 B3 B0B1B2B3 B3B2B1B0 lpc_debug_read()
319 * 32-bit: B0 B1 B2 B3 B3B2B1B0 B0B1B2B3 lpc_debug_write()
/linux-4.4.14/drivers/net/dsa/
H A Dmv88e6131.c24 { PORT_SWITCH_ID_6131_B2, "Marvell 88E6131 (B2)" },
/linux-4.4.14/drivers/media/tuners/
H A Dmt2060_priv.h33 Reg.No | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 | ( defaults )
H A Dtda9887.c347 tuner_info(" B2 carrier mode : %s\n", dump_write_message()
H A Dmt2063.c1837 step = "B2"; mt2063_init()
/linux-4.4.14/include/memory/
H A Djedec_ddr.h62 #define B2 1 macro
/linux-4.4.14/arch/ia64/kernel/
H A Dentry.h57 .spillsp b2,SW(B2)+16+(off); .spillsp b3,SW(B3)+16+(off); \
H A Dunwind_decoder.c384 UNW_DEC_EPILOGUE(B2, t, (code & 0x1f), arg); unw_decode_b2()
H A Dmca_asm.S602 stf.spill [temp1]=f30,SW(B2)-SW(F30)
761 ldf.fill f30=[temp1],SW(B2)-SW(F30)
H A Dentry.S290 st8.spill [r15]=r7,SW(B2)-SW(R7) // spill r7
302 st8 [r15]=r23,SW(B3)-SW(B2) // save b2
/linux-4.4.14/drivers/misc/
H A Dbmp085.c72 s16 B1, B2; member in struct:bmp085_calibration_data
118 cali->B2 = be16_to_cpu(tmp[7]); bmp085_read_calibration_data()
252 x1 *= cali->B2; bmp085_get_pressure()
/linux-4.4.14/mm/
H A Dinternal.h158 * 1) Any buddy B1 will have an order O twin B2 which satisfies
160 * B2 = B1 ^ (1 << O)
163 * B2 = 8 ^ (1 << 1) = 8 ^ 2 = 10
/linux-4.4.14/include/media/
H A Dadv7842.h112 u16 B2; member in struct:adv7842_sdp_csc_coeff
/linux-4.4.14/arch/blackfin/kernel/
H A Dpseudodbg.c16 "B0", "B1", "B2", "B3", "L0", "L1", "L2", "L3",
H A Dtrace.c975 pr_notice(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n", show_regs()
/linux-4.4.14/sound/pci/cs5535audio/
H A Dcs5535audio_olpc.c26 * High Pass Filter) via GPIO. It is supported on B2 and later models.
/linux-4.4.14/drivers/isdn/hardware/eicon/
H A Dmdm_msg.h136 DLC: B2 modem configuration
328 CAPI B2 Config Constants
H A Ddivacapi.h1116 B2 configuration for PIAFS:
H A Dmessage.c2643 or B2 protocol not any LAPD connect_b3_req()
8261 dbug(1, dprintf("B2-Config")); add_b23()
8274 /* if B2 Protocol is LAPD, b2_config structure is different */ add_b23()
8565 /* B2 Configuration for modem: */
/linux-4.4.14/arch/powerpc/perf/
H A Dppc970-pmu.c91 * SPT0T1 UC PS1 PS2 B0 B1 B2 B3 P1P2P3P4P5P6P7P8
120 * B1, B2, B3
H A Dpower4-pmu.c108 * | UC1 UC2 UC3 ||| PS1 PS2 B0 B1 B2 B3 P1P2P3P4P5P6P7P8
166 * B1, B2, B3
H A Dpower5+-pmu.c80 * NC G0G1G2 G3 T0T1 UC B0 B1 B2 B3 P6P5P4P3P2P1
109 * B1, B2, B3
H A Dpower5-pmu.c80 * T0T1 NC G0G1G2 G3 UC PS1PS2 B0 B1 B2 B3 P6P5P4P3P2P1
117 * B1, B2, B3
/linux-4.4.14/drivers/isdn/hardware/mISDN/
H A Dhfcpci.c274 * STIO1 is used as output for data, B1+B2 from ST->IOM+HFC reset_hfcpci()
275 * STIO2 is used as data input, B1+B2 from IOM->ST reset_hfcpci()
280 /* set data flow directions: connect B1,B2: HFC to/from PCM */ reset_hfcpci()
1208 if (val & 0x10) { /* B2 rx */ hfcpci_int()
1222 if (val & 0x02) { /* B2 tx */ hfcpci_int()
1277 hc->hw.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcpci()
1282 hc->hw.bswapped = 1; /* B1 and B2 exchanged */ mode_hfcpci()
1285 hc->hw.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcpci()
1290 hc->hw.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcpci()
2286 if (bch && bch->state == ISDN_P_B_RAW) { /* B2 rx&tx */ _hfcpci_softirq()
H A DmISDNipac.c619 else if (para & 2) /* B2 */ isac_ctrl()
781 {"2086/2186 V1.1", "2085 B1", "2085 B2",
1205 pr_debug("%s: B2 ISTA %02x\n", ipac->name, ista); mISDNipac_irq()
1237 } else { /* B2 and ICB */ hscx_mode()
1523 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */ channel_ctrl()
H A Dspeedfax.c230 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */ channel_ctrl()
H A Davmfritz.c889 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */ channel_ctrl()
H A Dnetjet.c844 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */ channel_ctrl()
/linux-4.4.14/drivers/isdn/gigaset/
H A Dcapi.c131 [22] = { "8890", "91B2" }, /* International interworking for
966 /* B2 protocols: transparent only */ gigaset_isdn_start()
1536 "B2 Protocol X.75 SLP unsupported, using Transparent\n"); do_connect_req()
1553 "B2 Protocol %u unsupported, using Transparent\n", do_connect_req()
1562 "CONNECT_REQ", "B2 Configuration"); do_connect_req()
1678 "B2 Protocol X.75 SLP unsupported, using Transparent\n"); do_connect_resp()
1695 "B2 Protocol %u unsupported, using Transparent\n", do_connect_resp()
1704 "CONNECT_RESP", "B2 Configuration"); do_connect_resp()
H A Dbas-gigaset.c2645 gig_dbg(DEBUG_INIT, "closing B2 channel"); bas_gigaset_exit()
/linux-4.4.14/net/sched/
H A Dematch.c28 * A AND (B1 OR B2) AND C AND D
34 * | A AND | B AND | C AND | D END | B1 OR | B2 END |
/linux-4.4.14/drivers/tty/
H A Dmoxa.h167 #define FlowControl 0x0C /* B7 B6 B5 B4 B3 B2 B1 B0 */
/linux-4.4.14/drivers/cpufreq/
H A Dsa1110-cpufreq.c158 * CPU steppings prior to B2 must either run the memory at sdram_calculate_timing()
/linux-4.4.14/drivers/net/wireless/b43/
H A Dphy_n.h550 #define B43_NPHY_TXF_20CO_S0B2 B43_PHY_N(0x18D) /* TX filter 20 coeff stage 0 B2 */
553 #define B43_NPHY_TXF_20CO_S1B2 B43_PHY_N(0x190) /* TX filter 20 coeff stage 1 B2 */
556 #define B43_NPHY_TXF_20CO_S2B2 B43_PHY_N(0x193) /* TX filter 20 coeff stage 2 B2 */
565 #define B43_NPHY_TXF_40CO_S0B2 B43_PHY_N(0x19C) /* TX filter 40 coeff stage 0 B2 */
568 #define B43_NPHY_TXF_40CO_S1B2 B43_PHY_N(0x19F) /* TX filter 40 coeff stage 1 B2 */
571 #define B43_NPHY_TXF_40CO_S2B2 B43_PHY_N(0x1A2) /* TX filter 40 coeff stage 2 B2 */
/linux-4.4.14/arch/m68k/ifpsp060/src/
H A Dfplsp.S4933 # even polynomial in r, 1 + r*r*(B1+s*(B2+ ... + s*B8)), #
5129 #--SGN + S'*(B1 + S(B2 + S(B3 + S(B4 + ... + SB8)))), WHERE
5131 #--SGN + S'*([B1+T(B3+T(B5+TB7))] + [S(B2+T(B4+T(B6+TB8)))])
5134 #--WHILE B2 AND B3 ARE IN DOUBLE-EXTENDED FORMAT, B1 IS -1/2
5174 fadd.x COSB2(%pc),%fp2 # B2+T(B4+T(B6+TB8))
5177 fmul.x %fp2,%fp0 # S(B2+T(B4+T(B6+TB8)))
5339 fadd.x COSB2(%pc),%fp2 # B2+S(B3+...)
5342 fmul.x %fp2,%fp0 # S(B2+...)
5345 fadd.s COSB1(%pc),%fp0 # B1+S(B2...)
5346 fmul.x SPRIME(%a6),%fp0 # S'(B1+S(B2+...))
5410 fadd.x COSB2(%pc),%fp1 # B2+S(B3+...)
5413 fmul.x %fp0,%fp1 # S(B2+...)
5417 fadd.s COSB1(%pc),%fp1 # B1+S(B2...)
5419 fmul.x SPRIME(%a6),%fp1 # S'(B1+S(B2+...))
6352 #--ATAN(X) BY X + X*Y*(B1+Y*(B2+Y*(B3+Y*(B4+Y*(B5+Y*B6)))))
6353 #--WHICH IS X + X*Y*( [B1+Z*(B3+Z*B5)] + [Y*(B2+Z*(B4+Z*B6)] )
6379 fadd.d ATANB2(%pc),%fp2 # B2+Z*(B4+Z*B6)
6382 fmul.x %fp0,%fp2 # Y*(B2+Z*(B4+Z*B6))
6385 fadd.x %fp2,%fp1 # [B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))]
6387 fmul.x %fp1,%fp0 # X*Y*([B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))])
6447 # ... +[Y*(B2+Z*(B4+Z*B6))])
6971 # p = X + X*X*(B1 + X*(B2 + ... + X*B12)) #
6975 # precision; and B2 is double extended. #
6983 # Q = X*S*(B2 + X*(B3 + ... + X*B12)) #
6986 # Q = [ X*S*(B2 + S*(B4 + ... + S*B12)) ] + #
7459 fadd.x EM1B2(%pc),%fp1 # fp1 is B2+S*...
7462 fmul.x %fp0,%fp1 # fp1 is S*(B2+...
7465 fmul.x (%a0),%fp1 # fp1 is X*S*(B2...
8341 #--U + U*V*(B1 + V*(B2 + V*(B3 + V*(B4 + V*B5)))) BY
8342 #--U + U*V*( [B1 + W*(B3 + W*B5)] + [V*(B2 + W*B4)] )
8356 fadd.d LOGB2(%pc),%fp2 # B2+W*B4
8360 fmul.x %fp0,%fp2 # V*(B2+W*B4)
8365 fadd.x %fp2,%fp1 # B1+W*(B3+W*B5) + V*(B2+W*B4), FP2 RELEASED
8368 fmul.x %fp1,%fp0 # U*V*( [B1+W*(B3+W*B5)] + [V*(B2+W*B4)] )
H A Dfpsp.S5039 # even polynomial in r, 1 + r*r*(B1+s*(B2+ ... + s*B8)), #
5235 #--SGN + S'*(B1 + S(B2 + S(B3 + S(B4 + ... + SB8)))), WHERE
5237 #--SGN + S'*([B1+T(B3+T(B5+TB7))] + [S(B2+T(B4+T(B6+TB8)))])
5240 #--WHILE B2 AND B3 ARE IN DOUBLE-EXTENDED FORMAT, B1 IS -1/2
5280 fadd.x COSB2(%pc),%fp2 # B2+T(B4+T(B6+TB8))
5283 fmul.x %fp2,%fp0 # S(B2+T(B4+T(B6+TB8)))
5445 fadd.x COSB2(%pc),%fp2 # B2+S(B3+...)
5448 fmul.x %fp2,%fp0 # S(B2+...)
5451 fadd.s COSB1(%pc),%fp0 # B1+S(B2...)
5452 fmul.x SPRIME(%a6),%fp0 # S'(B1+S(B2+...))
5516 fadd.x COSB2(%pc),%fp1 # B2+S(B3+...)
5519 fmul.x %fp0,%fp1 # S(B2+...)
5523 fadd.s COSB1(%pc),%fp1 # B1+S(B2...)
5525 fmul.x SPRIME(%a6),%fp1 # S'(B1+S(B2+...))
6458 #--ATAN(X) BY X + X*Y*(B1+Y*(B2+Y*(B3+Y*(B4+Y*(B5+Y*B6)))))
6459 #--WHICH IS X + X*Y*( [B1+Z*(B3+Z*B5)] + [Y*(B2+Z*(B4+Z*B6)] )
6485 fadd.d ATANB2(%pc),%fp2 # B2+Z*(B4+Z*B6)
6488 fmul.x %fp0,%fp2 # Y*(B2+Z*(B4+Z*B6))
6491 fadd.x %fp2,%fp1 # [B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))]
6493 fmul.x %fp1,%fp0 # X*Y*([B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))])
6553 # ... +[Y*(B2+Z*(B4+Z*B6))])
7077 # p = X + X*X*(B1 + X*(B2 + ... + X*B12)) #
7081 # precision; and B2 is double extended. #
7089 # Q = X*S*(B2 + X*(B3 + ... + X*B12)) #
7092 # Q = [ X*S*(B2 + S*(B4 + ... + S*B12)) ] + #
7565 fadd.x EM1B2(%pc),%fp1 # fp1 is B2+S*...
7568 fmul.x %fp0,%fp1 # fp1 is S*(B2+...
7571 fmul.x (%a0),%fp1 # fp1 is X*S*(B2...
8447 #--U + U*V*(B1 + V*(B2 + V*(B3 + V*(B4 + V*B5)))) BY
8448 #--U + U*V*( [B1 + W*(B3 + W*B5)] + [V*(B2 + W*B4)] )
8462 fadd.d LOGB2(%pc),%fp2 # B2+W*B4
8466 fmul.x %fp0,%fp2 # V*(B2+W*B4)
8471 fadd.x %fp2,%fp1 # B1+W*(B3+W*B5) + V*(B2+W*B4), FP2 RELEASED
8474 fmul.x %fp1,%fp0 # U*V*( [B1+W*(B3+W*B5)] + [V*(B2+W*B4)] )
/linux-4.4.14/drivers/video/fbdev/
H A Dssd1307fb.c171 * B0 B1 B2 B3 B4 ssd1307fb_update_display()
182 * (3) A2 B2 C2 D2 E2 F2 G2 H2 ssd1307fb_update_display()
/linux-4.4.14/drivers/char/agp/
H A Damd64-agp.c360 case 0x13: revstring="B2"; break; amd8151_init()
369 * Chips before B2 stepping incorrectly reporting v3.5 amd8151_init()
/linux-4.4.14/arch/sh/boards/
H A Dboard-magicpanelr2.c106 * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); setup_port_multiplexing()
/linux-4.4.14/drivers/media/i2c/
H A Dad9389b.c182 u16 B1, u16 B2, u16 B3, u16 B4, ad9389b_csc_coeff()
198 ad9389b_wr_and_or(sd, 0x22, 0xe0, B2>>8); ad9389b_csc_coeff()
199 ad9389b_wr(sd, 0x23, B2); ad9389b_csc_coeff()
180 ad9389b_csc_coeff(struct v4l2_subdev *sd, u16 A1, u16 A2, u16 A3, u16 A4, u16 B1, u16 B2, u16 B3, u16 B4, u16 C1, u16 C2, u16 C3, u16 C4) ad9389b_csc_coeff() argument
H A Dadv7511.c289 u16 B1, u16 B2, u16 B3, u16 B4, adv7511_csc_coeff()
305 adv7511_wr_and_or(sd, 0x22, 0xe0, B2>>8); adv7511_csc_coeff()
306 adv7511_wr(sd, 0x23, B2); adv7511_csc_coeff()
287 adv7511_csc_coeff(struct v4l2_subdev *sd, u16 A1, u16 A2, u16 A3, u16 A4, u16 B1, u16 B2, u16 B3, u16 B4, u16 C1, u16 C2, u16 C3, u16 C4) adv7511_csc_coeff() argument
H A Dadv7842.c1765 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8); sdp_csc_coeff()
1766 sdp_io_write(sd, 0xeb, c->B2); sdp_csc_coeff()
H A Dtvaudio.c624 /* B3, B2: output signal select
/linux-4.4.14/drivers/input/mouse/
H A Dvsxxxaa.c274 * [0]: 1 1 0 B4 B3 B2 B1 Pr vsxxxaa_handle_ABS_packet()
/linux-4.4.14/drivers/input/tablet/
H A Dwacom_serial4.c58 * bit 5 B2
/linux-4.4.14/arch/s390/kvm/
H A Dpriv.c616 * A lot of B2 instructions are priviledged. Here we check for kvm_s390_handle_b2()
794 /* This is handled just as for the B2 instructions. */ kvm_s390_handle_b9()
/linux-4.4.14/sound/pci/hda/
H A Dpatch_cirrus.c1007 coef |= 0x0008; /* B1,B2 are GPIOs */ cs4210_pinmux_init()
1012 coef |= 0x0010; /* B2 is SENSE_B, not inverted */ cs4210_pinmux_init()
/linux-4.4.14/drivers/ata/
H A Dsata_mv.c44 * 80x1-B2 errata PCI#11:
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
981 * Workaround for 88SX60x1-B2 FEr SATA#13: mv_write_cached_reg()
3408 * Workaround for 60x1-B2 errata SATA#13: mv6_phy_errata()
3777 /* workaround for 60x1-B2 errata PCI#7 */ mv_60x1b2_errata_pci7()
3824 "Applying B2 workarounds to unknown rev\n"); mv_chip_id()
3845 "Applying B2 workarounds to unknown rev\n"); mv_chip_id()
H A Dsata_sil.c31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
/linux-4.4.14/drivers/ide/
H A Dsiimage.c13 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
/linux-4.4.14/lib/fonts/
H A Dfont_acorn_8x8.c184 /* B2 */ 0xdd, 0x77, 0xdd, 0x77, 0xdd, 0x77, 0xdd, 0x77,
/linux-4.4.14/arch/arm64/kernel/
H A Dinsn.c167 * Section B2.6.5 "Concurrent modification and execution of instructions":
/linux-4.4.14/drivers/isdn/capi/
H A Dcapidrv.c852 return "B2 protocol not supported"; capi_info2str()
858 return "B2 protocol parameter not supported"; capi_info2str()
/linux-4.4.14/drivers/scsi/pm8001/
H A Dpm8001_hwi.h558 /* B2-0 : taskAttribute */
H A Dpm80xx_hwi.h682 /* B2-0 : taskAttribute */
/linux-4.4.14/drivers/isdn/act2000/
H A Dcapi.c1095 /* SELECT B2 PROTOCOL CONF */ actcapi_debug_msg()
/linux-4.4.14/drivers/media/dvb-frontends/
H A Dtda18271c2dd.c595 printk(KERN_ERR "tda18271c2dd: %s %d RF1 = %d A1 = %d B1 = %d RF2 = %d A2 = %d B2 = %d RF3 = %d\n", __func__, RFTrackingFiltersInit()
/linux-4.4.14/drivers/net/wireless/libertas/
H A Dif_cs.c921 pr_err("8381 rev B2 and older are not supported\n"); if_cs_probe()
/linux-4.4.14/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-mt8135.h1990 "B2", "mt8135",
/linux-4.4.14/drivers/net/wireless/ath/carl9170/
H A Drx.c225 * bytes: 04 c2 XX YY B4 B3 B2 B1 carl9170_handle_command_response()
/linux-4.4.14/arch/s390/net/
H A Dbpf_jit_comp.c1000 * B2: pointer to bpf_array bpf_jit_insn()
/linux-4.4.14/drivers/staging/wilc1000/
H A Dwilc_wlan.c1928 } else { /* if(rfrevid == 5) */ /* 1002B2 */ wilc_get_chipid()
/linux-4.4.14/drivers/isdn/mISDN/
H A Dl1oip_core.c1030 ch = rq->adr.channel; /* BRI: 1=B1 2=B2 PRI: 1..15,17.. */ open_bchannel()
/linux-4.4.14/drivers/dma/
H A Dcoh901318.c213 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
/linux-4.4.14/sound/pci/ctxfi/
H A Dcthw20k2.c1628 0x00000000, /* Vol Control B2 */ hw_dac_init()
/linux-4.4.14/drivers/message/fusion/
H A Dmptbase.c1486 product_str = "LSI53C1030 B2"; mpt_get_product_name()
1555 product_str = "LSISAS1064E B2"; mpt_get_product_name()
1595 product_str = "LSISAS1068E B2"; mpt_get_product_name()
/linux-4.4.14/drivers/net/ethernet/marvell/
H A Dsky2.h1231 PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
/linux-4.4.14/sound/pci/
H A Dazt3328.c107 * - "timidity -iAv -B2,8 -Os -EFreverb=0"
/linux-4.4.14/drivers/video/fbdev/aty/
H A Datyfb_base.c508 name = "ATI264VT3 (B2) (Mach64 VT)"; correct_chipset()
/linux-4.4.14/drivers/net/ethernet/sun/
H A Dcassini.h29 * revision ids: 0x30 = Saturn B2
/linux-4.4.14/net/sctp/
H A Dsm_statefuns.c5732 /* ADDIP 4.1 B2) Increment the association error counters and perform sctp_sf_t4_timer_expire()

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