Searched refs:tmp (Results 1 - 200 of 3296) sorted by relevance

1234567891011>>

/linux-4.4.14/drivers/staging/skein/
H A D	threefish_block.c	507 u64 tmp; threefish_decrypt_256() local 513 tmp = b3 ^ b0; threefish_decrypt_256() 514 b3 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 517 tmp = b1 ^ b2; threefish_decrypt_256() 518 b1 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 521 tmp = b1 ^ b0; threefish_decrypt_256() 522 b1 = (tmp >> 58) | (tmp << (64 - 58)); threefish_decrypt_256() 525 tmp = b3 ^ b2; threefish_decrypt_256() 526 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_256() 529 tmp = b3 ^ b0; threefish_decrypt_256() 530 b3 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_256() 533 tmp = b1 ^ b2; threefish_decrypt_256() 534 b1 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_256() 537 tmp = b1 ^ b0; threefish_decrypt_256() 538 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_256() 542 tmp = b3 ^ b2; threefish_decrypt_256() 543 b3 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_256() 547 tmp = b3 ^ b0; threefish_decrypt_256() 548 b3 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_256() 551 tmp = b1 ^ b2; threefish_decrypt_256() 552 b1 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_256() 555 tmp = b1 ^ b0; threefish_decrypt_256() 556 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_256() 559 tmp = b3 ^ b2; threefish_decrypt_256() 560 b3 = (tmp >> 40) | (tmp << (64 - 40)); threefish_decrypt_256() 563 tmp = b3 ^ b0; threefish_decrypt_256() 564 b3 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_256() 567 tmp = b1 ^ b2; threefish_decrypt_256() 568 b1 = (tmp >> 57) | (tmp << (64 - 57)); threefish_decrypt_256() 571 tmp = b1 ^ b0; threefish_decrypt_256() 572 b1 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_256() 576 tmp = b3 ^ b2; threefish_decrypt_256() 577 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_256() 582 tmp = b3 ^ b0; threefish_decrypt_256() 583 b3 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 586 tmp = b1 ^ b2; threefish_decrypt_256() 587 b1 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 590 tmp = b1 ^ b0; threefish_decrypt_256() 591 b1 = (tmp >> 58) | (tmp << (64 - 58)); threefish_decrypt_256() 594 tmp = b3 ^ b2; threefish_decrypt_256() 595 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_256() 598 tmp = b3 ^ b0; threefish_decrypt_256() 599 b3 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_256() 602 tmp = b1 ^ b2; threefish_decrypt_256() 603 b1 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_256() 606 tmp = b1 ^ b0; threefish_decrypt_256() 607 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_256() 611 tmp = b3 ^ b2; threefish_decrypt_256() 612 b3 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_256() 616 tmp = b3 ^ b0; threefish_decrypt_256() 617 b3 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_256() 620 tmp = b1 ^ b2; threefish_decrypt_256() 621 b1 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_256() 624 tmp = b1 ^ b0; threefish_decrypt_256() 625 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_256() 628 tmp = b3 ^ b2; threefish_decrypt_256() 629 b3 = (tmp >> 40) | (tmp << (64 - 40)); threefish_decrypt_256() 632 tmp = b3 ^ b0; threefish_decrypt_256() 633 b3 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_256() 636 tmp = b1 ^ b2; threefish_decrypt_256() 637 b1 = (tmp >> 57) | (tmp << (64 - 57)); threefish_decrypt_256() 640 tmp = b1 ^ b0; threefish_decrypt_256() 641 b1 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_256() 645 tmp = b3 ^ b2; threefish_decrypt_256() 646 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_256() 651 tmp = b3 ^ b0; threefish_decrypt_256() 652 b3 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 655 tmp = b1 ^ b2; threefish_decrypt_256() 656 b1 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 659 tmp = b1 ^ b0; threefish_decrypt_256() 660 b1 = (tmp >> 58) | (tmp << (64 - 58)); threefish_decrypt_256() 663 tmp = b3 ^ b2; threefish_decrypt_256() 664 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_256() 667 tmp = b3 ^ b0; threefish_decrypt_256() 668 b3 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_256() 671 tmp = b1 ^ b2; threefish_decrypt_256() 672 b1 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_256() 675 tmp = b1 ^ b0; threefish_decrypt_256() 676 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_256() 680 tmp = b3 ^ b2; threefish_decrypt_256() 681 b3 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_256() 685 tmp = b3 ^ b0; threefish_decrypt_256() 686 b3 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_256() 689 tmp = b1 ^ b2; threefish_decrypt_256() 690 b1 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_256() 693 tmp = b1 ^ b0; threefish_decrypt_256() 694 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_256() 697 tmp = b3 ^ b2; threefish_decrypt_256() 698 b3 = (tmp >> 40) | (tmp << (64 - 40)); threefish_decrypt_256() 701 tmp = b3 ^ b0; threefish_decrypt_256() 702 b3 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_256() 705 tmp = b1 ^ b2; threefish_decrypt_256() 706 b1 = (tmp >> 57) | (tmp << (64 - 57)); threefish_decrypt_256() 709 tmp = b1 ^ b0; threefish_decrypt_256() 710 b1 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_256() 714 tmp = b3 ^ b2; threefish_decrypt_256() 715 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_256() 720 tmp = b3 ^ b0; threefish_decrypt_256() 721 b3 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 724 tmp = b1 ^ b2; threefish_decrypt_256() 725 b1 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 728 tmp = b1 ^ b0; threefish_decrypt_256() 729 b1 = (tmp >> 58) | (tmp << (64 - 58)); threefish_decrypt_256() 732 tmp = b3 ^ b2; threefish_decrypt_256() 733 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_256() 736 tmp = b3 ^ b0; threefish_decrypt_256() 737 b3 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_256() 740 tmp = b1 ^ b2; threefish_decrypt_256() 741 b1 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_256() 744 tmp = b1 ^ b0; threefish_decrypt_256() 745 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_256() 749 tmp = b3 ^ b2; threefish_decrypt_256() 750 b3 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_256() 754 tmp = b3 ^ b0; threefish_decrypt_256() 755 b3 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_256() 758 tmp = b1 ^ b2; threefish_decrypt_256() 759 b1 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_256() 762 tmp = b1 ^ b0; threefish_decrypt_256() 763 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_256() 766 tmp = b3 ^ b2; threefish_decrypt_256() 767 b3 = (tmp >> 40) | (tmp << (64 - 40)); threefish_decrypt_256() 770 tmp = b3 ^ b0; threefish_decrypt_256() 771 b3 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_256() 774 tmp = b1 ^ b2; threefish_decrypt_256() 775 b1 = (tmp >> 57) | (tmp << (64 - 57)); threefish_decrypt_256() 778 tmp = b1 ^ b0; threefish_decrypt_256() 779 b1 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_256() 783 tmp = b3 ^ b2; threefish_decrypt_256() 784 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_256() 789 tmp = b3 ^ b0; threefish_decrypt_256() 790 b3 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 793 tmp = b1 ^ b2; threefish_decrypt_256() 794 b1 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 797 tmp = b1 ^ b0; threefish_decrypt_256() 798 b1 = (tmp >> 58) | (tmp << (64 - 58)); threefish_decrypt_256() 801 tmp = b3 ^ b2; threefish_decrypt_256() 802 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_256() 805 tmp = b3 ^ b0; threefish_decrypt_256() 806 b3 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_256() 809 tmp = b1 ^ b2; threefish_decrypt_256() 810 b1 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_256() 813 tmp = b1 ^ b0; threefish_decrypt_256() 814 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_256() 818 tmp = b3 ^ b2; threefish_decrypt_256() 819 b3 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_256() 823 tmp = b3 ^ b0; threefish_decrypt_256() 824 b3 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_256() 827 tmp = b1 ^ b2; threefish_decrypt_256() 828 b1 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_256() 831 tmp = b1 ^ b0; threefish_decrypt_256() 832 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_256() 835 tmp = b3 ^ b2; threefish_decrypt_256() 836 b3 = (tmp >> 40) | (tmp << (64 - 40)); threefish_decrypt_256() 839 tmp = b3 ^ b0; threefish_decrypt_256() 840 b3 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_256() 843 tmp = b1 ^ b2; threefish_decrypt_256() 844 b1 = (tmp >> 57) | (tmp << (64 - 57)); threefish_decrypt_256() 847 tmp = b1 ^ b0; threefish_decrypt_256() 848 b1 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_256() 852 tmp = b3 ^ b2; threefish_decrypt_256() 853 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_256() 858 tmp = b3 ^ b0; threefish_decrypt_256() 859 b3 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 862 tmp = b1 ^ b2; threefish_decrypt_256() 863 b1 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 866 tmp = b1 ^ b0; threefish_decrypt_256() 867 b1 = (tmp >> 58) | (tmp << (64 - 58)); threefish_decrypt_256() 870 tmp = b3 ^ b2; threefish_decrypt_256() 871 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_256() 874 tmp = b3 ^ b0; threefish_decrypt_256() 875 b3 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_256() 878 tmp = b1 ^ b2; threefish_decrypt_256() 879 b1 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_256() 882 tmp = b1 ^ b0; threefish_decrypt_256() 883 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_256() 887 tmp = b3 ^ b2; threefish_decrypt_256() 888 b3 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_256() 892 tmp = b3 ^ b0; threefish_decrypt_256() 893 b3 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_256() 896 tmp = b1 ^ b2; threefish_decrypt_256() 897 b1 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_256() 900 tmp = b1 ^ b0; threefish_decrypt_256() 901 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_256() 904 tmp = b3 ^ b2; threefish_decrypt_256() 905 b3 = (tmp >> 40) | (tmp << (64 - 40)); threefish_decrypt_256() 908 tmp = b3 ^ b0; threefish_decrypt_256() 909 b3 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_256() 912 tmp = b1 ^ b2; threefish_decrypt_256() 913 b1 = (tmp >> 57) | (tmp << (64 - 57)); threefish_decrypt_256() 916 tmp = b1 ^ b0; threefish_decrypt_256() 917 b1 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_256() 921 tmp = b3 ^ b2; threefish_decrypt_256() 922 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_256() 927 tmp = b3 ^ b0; threefish_decrypt_256() 928 b3 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 931 tmp = b1 ^ b2; threefish_decrypt_256() 932 b1 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 935 tmp = b1 ^ b0; threefish_decrypt_256() 936 b1 = (tmp >> 58) | (tmp << (64 - 58)); threefish_decrypt_256() 939 tmp = b3 ^ b2; threefish_decrypt_256() 940 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_256() 943 tmp = b3 ^ b0; threefish_decrypt_256() 944 b3 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_256() 947 tmp = b1 ^ b2; threefish_decrypt_256() 948 b1 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_256() 951 tmp = b1 ^ b0; threefish_decrypt_256() 952 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_256() 956 tmp = b3 ^ b2; threefish_decrypt_256() 957 b3 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_256() 961 tmp = b3 ^ b0; threefish_decrypt_256() 962 b3 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_256() 965 tmp = b1 ^ b2; threefish_decrypt_256() 966 b1 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_256() 969 tmp = b1 ^ b0; threefish_decrypt_256() 970 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_256() 973 tmp = b3 ^ b2; threefish_decrypt_256() 974 b3 = (tmp >> 40) | (tmp << (64 - 40)); threefish_decrypt_256() 977 tmp = b3 ^ b0; threefish_decrypt_256() 978 b3 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_256() 981 tmp = b1 ^ b2; threefish_decrypt_256() 982 b1 = (tmp >> 57) | (tmp << (64 - 57)); threefish_decrypt_256() 985 tmp = b1 ^ b0; threefish_decrypt_256() 986 b1 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_256() 990 tmp = b3 ^ b2; threefish_decrypt_256() 991 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_256() 996 tmp = b3 ^ b0; threefish_decrypt_256() 997 b3 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 1000 tmp = b1 ^ b2; threefish_decrypt_256() 1001 b1 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 1004 tmp = b1 ^ b0; threefish_decrypt_256() 1005 b1 = (tmp >> 58) | (tmp << (64 - 58)); threefish_decrypt_256() 1008 tmp = b3 ^ b2; threefish_decrypt_256() 1009 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_256() 1012 tmp = b3 ^ b0; threefish_decrypt_256() 1013 b3 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_256() 1016 tmp = b1 ^ b2; threefish_decrypt_256() 1017 b1 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_256() 1020 tmp = b1 ^ b0; threefish_decrypt_256() 1021 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_256() 1025 tmp = b3 ^ b2; threefish_decrypt_256() 1026 b3 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_256() 1030 tmp = b3 ^ b0; threefish_decrypt_256() 1031 b3 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_256() 1034 tmp = b1 ^ b2; threefish_decrypt_256() 1035 b1 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_256() 1038 tmp = b1 ^ b0; threefish_decrypt_256() 1039 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_256() 1042 tmp = b3 ^ b2; threefish_decrypt_256() 1043 b3 = (tmp >> 40) | (tmp << (64 - 40)); threefish_decrypt_256() 1046 tmp = b3 ^ b0; threefish_decrypt_256() 1047 b3 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_256() 1050 tmp = b1 ^ b2; threefish_decrypt_256() 1051 b1 = (tmp >> 57) | (tmp << (64 - 57)); threefish_decrypt_256() 1054 tmp = b1 ^ b0; threefish_decrypt_256() 1055 b1 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_256() 1059 tmp = b3 ^ b2; threefish_decrypt_256() 1060 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_256() 1065 tmp = b3 ^ b0; threefish_decrypt_256() 1066 b3 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 1069 tmp = b1 ^ b2; threefish_decrypt_256() 1070 b1 = (tmp >> 32) | (tmp << (64 - 32)); threefish_decrypt_256() 1073 tmp = b1 ^ b0; threefish_decrypt_256() 1074 b1 = (tmp >> 58) | (tmp << (64 - 58)); threefish_decrypt_256() 1077 tmp = b3 ^ b2; threefish_decrypt_256() 1078 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_256() 1081 tmp = b3 ^ b0; threefish_decrypt_256() 1082 b3 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_256() 1085 tmp = b1 ^ b2; threefish_decrypt_256() 1086 b1 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_256() 1089 tmp = b1 ^ b0; threefish_decrypt_256() 1090 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_256() 1094 tmp = b3 ^ b2; threefish_decrypt_256() 1095 b3 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_256() 1099 tmp = b3 ^ b0; threefish_decrypt_256() 1100 b3 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_256() 1103 tmp = b1 ^ b2; threefish_decrypt_256() 1104 b1 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_256() 1107 tmp = b1 ^ b0; threefish_decrypt_256() 1108 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_256() 1111 tmp = b3 ^ b2; threefish_decrypt_256() 1112 b3 = (tmp >> 40) | (tmp << (64 - 40)); threefish_decrypt_256() 1115 tmp = b3 ^ b0; threefish_decrypt_256() 1116 b3 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_256() 1119 tmp = b1 ^ b2; threefish_decrypt_256() 1120 b1 = (tmp >> 57) | (tmp << (64 - 57)); threefish_decrypt_256() 1123 tmp = b1 ^ b0; threefish_decrypt_256() 1124 b1 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_256() 1128 tmp = b3 ^ b2; threefish_decrypt_256() 1129 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_256() 2115 u64 tmp; threefish_decrypt_512() local 2126 tmp = b3 ^ b4; threefish_decrypt_512() 2127 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_512() 2130 tmp = b5 ^ b2; threefish_decrypt_512() 2131 b5 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 2134 tmp = b7 ^ b0; threefish_decrypt_512() 2135 b7 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_512() 2138 tmp = b1 ^ b6; threefish_decrypt_512() 2139 b1 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_512() 2142 tmp = b7 ^ b2; threefish_decrypt_512() 2143 b7 = (tmp >> 43) | (tmp << (64 - 43)); threefish_decrypt_512() 2146 tmp = b5 ^ b0; threefish_decrypt_512() 2147 b5 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2150 tmp = b3 ^ b6; threefish_decrypt_512() 2151 b3 = (tmp >> 29) | (tmp << (64 - 29)); threefish_decrypt_512() 2154 tmp = b1 ^ b4; threefish_decrypt_512() 2155 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_512() 2158 tmp = b3 ^ b0; threefish_decrypt_512() 2159 b3 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 2162 tmp = b5 ^ b6; threefish_decrypt_512() 2163 b5 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_512() 2166 tmp = b7 ^ b4; threefish_decrypt_512() 2167 b7 = (tmp >> 50) | (tmp << (64 - 50)); threefish_decrypt_512() 2170 tmp = b1 ^ b2; threefish_decrypt_512() 2171 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_512() 2174 tmp = b7 ^ b6; threefish_decrypt_512() 2175 b7 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_512() 2179 tmp = b5 ^ b4; threefish_decrypt_512() 2180 b5 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_512() 2184 tmp = b3 ^ b2; threefish_decrypt_512() 2185 b3 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_512() 2189 tmp = b1 ^ b0; threefish_decrypt_512() 2190 b1 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2194 tmp = b3 ^ b4; threefish_decrypt_512() 2195 b3 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 2198 tmp = b5 ^ b2; threefish_decrypt_512() 2199 b5 = (tmp >> 54) | (tmp << (64 - 54)); threefish_decrypt_512() 2202 tmp = b7 ^ b0; threefish_decrypt_512() 2203 b7 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_512() 2206 tmp = b1 ^ b6; threefish_decrypt_512() 2207 b1 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_512() 2210 tmp = b7 ^ b2; threefish_decrypt_512() 2211 b7 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2214 tmp = b5 ^ b0; threefish_decrypt_512() 2215 b5 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 2218 tmp = b3 ^ b6; threefish_decrypt_512() 2219 b3 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_512() 2222 tmp = b1 ^ b4; threefish_decrypt_512() 2223 b1 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 2226 tmp = b3 ^ b0; threefish_decrypt_512() 2227 b3 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_512() 2230 tmp = b5 ^ b6; threefish_decrypt_512() 2231 b5 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_512() 2234 tmp = b7 ^ b4; threefish_decrypt_512() 2235 b7 = (tmp >> 27) | (tmp << (64 - 27)); threefish_decrypt_512() 2238 tmp = b1 ^ b2; threefish_decrypt_512() 2239 b1 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_512() 2242 tmp = b7 ^ b6; threefish_decrypt_512() 2243 b7 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_512() 2247 tmp = b5 ^ b4; threefish_decrypt_512() 2248 b5 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_512() 2252 tmp = b3 ^ b2; threefish_decrypt_512() 2253 b3 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 2257 tmp = b1 ^ b0; threefish_decrypt_512() 2258 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_512() 2262 tmp = b3 ^ b4; threefish_decrypt_512() 2263 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_512() 2266 tmp = b5 ^ b2; threefish_decrypt_512() 2267 b5 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 2270 tmp = b7 ^ b0; threefish_decrypt_512() 2271 b7 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_512() 2274 tmp = b1 ^ b6; threefish_decrypt_512() 2275 b1 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_512() 2278 tmp = b7 ^ b2; threefish_decrypt_512() 2279 b7 = (tmp >> 43) | (tmp << (64 - 43)); threefish_decrypt_512() 2282 tmp = b5 ^ b0; threefish_decrypt_512() 2283 b5 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2286 tmp = b3 ^ b6; threefish_decrypt_512() 2287 b3 = (tmp >> 29) | (tmp << (64 - 29)); threefish_decrypt_512() 2290 tmp = b1 ^ b4; threefish_decrypt_512() 2291 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_512() 2294 tmp = b3 ^ b0; threefish_decrypt_512() 2295 b3 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 2298 tmp = b5 ^ b6; threefish_decrypt_512() 2299 b5 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_512() 2302 tmp = b7 ^ b4; threefish_decrypt_512() 2303 b7 = (tmp >> 50) | (tmp << (64 - 50)); threefish_decrypt_512() 2306 tmp = b1 ^ b2; threefish_decrypt_512() 2307 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_512() 2310 tmp = b7 ^ b6; threefish_decrypt_512() 2311 b7 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_512() 2315 tmp = b5 ^ b4; threefish_decrypt_512() 2316 b5 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_512() 2320 tmp = b3 ^ b2; threefish_decrypt_512() 2321 b3 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_512() 2325 tmp = b1 ^ b0; threefish_decrypt_512() 2326 b1 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2330 tmp = b3 ^ b4; threefish_decrypt_512() 2331 b3 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 2334 tmp = b5 ^ b2; threefish_decrypt_512() 2335 b5 = (tmp >> 54) | (tmp << (64 - 54)); threefish_decrypt_512() 2338 tmp = b7 ^ b0; threefish_decrypt_512() 2339 b7 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_512() 2342 tmp = b1 ^ b6; threefish_decrypt_512() 2343 b1 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_512() 2346 tmp = b7 ^ b2; threefish_decrypt_512() 2347 b7 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2350 tmp = b5 ^ b0; threefish_decrypt_512() 2351 b5 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 2354 tmp = b3 ^ b6; threefish_decrypt_512() 2355 b3 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_512() 2358 tmp = b1 ^ b4; threefish_decrypt_512() 2359 b1 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 2362 tmp = b3 ^ b0; threefish_decrypt_512() 2363 b3 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_512() 2366 tmp = b5 ^ b6; threefish_decrypt_512() 2367 b5 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_512() 2370 tmp = b7 ^ b4; threefish_decrypt_512() 2371 b7 = (tmp >> 27) | (tmp << (64 - 27)); threefish_decrypt_512() 2374 tmp = b1 ^ b2; threefish_decrypt_512() 2375 b1 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_512() 2378 tmp = b7 ^ b6; threefish_decrypt_512() 2379 b7 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_512() 2383 tmp = b5 ^ b4; threefish_decrypt_512() 2384 b5 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_512() 2388 tmp = b3 ^ b2; threefish_decrypt_512() 2389 b3 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 2393 tmp = b1 ^ b0; threefish_decrypt_512() 2394 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_512() 2398 tmp = b3 ^ b4; threefish_decrypt_512() 2399 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_512() 2402 tmp = b5 ^ b2; threefish_decrypt_512() 2403 b5 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 2406 tmp = b7 ^ b0; threefish_decrypt_512() 2407 b7 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_512() 2410 tmp = b1 ^ b6; threefish_decrypt_512() 2411 b1 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_512() 2414 tmp = b7 ^ b2; threefish_decrypt_512() 2415 b7 = (tmp >> 43) | (tmp << (64 - 43)); threefish_decrypt_512() 2418 tmp = b5 ^ b0; threefish_decrypt_512() 2419 b5 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2422 tmp = b3 ^ b6; threefish_decrypt_512() 2423 b3 = (tmp >> 29) | (tmp << (64 - 29)); threefish_decrypt_512() 2426 tmp = b1 ^ b4; threefish_decrypt_512() 2427 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_512() 2430 tmp = b3 ^ b0; threefish_decrypt_512() 2431 b3 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 2434 tmp = b5 ^ b6; threefish_decrypt_512() 2435 b5 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_512() 2438 tmp = b7 ^ b4; threefish_decrypt_512() 2439 b7 = (tmp >> 50) | (tmp << (64 - 50)); threefish_decrypt_512() 2442 tmp = b1 ^ b2; threefish_decrypt_512() 2443 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_512() 2446 tmp = b7 ^ b6; threefish_decrypt_512() 2447 b7 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_512() 2451 tmp = b5 ^ b4; threefish_decrypt_512() 2452 b5 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_512() 2456 tmp = b3 ^ b2; threefish_decrypt_512() 2457 b3 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_512() 2461 tmp = b1 ^ b0; threefish_decrypt_512() 2462 b1 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2466 tmp = b3 ^ b4; threefish_decrypt_512() 2467 b3 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 2470 tmp = b5 ^ b2; threefish_decrypt_512() 2471 b5 = (tmp >> 54) | (tmp << (64 - 54)); threefish_decrypt_512() 2474 tmp = b7 ^ b0; threefish_decrypt_512() 2475 b7 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_512() 2478 tmp = b1 ^ b6; threefish_decrypt_512() 2479 b1 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_512() 2482 tmp = b7 ^ b2; threefish_decrypt_512() 2483 b7 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2486 tmp = b5 ^ b0; threefish_decrypt_512() 2487 b5 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 2490 tmp = b3 ^ b6; threefish_decrypt_512() 2491 b3 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_512() 2494 tmp = b1 ^ b4; threefish_decrypt_512() 2495 b1 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 2498 tmp = b3 ^ b0; threefish_decrypt_512() 2499 b3 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_512() 2502 tmp = b5 ^ b6; threefish_decrypt_512() 2503 b5 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_512() 2506 tmp = b7 ^ b4; threefish_decrypt_512() 2507 b7 = (tmp >> 27) | (tmp << (64 - 27)); threefish_decrypt_512() 2510 tmp = b1 ^ b2; threefish_decrypt_512() 2511 b1 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_512() 2514 tmp = b7 ^ b6; threefish_decrypt_512() 2515 b7 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_512() 2519 tmp = b5 ^ b4; threefish_decrypt_512() 2520 b5 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_512() 2524 tmp = b3 ^ b2; threefish_decrypt_512() 2525 b3 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 2529 tmp = b1 ^ b0; threefish_decrypt_512() 2530 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_512() 2534 tmp = b3 ^ b4; threefish_decrypt_512() 2535 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_512() 2538 tmp = b5 ^ b2; threefish_decrypt_512() 2539 b5 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 2542 tmp = b7 ^ b0; threefish_decrypt_512() 2543 b7 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_512() 2546 tmp = b1 ^ b6; threefish_decrypt_512() 2547 b1 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_512() 2550 tmp = b7 ^ b2; threefish_decrypt_512() 2551 b7 = (tmp >> 43) | (tmp << (64 - 43)); threefish_decrypt_512() 2554 tmp = b5 ^ b0; threefish_decrypt_512() 2555 b5 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2558 tmp = b3 ^ b6; threefish_decrypt_512() 2559 b3 = (tmp >> 29) | (tmp << (64 - 29)); threefish_decrypt_512() 2562 tmp = b1 ^ b4; threefish_decrypt_512() 2563 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_512() 2566 tmp = b3 ^ b0; threefish_decrypt_512() 2567 b3 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 2570 tmp = b5 ^ b6; threefish_decrypt_512() 2571 b5 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_512() 2574 tmp = b7 ^ b4; threefish_decrypt_512() 2575 b7 = (tmp >> 50) | (tmp << (64 - 50)); threefish_decrypt_512() 2578 tmp = b1 ^ b2; threefish_decrypt_512() 2579 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_512() 2582 tmp = b7 ^ b6; threefish_decrypt_512() 2583 b7 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_512() 2587 tmp = b5 ^ b4; threefish_decrypt_512() 2588 b5 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_512() 2592 tmp = b3 ^ b2; threefish_decrypt_512() 2593 b3 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_512() 2597 tmp = b1 ^ b0; threefish_decrypt_512() 2598 b1 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2602 tmp = b3 ^ b4; threefish_decrypt_512() 2603 b3 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 2606 tmp = b5 ^ b2; threefish_decrypt_512() 2607 b5 = (tmp >> 54) | (tmp << (64 - 54)); threefish_decrypt_512() 2610 tmp = b7 ^ b0; threefish_decrypt_512() 2611 b7 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_512() 2614 tmp = b1 ^ b6; threefish_decrypt_512() 2615 b1 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_512() 2618 tmp = b7 ^ b2; threefish_decrypt_512() 2619 b7 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2622 tmp = b5 ^ b0; threefish_decrypt_512() 2623 b5 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 2626 tmp = b3 ^ b6; threefish_decrypt_512() 2627 b3 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_512() 2630 tmp = b1 ^ b4; threefish_decrypt_512() 2631 b1 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 2634 tmp = b3 ^ b0; threefish_decrypt_512() 2635 b3 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_512() 2638 tmp = b5 ^ b6; threefish_decrypt_512() 2639 b5 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_512() 2642 tmp = b7 ^ b4; threefish_decrypt_512() 2643 b7 = (tmp >> 27) | (tmp << (64 - 27)); threefish_decrypt_512() 2646 tmp = b1 ^ b2; threefish_decrypt_512() 2647 b1 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_512() 2650 tmp = b7 ^ b6; threefish_decrypt_512() 2651 b7 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_512() 2655 tmp = b5 ^ b4; threefish_decrypt_512() 2656 b5 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_512() 2660 tmp = b3 ^ b2; threefish_decrypt_512() 2661 b3 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 2665 tmp = b1 ^ b0; threefish_decrypt_512() 2666 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_512() 2670 tmp = b3 ^ b4; threefish_decrypt_512() 2671 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_512() 2674 tmp = b5 ^ b2; threefish_decrypt_512() 2675 b5 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 2678 tmp = b7 ^ b0; threefish_decrypt_512() 2679 b7 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_512() 2682 tmp = b1 ^ b6; threefish_decrypt_512() 2683 b1 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_512() 2686 tmp = b7 ^ b2; threefish_decrypt_512() 2687 b7 = (tmp >> 43) | (tmp << (64 - 43)); threefish_decrypt_512() 2690 tmp = b5 ^ b0; threefish_decrypt_512() 2691 b5 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2694 tmp = b3 ^ b6; threefish_decrypt_512() 2695 b3 = (tmp >> 29) | (tmp << (64 - 29)); threefish_decrypt_512() 2698 tmp = b1 ^ b4; threefish_decrypt_512() 2699 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_512() 2702 tmp = b3 ^ b0; threefish_decrypt_512() 2703 b3 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 2706 tmp = b5 ^ b6; threefish_decrypt_512() 2707 b5 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_512() 2710 tmp = b7 ^ b4; threefish_decrypt_512() 2711 b7 = (tmp >> 50) | (tmp << (64 - 50)); threefish_decrypt_512() 2714 tmp = b1 ^ b2; threefish_decrypt_512() 2715 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_512() 2718 tmp = b7 ^ b6; threefish_decrypt_512() 2719 b7 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_512() 2723 tmp = b5 ^ b4; threefish_decrypt_512() 2724 b5 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_512() 2728 tmp = b3 ^ b2; threefish_decrypt_512() 2729 b3 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_512() 2733 tmp = b1 ^ b0; threefish_decrypt_512() 2734 b1 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2738 tmp = b3 ^ b4; threefish_decrypt_512() 2739 b3 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 2742 tmp = b5 ^ b2; threefish_decrypt_512() 2743 b5 = (tmp >> 54) | (tmp << (64 - 54)); threefish_decrypt_512() 2746 tmp = b7 ^ b0; threefish_decrypt_512() 2747 b7 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_512() 2750 tmp = b1 ^ b6; threefish_decrypt_512() 2751 b1 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_512() 2754 tmp = b7 ^ b2; threefish_decrypt_512() 2755 b7 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2758 tmp = b5 ^ b0; threefish_decrypt_512() 2759 b5 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 2762 tmp = b3 ^ b6; threefish_decrypt_512() 2763 b3 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_512() 2766 tmp = b1 ^ b4; threefish_decrypt_512() 2767 b1 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 2770 tmp = b3 ^ b0; threefish_decrypt_512() 2771 b3 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_512() 2774 tmp = b5 ^ b6; threefish_decrypt_512() 2775 b5 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_512() 2778 tmp = b7 ^ b4; threefish_decrypt_512() 2779 b7 = (tmp >> 27) | (tmp << (64 - 27)); threefish_decrypt_512() 2782 tmp = b1 ^ b2; threefish_decrypt_512() 2783 b1 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_512() 2786 tmp = b7 ^ b6; threefish_decrypt_512() 2787 b7 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_512() 2791 tmp = b5 ^ b4; threefish_decrypt_512() 2792 b5 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_512() 2796 tmp = b3 ^ b2; threefish_decrypt_512() 2797 b3 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 2801 tmp = b1 ^ b0; threefish_decrypt_512() 2802 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_512() 2806 tmp = b3 ^ b4; threefish_decrypt_512() 2807 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_512() 2810 tmp = b5 ^ b2; threefish_decrypt_512() 2811 b5 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 2814 tmp = b7 ^ b0; threefish_decrypt_512() 2815 b7 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_512() 2818 tmp = b1 ^ b6; threefish_decrypt_512() 2819 b1 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_512() 2822 tmp = b7 ^ b2; threefish_decrypt_512() 2823 b7 = (tmp >> 43) | (tmp << (64 - 43)); threefish_decrypt_512() 2826 tmp = b5 ^ b0; threefish_decrypt_512() 2827 b5 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2830 tmp = b3 ^ b6; threefish_decrypt_512() 2831 b3 = (tmp >> 29) | (tmp << (64 - 29)); threefish_decrypt_512() 2834 tmp = b1 ^ b4; threefish_decrypt_512() 2835 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_512() 2838 tmp = b3 ^ b0; threefish_decrypt_512() 2839 b3 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 2842 tmp = b5 ^ b6; threefish_decrypt_512() 2843 b5 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_512() 2846 tmp = b7 ^ b4; threefish_decrypt_512() 2847 b7 = (tmp >> 50) | (tmp << (64 - 50)); threefish_decrypt_512() 2850 tmp = b1 ^ b2; threefish_decrypt_512() 2851 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_512() 2854 tmp = b7 ^ b6; threefish_decrypt_512() 2855 b7 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_512() 2859 tmp = b5 ^ b4; threefish_decrypt_512() 2860 b5 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_512() 2864 tmp = b3 ^ b2; threefish_decrypt_512() 2865 b3 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_512() 2869 tmp = b1 ^ b0; threefish_decrypt_512() 2870 b1 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2874 tmp = b3 ^ b4; threefish_decrypt_512() 2875 b3 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 2878 tmp = b5 ^ b2; threefish_decrypt_512() 2879 b5 = (tmp >> 54) | (tmp << (64 - 54)); threefish_decrypt_512() 2882 tmp = b7 ^ b0; threefish_decrypt_512() 2883 b7 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_512() 2886 tmp = b1 ^ b6; threefish_decrypt_512() 2887 b1 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_512() 2890 tmp = b7 ^ b2; threefish_decrypt_512() 2891 b7 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2894 tmp = b5 ^ b0; threefish_decrypt_512() 2895 b5 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 2898 tmp = b3 ^ b6; threefish_decrypt_512() 2899 b3 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_512() 2902 tmp = b1 ^ b4; threefish_decrypt_512() 2903 b1 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 2906 tmp = b3 ^ b0; threefish_decrypt_512() 2907 b3 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_512() 2910 tmp = b5 ^ b6; threefish_decrypt_512() 2911 b5 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_512() 2914 tmp = b7 ^ b4; threefish_decrypt_512() 2915 b7 = (tmp >> 27) | (tmp << (64 - 27)); threefish_decrypt_512() 2918 tmp = b1 ^ b2; threefish_decrypt_512() 2919 b1 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_512() 2922 tmp = b7 ^ b6; threefish_decrypt_512() 2923 b7 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_512() 2927 tmp = b5 ^ b4; threefish_decrypt_512() 2928 b5 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_512() 2932 tmp = b3 ^ b2; threefish_decrypt_512() 2933 b3 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 2937 tmp = b1 ^ b0; threefish_decrypt_512() 2938 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_512() 2942 tmp = b3 ^ b4; threefish_decrypt_512() 2943 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_512() 2946 tmp = b5 ^ b2; threefish_decrypt_512() 2947 b5 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 2950 tmp = b7 ^ b0; threefish_decrypt_512() 2951 b7 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_512() 2954 tmp = b1 ^ b6; threefish_decrypt_512() 2955 b1 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_512() 2958 tmp = b7 ^ b2; threefish_decrypt_512() 2959 b7 = (tmp >> 43) | (tmp << (64 - 43)); threefish_decrypt_512() 2962 tmp = b5 ^ b0; threefish_decrypt_512() 2963 b5 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 2966 tmp = b3 ^ b6; threefish_decrypt_512() 2967 b3 = (tmp >> 29) | (tmp << (64 - 29)); threefish_decrypt_512() 2970 tmp = b1 ^ b4; threefish_decrypt_512() 2971 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_512() 2974 tmp = b3 ^ b0; threefish_decrypt_512() 2975 b3 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 2978 tmp = b5 ^ b6; threefish_decrypt_512() 2979 b5 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_512() 2982 tmp = b7 ^ b4; threefish_decrypt_512() 2983 b7 = (tmp >> 50) | (tmp << (64 - 50)); threefish_decrypt_512() 2986 tmp = b1 ^ b2; threefish_decrypt_512() 2987 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_512() 2990 tmp = b7 ^ b6; threefish_decrypt_512() 2991 b7 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_512() 2995 tmp = b5 ^ b4; threefish_decrypt_512() 2996 b5 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_512() 3000 tmp = b3 ^ b2; threefish_decrypt_512() 3001 b3 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_512() 3005 tmp = b1 ^ b0; threefish_decrypt_512() 3006 b1 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 3010 tmp = b3 ^ b4; threefish_decrypt_512() 3011 b3 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 3014 tmp = b5 ^ b2; threefish_decrypt_512() 3015 b5 = (tmp >> 54) | (tmp << (64 - 54)); threefish_decrypt_512() 3018 tmp = b7 ^ b0; threefish_decrypt_512() 3019 b7 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_512() 3022 tmp = b1 ^ b6; threefish_decrypt_512() 3023 b1 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_512() 3026 tmp = b7 ^ b2; threefish_decrypt_512() 3027 b7 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 3030 tmp = b5 ^ b0; threefish_decrypt_512() 3031 b5 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 3034 tmp = b3 ^ b6; threefish_decrypt_512() 3035 b3 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_512() 3038 tmp = b1 ^ b4; threefish_decrypt_512() 3039 b1 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 3042 tmp = b3 ^ b0; threefish_decrypt_512() 3043 b3 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_512() 3046 tmp = b5 ^ b6; threefish_decrypt_512() 3047 b5 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_512() 3050 tmp = b7 ^ b4; threefish_decrypt_512() 3051 b7 = (tmp >> 27) | (tmp << (64 - 27)); threefish_decrypt_512() 3054 tmp = b1 ^ b2; threefish_decrypt_512() 3055 b1 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_512() 3058 tmp = b7 ^ b6; threefish_decrypt_512() 3059 b7 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_512() 3063 tmp = b5 ^ b4; threefish_decrypt_512() 3064 b5 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_512() 3068 tmp = b3 ^ b2; threefish_decrypt_512() 3069 b3 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 3073 tmp = b1 ^ b0; threefish_decrypt_512() 3074 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_512() 3078 tmp = b3 ^ b4; threefish_decrypt_512() 3079 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_512() 3082 tmp = b5 ^ b2; threefish_decrypt_512() 3083 b5 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 3086 tmp = b7 ^ b0; threefish_decrypt_512() 3087 b7 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_512() 3090 tmp = b1 ^ b6; threefish_decrypt_512() 3091 b1 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_512() 3094 tmp = b7 ^ b2; threefish_decrypt_512() 3095 b7 = (tmp >> 43) | (tmp << (64 - 43)); threefish_decrypt_512() 3098 tmp = b5 ^ b0; threefish_decrypt_512() 3099 b5 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 3102 tmp = b3 ^ b6; threefish_decrypt_512() 3103 b3 = (tmp >> 29) | (tmp << (64 - 29)); threefish_decrypt_512() 3106 tmp = b1 ^ b4; threefish_decrypt_512() 3107 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_512() 3110 tmp = b3 ^ b0; threefish_decrypt_512() 3111 b3 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 3114 tmp = b5 ^ b6; threefish_decrypt_512() 3115 b5 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_512() 3118 tmp = b7 ^ b4; threefish_decrypt_512() 3119 b7 = (tmp >> 50) | (tmp << (64 - 50)); threefish_decrypt_512() 3122 tmp = b1 ^ b2; threefish_decrypt_512() 3123 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_512() 3126 tmp = b7 ^ b6; threefish_decrypt_512() 3127 b7 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_512() 3131 tmp = b5 ^ b4; threefish_decrypt_512() 3132 b5 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_512() 3136 tmp = b3 ^ b2; threefish_decrypt_512() 3137 b3 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_512() 3141 tmp = b1 ^ b0; threefish_decrypt_512() 3142 b1 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 3146 tmp = b3 ^ b4; threefish_decrypt_512() 3147 b3 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 3150 tmp = b5 ^ b2; threefish_decrypt_512() 3151 b5 = (tmp >> 54) | (tmp << (64 - 54)); threefish_decrypt_512() 3154 tmp = b7 ^ b0; threefish_decrypt_512() 3155 b7 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_512() 3158 tmp = b1 ^ b6; threefish_decrypt_512() 3159 b1 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_512() 3162 tmp = b7 ^ b2; threefish_decrypt_512() 3163 b7 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 3166 tmp = b5 ^ b0; threefish_decrypt_512() 3167 b5 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 3170 tmp = b3 ^ b6; threefish_decrypt_512() 3171 b3 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_512() 3174 tmp = b1 ^ b4; threefish_decrypt_512() 3175 b1 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 3178 tmp = b3 ^ b0; threefish_decrypt_512() 3179 b3 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_512() 3182 tmp = b5 ^ b6; threefish_decrypt_512() 3183 b5 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_512() 3186 tmp = b7 ^ b4; threefish_decrypt_512() 3187 b7 = (tmp >> 27) | (tmp << (64 - 27)); threefish_decrypt_512() 3190 tmp = b1 ^ b2; threefish_decrypt_512() 3191 b1 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_512() 3194 tmp = b7 ^ b6; threefish_decrypt_512() 3195 b7 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_512() 3199 tmp = b5 ^ b4; threefish_decrypt_512() 3200 b5 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_512() 3204 tmp = b3 ^ b2; threefish_decrypt_512() 3205 b3 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 3209 tmp = b1 ^ b0; threefish_decrypt_512() 3210 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_512() 3214 tmp = b3 ^ b4; threefish_decrypt_512() 3215 b3 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_512() 3218 tmp = b5 ^ b2; threefish_decrypt_512() 3219 b5 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 3222 tmp = b7 ^ b0; threefish_decrypt_512() 3223 b7 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_512() 3226 tmp = b1 ^ b6; threefish_decrypt_512() 3227 b1 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_512() 3230 tmp = b7 ^ b2; threefish_decrypt_512() 3231 b7 = (tmp >> 43) | (tmp << (64 - 43)); threefish_decrypt_512() 3234 tmp = b5 ^ b0; threefish_decrypt_512() 3235 b5 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 3238 tmp = b3 ^ b6; threefish_decrypt_512() 3239 b3 = (tmp >> 29) | (tmp << (64 - 29)); threefish_decrypt_512() 3242 tmp = b1 ^ b4; threefish_decrypt_512() 3243 b1 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_512() 3246 tmp = b3 ^ b0; threefish_decrypt_512() 3247 b3 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 3250 tmp = b5 ^ b6; threefish_decrypt_512() 3251 b5 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_512() 3254 tmp = b7 ^ b4; threefish_decrypt_512() 3255 b7 = (tmp >> 50) | (tmp << (64 - 50)); threefish_decrypt_512() 3258 tmp = b1 ^ b2; threefish_decrypt_512() 3259 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_512() 3262 tmp = b7 ^ b6; threefish_decrypt_512() 3263 b7 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_512() 3267 tmp = b5 ^ b4; threefish_decrypt_512() 3268 b5 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_512() 3272 tmp = b3 ^ b2; threefish_decrypt_512() 3273 b3 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_512() 3277 tmp = b1 ^ b0; threefish_decrypt_512() 3278 b1 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 3282 tmp = b3 ^ b4; threefish_decrypt_512() 3283 b3 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_512() 3286 tmp = b5 ^ b2; threefish_decrypt_512() 3287 b5 = (tmp >> 54) | (tmp << (64 - 54)); threefish_decrypt_512() 3290 tmp = b7 ^ b0; threefish_decrypt_512() 3291 b7 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_512() 3294 tmp = b1 ^ b6; threefish_decrypt_512() 3295 b1 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_512() 3298 tmp = b7 ^ b2; threefish_decrypt_512() 3299 b7 = (tmp >> 39) | (tmp << (64 - 39)); threefish_decrypt_512() 3302 tmp = b5 ^ b0; threefish_decrypt_512() 3303 b5 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 3306 tmp = b3 ^ b6; threefish_decrypt_512() 3307 b3 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_512() 3310 tmp = b1 ^ b4; threefish_decrypt_512() 3311 b1 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_512() 3314 tmp = b3 ^ b0; threefish_decrypt_512() 3315 b3 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_512() 3318 tmp = b5 ^ b6; threefish_decrypt_512() 3319 b5 = (tmp >> 14) | (tmp << (64 - 14)); threefish_decrypt_512() 3322 tmp = b7 ^ b4; threefish_decrypt_512() 3323 b7 = (tmp >> 27) | (tmp << (64 - 27)); threefish_decrypt_512() 3326 tmp = b1 ^ b2; threefish_decrypt_512() 3327 b1 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_512() 3330 tmp = b7 ^ b6; threefish_decrypt_512() 3331 b7 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_512() 3335 tmp = b5 ^ b4; threefish_decrypt_512() 3336 b5 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_512() 3340 tmp = b3 ^ b2; threefish_decrypt_512() 3341 b3 = (tmp >> 36) | (tmp << (64 - 36)); threefish_decrypt_512() 3345 tmp = b1 ^ b0; threefish_decrypt_512() 3346 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_512() 5504 u64 tmp; threefish_decrypt_1024() local 5522 tmp = b7 ^ b12; threefish_decrypt_1024() 5523 b7 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 5526 tmp = b3 ^ b10; threefish_decrypt_1024() 5527 b3 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 5530 tmp = b5 ^ b8; threefish_decrypt_1024() 5531 b5 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 5534 tmp = b1 ^ b14; threefish_decrypt_1024() 5535 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 5538 tmp = b9 ^ b4; threefish_decrypt_1024() 5539 b9 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 5542 tmp = b13 ^ b6; threefish_decrypt_1024() 5543 b13 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_1024() 5546 tmp = b11 ^ b2; threefish_decrypt_1024() 5547 b11 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 5550 tmp = b15 ^ b0; threefish_decrypt_1024() 5551 b15 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 5554 tmp = b9 ^ b10; threefish_decrypt_1024() 5555 b9 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 5558 tmp = b11 ^ b8; threefish_decrypt_1024() 5559 b11 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 5562 tmp = b13 ^ b14; threefish_decrypt_1024() 5563 b13 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 5566 tmp = b15 ^ b12; threefish_decrypt_1024() 5567 b15 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 5570 tmp = b1 ^ b6; threefish_decrypt_1024() 5571 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_1024() 5574 tmp = b3 ^ b4; threefish_decrypt_1024() 5575 b3 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 5578 tmp = b5 ^ b2; threefish_decrypt_1024() 5579 b5 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 5582 tmp = b7 ^ b0; threefish_decrypt_1024() 5583 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 5586 tmp = b1 ^ b8; threefish_decrypt_1024() 5587 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 5590 tmp = b5 ^ b14; threefish_decrypt_1024() 5591 b5 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 5594 tmp = b3 ^ b12; threefish_decrypt_1024() 5595 b3 = (tmp >> 53) | (tmp << (64 - 53)); threefish_decrypt_1024() 5598 tmp = b7 ^ b10; threefish_decrypt_1024() 5599 b7 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 5602 tmp = b15 ^ b4; threefish_decrypt_1024() 5603 b15 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 5606 tmp = b11 ^ b6; threefish_decrypt_1024() 5607 b11 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_1024() 5610 tmp = b13 ^ b2; threefish_decrypt_1024() 5611 b13 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 5614 tmp = b9 ^ b0; threefish_decrypt_1024() 5615 b9 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 5618 tmp = b15 ^ b14; threefish_decrypt_1024() 5619 b15 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_1024() 5623 tmp = b13 ^ b12; threefish_decrypt_1024() 5624 b13 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 5628 tmp = b11 ^ b10; threefish_decrypt_1024() 5629 b11 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 5633 tmp = b9 ^ b8; threefish_decrypt_1024() 5634 b9 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_1024() 5638 tmp = b7 ^ b6; threefish_decrypt_1024() 5639 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 5643 tmp = b5 ^ b4; threefish_decrypt_1024() 5644 b5 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 5648 tmp = b3 ^ b2; threefish_decrypt_1024() 5649 b3 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 5653 tmp = b1 ^ b0; threefish_decrypt_1024() 5654 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 5658 tmp = b7 ^ b12; threefish_decrypt_1024() 5659 b7 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 5662 tmp = b3 ^ b10; threefish_decrypt_1024() 5663 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 5666 tmp = b5 ^ b8; threefish_decrypt_1024() 5667 b5 = (tmp >> 28) | (tmp << (64 - 28)); threefish_decrypt_1024() 5670 tmp = b1 ^ b14; threefish_decrypt_1024() 5671 b1 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 5674 tmp = b9 ^ b4; threefish_decrypt_1024() 5675 b9 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 5678 tmp = b13 ^ b6; threefish_decrypt_1024() 5679 b13 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 5682 tmp = b11 ^ b2; threefish_decrypt_1024() 5683 b11 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 5686 tmp = b15 ^ b0; threefish_decrypt_1024() 5687 b15 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_1024() 5690 tmp = b9 ^ b10; threefish_decrypt_1024() 5691 b9 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 5694 tmp = b11 ^ b8; threefish_decrypt_1024() 5695 b11 = (tmp >> 59) | (tmp << (64 - 59)); threefish_decrypt_1024() 5698 tmp = b13 ^ b14; threefish_decrypt_1024() 5699 b13 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 5702 tmp = b15 ^ b12; threefish_decrypt_1024() 5703 b15 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 5706 tmp = b1 ^ b6; threefish_decrypt_1024() 5707 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 5710 tmp = b3 ^ b4; threefish_decrypt_1024() 5711 b3 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 5714 tmp = b5 ^ b2; threefish_decrypt_1024() 5715 b5 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 5718 tmp = b7 ^ b0; threefish_decrypt_1024() 5719 b7 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_1024() 5722 tmp = b1 ^ b8; threefish_decrypt_1024() 5723 b1 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 5726 tmp = b5 ^ b14; threefish_decrypt_1024() 5727 b5 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 5730 tmp = b3 ^ b12; threefish_decrypt_1024() 5731 b3 = (tmp >> 18) | (tmp << (64 - 18)); threefish_decrypt_1024() 5734 tmp = b7 ^ b10; threefish_decrypt_1024() 5735 b7 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_1024() 5738 tmp = b15 ^ b4; threefish_decrypt_1024() 5739 b15 = (tmp >> 55) | (tmp << (64 - 55)); threefish_decrypt_1024() 5742 tmp = b11 ^ b6; threefish_decrypt_1024() 5743 b11 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_1024() 5746 tmp = b13 ^ b2; threefish_decrypt_1024() 5747 b13 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 5750 tmp = b9 ^ b0; threefish_decrypt_1024() 5751 b9 = (tmp >> 38) | (tmp << (64 - 38)); threefish_decrypt_1024() 5754 tmp = b15 ^ b14; threefish_decrypt_1024() 5755 b15 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 5759 tmp = b13 ^ b12; threefish_decrypt_1024() 5760 b13 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_1024() 5764 tmp = b11 ^ b10; threefish_decrypt_1024() 5765 b11 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 5769 tmp = b9 ^ b8; threefish_decrypt_1024() 5770 b9 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 5774 tmp = b7 ^ b6; threefish_decrypt_1024() 5775 b7 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 5779 tmp = b5 ^ b4; threefish_decrypt_1024() 5780 b5 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 5784 tmp = b3 ^ b2; threefish_decrypt_1024() 5785 b3 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 5789 tmp = b1 ^ b0; threefish_decrypt_1024() 5790 b1 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_1024() 5794 tmp = b7 ^ b12; threefish_decrypt_1024() 5795 b7 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 5798 tmp = b3 ^ b10; threefish_decrypt_1024() 5799 b3 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 5802 tmp = b5 ^ b8; threefish_decrypt_1024() 5803 b5 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 5806 tmp = b1 ^ b14; threefish_decrypt_1024() 5807 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 5810 tmp = b9 ^ b4; threefish_decrypt_1024() 5811 b9 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 5814 tmp = b13 ^ b6; threefish_decrypt_1024() 5815 b13 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_1024() 5818 tmp = b11 ^ b2; threefish_decrypt_1024() 5819 b11 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 5822 tmp = b15 ^ b0; threefish_decrypt_1024() 5823 b15 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 5826 tmp = b9 ^ b10; threefish_decrypt_1024() 5827 b9 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 5830 tmp = b11 ^ b8; threefish_decrypt_1024() 5831 b11 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 5834 tmp = b13 ^ b14; threefish_decrypt_1024() 5835 b13 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 5838 tmp = b15 ^ b12; threefish_decrypt_1024() 5839 b15 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 5842 tmp = b1 ^ b6; threefish_decrypt_1024() 5843 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_1024() 5846 tmp = b3 ^ b4; threefish_decrypt_1024() 5847 b3 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 5850 tmp = b5 ^ b2; threefish_decrypt_1024() 5851 b5 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 5854 tmp = b7 ^ b0; threefish_decrypt_1024() 5855 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 5858 tmp = b1 ^ b8; threefish_decrypt_1024() 5859 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 5862 tmp = b5 ^ b14; threefish_decrypt_1024() 5863 b5 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 5866 tmp = b3 ^ b12; threefish_decrypt_1024() 5867 b3 = (tmp >> 53) | (tmp << (64 - 53)); threefish_decrypt_1024() 5870 tmp = b7 ^ b10; threefish_decrypt_1024() 5871 b7 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 5874 tmp = b15 ^ b4; threefish_decrypt_1024() 5875 b15 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 5878 tmp = b11 ^ b6; threefish_decrypt_1024() 5879 b11 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_1024() 5882 tmp = b13 ^ b2; threefish_decrypt_1024() 5883 b13 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 5886 tmp = b9 ^ b0; threefish_decrypt_1024() 5887 b9 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 5890 tmp = b15 ^ b14; threefish_decrypt_1024() 5891 b15 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_1024() 5895 tmp = b13 ^ b12; threefish_decrypt_1024() 5896 b13 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 5900 tmp = b11 ^ b10; threefish_decrypt_1024() 5901 b11 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 5905 tmp = b9 ^ b8; threefish_decrypt_1024() 5906 b9 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_1024() 5910 tmp = b7 ^ b6; threefish_decrypt_1024() 5911 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 5915 tmp = b5 ^ b4; threefish_decrypt_1024() 5916 b5 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 5920 tmp = b3 ^ b2; threefish_decrypt_1024() 5921 b3 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 5925 tmp = b1 ^ b0; threefish_decrypt_1024() 5926 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 5930 tmp = b7 ^ b12; threefish_decrypt_1024() 5931 b7 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 5934 tmp = b3 ^ b10; threefish_decrypt_1024() 5935 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 5938 tmp = b5 ^ b8; threefish_decrypt_1024() 5939 b5 = (tmp >> 28) | (tmp << (64 - 28)); threefish_decrypt_1024() 5942 tmp = b1 ^ b14; threefish_decrypt_1024() 5943 b1 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 5946 tmp = b9 ^ b4; threefish_decrypt_1024() 5947 b9 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 5950 tmp = b13 ^ b6; threefish_decrypt_1024() 5951 b13 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 5954 tmp = b11 ^ b2; threefish_decrypt_1024() 5955 b11 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 5958 tmp = b15 ^ b0; threefish_decrypt_1024() 5959 b15 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_1024() 5962 tmp = b9 ^ b10; threefish_decrypt_1024() 5963 b9 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 5966 tmp = b11 ^ b8; threefish_decrypt_1024() 5967 b11 = (tmp >> 59) | (tmp << (64 - 59)); threefish_decrypt_1024() 5970 tmp = b13 ^ b14; threefish_decrypt_1024() 5971 b13 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 5974 tmp = b15 ^ b12; threefish_decrypt_1024() 5975 b15 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 5978 tmp = b1 ^ b6; threefish_decrypt_1024() 5979 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 5982 tmp = b3 ^ b4; threefish_decrypt_1024() 5983 b3 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 5986 tmp = b5 ^ b2; threefish_decrypt_1024() 5987 b5 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 5990 tmp = b7 ^ b0; threefish_decrypt_1024() 5991 b7 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_1024() 5994 tmp = b1 ^ b8; threefish_decrypt_1024() 5995 b1 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 5998 tmp = b5 ^ b14; threefish_decrypt_1024() 5999 b5 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 6002 tmp = b3 ^ b12; threefish_decrypt_1024() 6003 b3 = (tmp >> 18) | (tmp << (64 - 18)); threefish_decrypt_1024() 6006 tmp = b7 ^ b10; threefish_decrypt_1024() 6007 b7 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_1024() 6010 tmp = b15 ^ b4; threefish_decrypt_1024() 6011 b15 = (tmp >> 55) | (tmp << (64 - 55)); threefish_decrypt_1024() 6014 tmp = b11 ^ b6; threefish_decrypt_1024() 6015 b11 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_1024() 6018 tmp = b13 ^ b2; threefish_decrypt_1024() 6019 b13 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 6022 tmp = b9 ^ b0; threefish_decrypt_1024() 6023 b9 = (tmp >> 38) | (tmp << (64 - 38)); threefish_decrypt_1024() 6026 tmp = b15 ^ b14; threefish_decrypt_1024() 6027 b15 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 6031 tmp = b13 ^ b12; threefish_decrypt_1024() 6032 b13 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_1024() 6036 tmp = b11 ^ b10; threefish_decrypt_1024() 6037 b11 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 6041 tmp = b9 ^ b8; threefish_decrypt_1024() 6042 b9 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 6046 tmp = b7 ^ b6; threefish_decrypt_1024() 6047 b7 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 6051 tmp = b5 ^ b4; threefish_decrypt_1024() 6052 b5 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 6056 tmp = b3 ^ b2; threefish_decrypt_1024() 6057 b3 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 6061 tmp = b1 ^ b0; threefish_decrypt_1024() 6062 b1 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_1024() 6066 tmp = b7 ^ b12; threefish_decrypt_1024() 6067 b7 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 6070 tmp = b3 ^ b10; threefish_decrypt_1024() 6071 b3 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 6074 tmp = b5 ^ b8; threefish_decrypt_1024() 6075 b5 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 6078 tmp = b1 ^ b14; threefish_decrypt_1024() 6079 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 6082 tmp = b9 ^ b4; threefish_decrypt_1024() 6083 b9 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 6086 tmp = b13 ^ b6; threefish_decrypt_1024() 6087 b13 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_1024() 6090 tmp = b11 ^ b2; threefish_decrypt_1024() 6091 b11 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 6094 tmp = b15 ^ b0; threefish_decrypt_1024() 6095 b15 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 6098 tmp = b9 ^ b10; threefish_decrypt_1024() 6099 b9 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 6102 tmp = b11 ^ b8; threefish_decrypt_1024() 6103 b11 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 6106 tmp = b13 ^ b14; threefish_decrypt_1024() 6107 b13 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 6110 tmp = b15 ^ b12; threefish_decrypt_1024() 6111 b15 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 6114 tmp = b1 ^ b6; threefish_decrypt_1024() 6115 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_1024() 6118 tmp = b3 ^ b4; threefish_decrypt_1024() 6119 b3 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 6122 tmp = b5 ^ b2; threefish_decrypt_1024() 6123 b5 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 6126 tmp = b7 ^ b0; threefish_decrypt_1024() 6127 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 6130 tmp = b1 ^ b8; threefish_decrypt_1024() 6131 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 6134 tmp = b5 ^ b14; threefish_decrypt_1024() 6135 b5 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 6138 tmp = b3 ^ b12; threefish_decrypt_1024() 6139 b3 = (tmp >> 53) | (tmp << (64 - 53)); threefish_decrypt_1024() 6142 tmp = b7 ^ b10; threefish_decrypt_1024() 6143 b7 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 6146 tmp = b15 ^ b4; threefish_decrypt_1024() 6147 b15 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 6150 tmp = b11 ^ b6; threefish_decrypt_1024() 6151 b11 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_1024() 6154 tmp = b13 ^ b2; threefish_decrypt_1024() 6155 b13 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 6158 tmp = b9 ^ b0; threefish_decrypt_1024() 6159 b9 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 6162 tmp = b15 ^ b14; threefish_decrypt_1024() 6163 b15 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_1024() 6167 tmp = b13 ^ b12; threefish_decrypt_1024() 6168 b13 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 6172 tmp = b11 ^ b10; threefish_decrypt_1024() 6173 b11 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 6177 tmp = b9 ^ b8; threefish_decrypt_1024() 6178 b9 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_1024() 6182 tmp = b7 ^ b6; threefish_decrypt_1024() 6183 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 6187 tmp = b5 ^ b4; threefish_decrypt_1024() 6188 b5 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 6192 tmp = b3 ^ b2; threefish_decrypt_1024() 6193 b3 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 6197 tmp = b1 ^ b0; threefish_decrypt_1024() 6198 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 6202 tmp = b7 ^ b12; threefish_decrypt_1024() 6203 b7 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 6206 tmp = b3 ^ b10; threefish_decrypt_1024() 6207 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 6210 tmp = b5 ^ b8; threefish_decrypt_1024() 6211 b5 = (tmp >> 28) | (tmp << (64 - 28)); threefish_decrypt_1024() 6214 tmp = b1 ^ b14; threefish_decrypt_1024() 6215 b1 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 6218 tmp = b9 ^ b4; threefish_decrypt_1024() 6219 b9 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 6222 tmp = b13 ^ b6; threefish_decrypt_1024() 6223 b13 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 6226 tmp = b11 ^ b2; threefish_decrypt_1024() 6227 b11 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 6230 tmp = b15 ^ b0; threefish_decrypt_1024() 6231 b15 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_1024() 6234 tmp = b9 ^ b10; threefish_decrypt_1024() 6235 b9 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 6238 tmp = b11 ^ b8; threefish_decrypt_1024() 6239 b11 = (tmp >> 59) | (tmp << (64 - 59)); threefish_decrypt_1024() 6242 tmp = b13 ^ b14; threefish_decrypt_1024() 6243 b13 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 6246 tmp = b15 ^ b12; threefish_decrypt_1024() 6247 b15 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 6250 tmp = b1 ^ b6; threefish_decrypt_1024() 6251 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 6254 tmp = b3 ^ b4; threefish_decrypt_1024() 6255 b3 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 6258 tmp = b5 ^ b2; threefish_decrypt_1024() 6259 b5 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 6262 tmp = b7 ^ b0; threefish_decrypt_1024() 6263 b7 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_1024() 6266 tmp = b1 ^ b8; threefish_decrypt_1024() 6267 b1 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 6270 tmp = b5 ^ b14; threefish_decrypt_1024() 6271 b5 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 6274 tmp = b3 ^ b12; threefish_decrypt_1024() 6275 b3 = (tmp >> 18) | (tmp << (64 - 18)); threefish_decrypt_1024() 6278 tmp = b7 ^ b10; threefish_decrypt_1024() 6279 b7 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_1024() 6282 tmp = b15 ^ b4; threefish_decrypt_1024() 6283 b15 = (tmp >> 55) | (tmp << (64 - 55)); threefish_decrypt_1024() 6286 tmp = b11 ^ b6; threefish_decrypt_1024() 6287 b11 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_1024() 6290 tmp = b13 ^ b2; threefish_decrypt_1024() 6291 b13 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 6294 tmp = b9 ^ b0; threefish_decrypt_1024() 6295 b9 = (tmp >> 38) | (tmp << (64 - 38)); threefish_decrypt_1024() 6298 tmp = b15 ^ b14; threefish_decrypt_1024() 6299 b15 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 6303 tmp = b13 ^ b12; threefish_decrypt_1024() 6304 b13 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_1024() 6308 tmp = b11 ^ b10; threefish_decrypt_1024() 6309 b11 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 6313 tmp = b9 ^ b8; threefish_decrypt_1024() 6314 b9 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 6318 tmp = b7 ^ b6; threefish_decrypt_1024() 6319 b7 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 6323 tmp = b5 ^ b4; threefish_decrypt_1024() 6324 b5 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 6328 tmp = b3 ^ b2; threefish_decrypt_1024() 6329 b3 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 6333 tmp = b1 ^ b0; threefish_decrypt_1024() 6334 b1 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_1024() 6338 tmp = b7 ^ b12; threefish_decrypt_1024() 6339 b7 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 6342 tmp = b3 ^ b10; threefish_decrypt_1024() 6343 b3 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 6346 tmp = b5 ^ b8; threefish_decrypt_1024() 6347 b5 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 6350 tmp = b1 ^ b14; threefish_decrypt_1024() 6351 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 6354 tmp = b9 ^ b4; threefish_decrypt_1024() 6355 b9 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 6358 tmp = b13 ^ b6; threefish_decrypt_1024() 6359 b13 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_1024() 6362 tmp = b11 ^ b2; threefish_decrypt_1024() 6363 b11 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 6366 tmp = b15 ^ b0; threefish_decrypt_1024() 6367 b15 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 6370 tmp = b9 ^ b10; threefish_decrypt_1024() 6371 b9 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 6374 tmp = b11 ^ b8; threefish_decrypt_1024() 6375 b11 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 6378 tmp = b13 ^ b14; threefish_decrypt_1024() 6379 b13 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 6382 tmp = b15 ^ b12; threefish_decrypt_1024() 6383 b15 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 6386 tmp = b1 ^ b6; threefish_decrypt_1024() 6387 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_1024() 6390 tmp = b3 ^ b4; threefish_decrypt_1024() 6391 b3 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 6394 tmp = b5 ^ b2; threefish_decrypt_1024() 6395 b5 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 6398 tmp = b7 ^ b0; threefish_decrypt_1024() 6399 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 6402 tmp = b1 ^ b8; threefish_decrypt_1024() 6403 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 6406 tmp = b5 ^ b14; threefish_decrypt_1024() 6407 b5 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 6410 tmp = b3 ^ b12; threefish_decrypt_1024() 6411 b3 = (tmp >> 53) | (tmp << (64 - 53)); threefish_decrypt_1024() 6414 tmp = b7 ^ b10; threefish_decrypt_1024() 6415 b7 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 6418 tmp = b15 ^ b4; threefish_decrypt_1024() 6419 b15 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 6422 tmp = b11 ^ b6; threefish_decrypt_1024() 6423 b11 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_1024() 6426 tmp = b13 ^ b2; threefish_decrypt_1024() 6427 b13 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 6430 tmp = b9 ^ b0; threefish_decrypt_1024() 6431 b9 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 6434 tmp = b15 ^ b14; threefish_decrypt_1024() 6435 b15 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_1024() 6439 tmp = b13 ^ b12; threefish_decrypt_1024() 6440 b13 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 6444 tmp = b11 ^ b10; threefish_decrypt_1024() 6445 b11 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 6449 tmp = b9 ^ b8; threefish_decrypt_1024() 6450 b9 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_1024() 6454 tmp = b7 ^ b6; threefish_decrypt_1024() 6455 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 6459 tmp = b5 ^ b4; threefish_decrypt_1024() 6460 b5 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 6464 tmp = b3 ^ b2; threefish_decrypt_1024() 6465 b3 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 6469 tmp = b1 ^ b0; threefish_decrypt_1024() 6470 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 6474 tmp = b7 ^ b12; threefish_decrypt_1024() 6475 b7 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 6478 tmp = b3 ^ b10; threefish_decrypt_1024() 6479 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 6482 tmp = b5 ^ b8; threefish_decrypt_1024() 6483 b5 = (tmp >> 28) | (tmp << (64 - 28)); threefish_decrypt_1024() 6486 tmp = b1 ^ b14; threefish_decrypt_1024() 6487 b1 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 6490 tmp = b9 ^ b4; threefish_decrypt_1024() 6491 b9 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 6494 tmp = b13 ^ b6; threefish_decrypt_1024() 6495 b13 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 6498 tmp = b11 ^ b2; threefish_decrypt_1024() 6499 b11 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 6502 tmp = b15 ^ b0; threefish_decrypt_1024() 6503 b15 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_1024() 6506 tmp = b9 ^ b10; threefish_decrypt_1024() 6507 b9 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 6510 tmp = b11 ^ b8; threefish_decrypt_1024() 6511 b11 = (tmp >> 59) | (tmp << (64 - 59)); threefish_decrypt_1024() 6514 tmp = b13 ^ b14; threefish_decrypt_1024() 6515 b13 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 6518 tmp = b15 ^ b12; threefish_decrypt_1024() 6519 b15 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 6522 tmp = b1 ^ b6; threefish_decrypt_1024() 6523 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 6526 tmp = b3 ^ b4; threefish_decrypt_1024() 6527 b3 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 6530 tmp = b5 ^ b2; threefish_decrypt_1024() 6531 b5 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 6534 tmp = b7 ^ b0; threefish_decrypt_1024() 6535 b7 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_1024() 6538 tmp = b1 ^ b8; threefish_decrypt_1024() 6539 b1 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 6542 tmp = b5 ^ b14; threefish_decrypt_1024() 6543 b5 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 6546 tmp = b3 ^ b12; threefish_decrypt_1024() 6547 b3 = (tmp >> 18) | (tmp << (64 - 18)); threefish_decrypt_1024() 6550 tmp = b7 ^ b10; threefish_decrypt_1024() 6551 b7 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_1024() 6554 tmp = b15 ^ b4; threefish_decrypt_1024() 6555 b15 = (tmp >> 55) | (tmp << (64 - 55)); threefish_decrypt_1024() 6558 tmp = b11 ^ b6; threefish_decrypt_1024() 6559 b11 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_1024() 6562 tmp = b13 ^ b2; threefish_decrypt_1024() 6563 b13 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 6566 tmp = b9 ^ b0; threefish_decrypt_1024() 6567 b9 = (tmp >> 38) | (tmp << (64 - 38)); threefish_decrypt_1024() 6570 tmp = b15 ^ b14; threefish_decrypt_1024() 6571 b15 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 6575 tmp = b13 ^ b12; threefish_decrypt_1024() 6576 b13 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_1024() 6580 tmp = b11 ^ b10; threefish_decrypt_1024() 6581 b11 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 6585 tmp = b9 ^ b8; threefish_decrypt_1024() 6586 b9 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 6590 tmp = b7 ^ b6; threefish_decrypt_1024() 6591 b7 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 6595 tmp = b5 ^ b4; threefish_decrypt_1024() 6596 b5 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 6600 tmp = b3 ^ b2; threefish_decrypt_1024() 6601 b3 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 6605 tmp = b1 ^ b0; threefish_decrypt_1024() 6606 b1 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_1024() 6610 tmp = b7 ^ b12; threefish_decrypt_1024() 6611 b7 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 6614 tmp = b3 ^ b10; threefish_decrypt_1024() 6615 b3 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 6618 tmp = b5 ^ b8; threefish_decrypt_1024() 6619 b5 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 6622 tmp = b1 ^ b14; threefish_decrypt_1024() 6623 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 6626 tmp = b9 ^ b4; threefish_decrypt_1024() 6627 b9 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 6630 tmp = b13 ^ b6; threefish_decrypt_1024() 6631 b13 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_1024() 6634 tmp = b11 ^ b2; threefish_decrypt_1024() 6635 b11 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 6638 tmp = b15 ^ b0; threefish_decrypt_1024() 6639 b15 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 6642 tmp = b9 ^ b10; threefish_decrypt_1024() 6643 b9 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 6646 tmp = b11 ^ b8; threefish_decrypt_1024() 6647 b11 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 6650 tmp = b13 ^ b14; threefish_decrypt_1024() 6651 b13 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 6654 tmp = b15 ^ b12; threefish_decrypt_1024() 6655 b15 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 6658 tmp = b1 ^ b6; threefish_decrypt_1024() 6659 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_1024() 6662 tmp = b3 ^ b4; threefish_decrypt_1024() 6663 b3 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 6666 tmp = b5 ^ b2; threefish_decrypt_1024() 6667 b5 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 6670 tmp = b7 ^ b0; threefish_decrypt_1024() 6671 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 6674 tmp = b1 ^ b8; threefish_decrypt_1024() 6675 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 6678 tmp = b5 ^ b14; threefish_decrypt_1024() 6679 b5 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 6682 tmp = b3 ^ b12; threefish_decrypt_1024() 6683 b3 = (tmp >> 53) | (tmp << (64 - 53)); threefish_decrypt_1024() 6686 tmp = b7 ^ b10; threefish_decrypt_1024() 6687 b7 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 6690 tmp = b15 ^ b4; threefish_decrypt_1024() 6691 b15 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 6694 tmp = b11 ^ b6; threefish_decrypt_1024() 6695 b11 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_1024() 6698 tmp = b13 ^ b2; threefish_decrypt_1024() 6699 b13 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 6702 tmp = b9 ^ b0; threefish_decrypt_1024() 6703 b9 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 6706 tmp = b15 ^ b14; threefish_decrypt_1024() 6707 b15 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_1024() 6711 tmp = b13 ^ b12; threefish_decrypt_1024() 6712 b13 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 6716 tmp = b11 ^ b10; threefish_decrypt_1024() 6717 b11 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 6721 tmp = b9 ^ b8; threefish_decrypt_1024() 6722 b9 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_1024() 6726 tmp = b7 ^ b6; threefish_decrypt_1024() 6727 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 6731 tmp = b5 ^ b4; threefish_decrypt_1024() 6732 b5 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 6736 tmp = b3 ^ b2; threefish_decrypt_1024() 6737 b3 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 6741 tmp = b1 ^ b0; threefish_decrypt_1024() 6742 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 6746 tmp = b7 ^ b12; threefish_decrypt_1024() 6747 b7 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 6750 tmp = b3 ^ b10; threefish_decrypt_1024() 6751 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 6754 tmp = b5 ^ b8; threefish_decrypt_1024() 6755 b5 = (tmp >> 28) | (tmp << (64 - 28)); threefish_decrypt_1024() 6758 tmp = b1 ^ b14; threefish_decrypt_1024() 6759 b1 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 6762 tmp = b9 ^ b4; threefish_decrypt_1024() 6763 b9 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 6766 tmp = b13 ^ b6; threefish_decrypt_1024() 6767 b13 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 6770 tmp = b11 ^ b2; threefish_decrypt_1024() 6771 b11 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 6774 tmp = b15 ^ b0; threefish_decrypt_1024() 6775 b15 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_1024() 6778 tmp = b9 ^ b10; threefish_decrypt_1024() 6779 b9 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 6782 tmp = b11 ^ b8; threefish_decrypt_1024() 6783 b11 = (tmp >> 59) | (tmp << (64 - 59)); threefish_decrypt_1024() 6786 tmp = b13 ^ b14; threefish_decrypt_1024() 6787 b13 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 6790 tmp = b15 ^ b12; threefish_decrypt_1024() 6791 b15 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 6794 tmp = b1 ^ b6; threefish_decrypt_1024() 6795 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 6798 tmp = b3 ^ b4; threefish_decrypt_1024() 6799 b3 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 6802 tmp = b5 ^ b2; threefish_decrypt_1024() 6803 b5 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 6806 tmp = b7 ^ b0; threefish_decrypt_1024() 6807 b7 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_1024() 6810 tmp = b1 ^ b8; threefish_decrypt_1024() 6811 b1 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 6814 tmp = b5 ^ b14; threefish_decrypt_1024() 6815 b5 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 6818 tmp = b3 ^ b12; threefish_decrypt_1024() 6819 b3 = (tmp >> 18) | (tmp << (64 - 18)); threefish_decrypt_1024() 6822 tmp = b7 ^ b10; threefish_decrypt_1024() 6823 b7 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_1024() 6826 tmp = b15 ^ b4; threefish_decrypt_1024() 6827 b15 = (tmp >> 55) | (tmp << (64 - 55)); threefish_decrypt_1024() 6830 tmp = b11 ^ b6; threefish_decrypt_1024() 6831 b11 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_1024() 6834 tmp = b13 ^ b2; threefish_decrypt_1024() 6835 b13 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 6838 tmp = b9 ^ b0; threefish_decrypt_1024() 6839 b9 = (tmp >> 38) | (tmp << (64 - 38)); threefish_decrypt_1024() 6842 tmp = b15 ^ b14; threefish_decrypt_1024() 6843 b15 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 6847 tmp = b13 ^ b12; threefish_decrypt_1024() 6848 b13 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_1024() 6852 tmp = b11 ^ b10; threefish_decrypt_1024() 6853 b11 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 6857 tmp = b9 ^ b8; threefish_decrypt_1024() 6858 b9 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 6862 tmp = b7 ^ b6; threefish_decrypt_1024() 6863 b7 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 6867 tmp = b5 ^ b4; threefish_decrypt_1024() 6868 b5 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 6872 tmp = b3 ^ b2; threefish_decrypt_1024() 6873 b3 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 6877 tmp = b1 ^ b0; threefish_decrypt_1024() 6878 b1 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_1024() 6882 tmp = b7 ^ b12; threefish_decrypt_1024() 6883 b7 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 6886 tmp = b3 ^ b10; threefish_decrypt_1024() 6887 b3 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 6890 tmp = b5 ^ b8; threefish_decrypt_1024() 6891 b5 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 6894 tmp = b1 ^ b14; threefish_decrypt_1024() 6895 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 6898 tmp = b9 ^ b4; threefish_decrypt_1024() 6899 b9 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 6902 tmp = b13 ^ b6; threefish_decrypt_1024() 6903 b13 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_1024() 6906 tmp = b11 ^ b2; threefish_decrypt_1024() 6907 b11 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 6910 tmp = b15 ^ b0; threefish_decrypt_1024() 6911 b15 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 6914 tmp = b9 ^ b10; threefish_decrypt_1024() 6915 b9 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 6918 tmp = b11 ^ b8; threefish_decrypt_1024() 6919 b11 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 6922 tmp = b13 ^ b14; threefish_decrypt_1024() 6923 b13 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 6926 tmp = b15 ^ b12; threefish_decrypt_1024() 6927 b15 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 6930 tmp = b1 ^ b6; threefish_decrypt_1024() 6931 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_1024() 6934 tmp = b3 ^ b4; threefish_decrypt_1024() 6935 b3 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 6938 tmp = b5 ^ b2; threefish_decrypt_1024() 6939 b5 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 6942 tmp = b7 ^ b0; threefish_decrypt_1024() 6943 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 6946 tmp = b1 ^ b8; threefish_decrypt_1024() 6947 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 6950 tmp = b5 ^ b14; threefish_decrypt_1024() 6951 b5 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 6954 tmp = b3 ^ b12; threefish_decrypt_1024() 6955 b3 = (tmp >> 53) | (tmp << (64 - 53)); threefish_decrypt_1024() 6958 tmp = b7 ^ b10; threefish_decrypt_1024() 6959 b7 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 6962 tmp = b15 ^ b4; threefish_decrypt_1024() 6963 b15 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 6966 tmp = b11 ^ b6; threefish_decrypt_1024() 6967 b11 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_1024() 6970 tmp = b13 ^ b2; threefish_decrypt_1024() 6971 b13 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 6974 tmp = b9 ^ b0; threefish_decrypt_1024() 6975 b9 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 6978 tmp = b15 ^ b14; threefish_decrypt_1024() 6979 b15 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_1024() 6983 tmp = b13 ^ b12; threefish_decrypt_1024() 6984 b13 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 6988 tmp = b11 ^ b10; threefish_decrypt_1024() 6989 b11 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 6993 tmp = b9 ^ b8; threefish_decrypt_1024() 6994 b9 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_1024() 6998 tmp = b7 ^ b6; threefish_decrypt_1024() 6999 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 7003 tmp = b5 ^ b4; threefish_decrypt_1024() 7004 b5 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 7008 tmp = b3 ^ b2; threefish_decrypt_1024() 7009 b3 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 7013 tmp = b1 ^ b0; threefish_decrypt_1024() 7014 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 7018 tmp = b7 ^ b12; threefish_decrypt_1024() 7019 b7 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 7022 tmp = b3 ^ b10; threefish_decrypt_1024() 7023 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 7026 tmp = b5 ^ b8; threefish_decrypt_1024() 7027 b5 = (tmp >> 28) | (tmp << (64 - 28)); threefish_decrypt_1024() 7030 tmp = b1 ^ b14; threefish_decrypt_1024() 7031 b1 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 7034 tmp = b9 ^ b4; threefish_decrypt_1024() 7035 b9 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 7038 tmp = b13 ^ b6; threefish_decrypt_1024() 7039 b13 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 7042 tmp = b11 ^ b2; threefish_decrypt_1024() 7043 b11 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 7046 tmp = b15 ^ b0; threefish_decrypt_1024() 7047 b15 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_1024() 7050 tmp = b9 ^ b10; threefish_decrypt_1024() 7051 b9 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 7054 tmp = b11 ^ b8; threefish_decrypt_1024() 7055 b11 = (tmp >> 59) | (tmp << (64 - 59)); threefish_decrypt_1024() 7058 tmp = b13 ^ b14; threefish_decrypt_1024() 7059 b13 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 7062 tmp = b15 ^ b12; threefish_decrypt_1024() 7063 b15 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 7066 tmp = b1 ^ b6; threefish_decrypt_1024() 7067 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 7070 tmp = b3 ^ b4; threefish_decrypt_1024() 7071 b3 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 7074 tmp = b5 ^ b2; threefish_decrypt_1024() 7075 b5 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 7078 tmp = b7 ^ b0; threefish_decrypt_1024() 7079 b7 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_1024() 7082 tmp = b1 ^ b8; threefish_decrypt_1024() 7083 b1 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 7086 tmp = b5 ^ b14; threefish_decrypt_1024() 7087 b5 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 7090 tmp = b3 ^ b12; threefish_decrypt_1024() 7091 b3 = (tmp >> 18) | (tmp << (64 - 18)); threefish_decrypt_1024() 7094 tmp = b7 ^ b10; threefish_decrypt_1024() 7095 b7 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_1024() 7098 tmp = b15 ^ b4; threefish_decrypt_1024() 7099 b15 = (tmp >> 55) | (tmp << (64 - 55)); threefish_decrypt_1024() 7102 tmp = b11 ^ b6; threefish_decrypt_1024() 7103 b11 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_1024() 7106 tmp = b13 ^ b2; threefish_decrypt_1024() 7107 b13 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 7110 tmp = b9 ^ b0; threefish_decrypt_1024() 7111 b9 = (tmp >> 38) | (tmp << (64 - 38)); threefish_decrypt_1024() 7114 tmp = b15 ^ b14; threefish_decrypt_1024() 7115 b15 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 7119 tmp = b13 ^ b12; threefish_decrypt_1024() 7120 b13 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_1024() 7124 tmp = b11 ^ b10; threefish_decrypt_1024() 7125 b11 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 7129 tmp = b9 ^ b8; threefish_decrypt_1024() 7130 b9 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 7134 tmp = b7 ^ b6; threefish_decrypt_1024() 7135 b7 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 7139 tmp = b5 ^ b4; threefish_decrypt_1024() 7140 b5 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 7144 tmp = b3 ^ b2; threefish_decrypt_1024() 7145 b3 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 7149 tmp = b1 ^ b0; threefish_decrypt_1024() 7150 b1 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_1024() 7154 tmp = b7 ^ b12; threefish_decrypt_1024() 7155 b7 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 7158 tmp = b3 ^ b10; threefish_decrypt_1024() 7159 b3 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 7162 tmp = b5 ^ b8; threefish_decrypt_1024() 7163 b5 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 7166 tmp = b1 ^ b14; threefish_decrypt_1024() 7167 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 7170 tmp = b9 ^ b4; threefish_decrypt_1024() 7171 b9 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 7174 tmp = b13 ^ b6; threefish_decrypt_1024() 7175 b13 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_1024() 7178 tmp = b11 ^ b2; threefish_decrypt_1024() 7179 b11 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 7182 tmp = b15 ^ b0; threefish_decrypt_1024() 7183 b15 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 7186 tmp = b9 ^ b10; threefish_decrypt_1024() 7187 b9 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 7190 tmp = b11 ^ b8; threefish_decrypt_1024() 7191 b11 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 7194 tmp = b13 ^ b14; threefish_decrypt_1024() 7195 b13 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 7198 tmp = b15 ^ b12; threefish_decrypt_1024() 7199 b15 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 7202 tmp = b1 ^ b6; threefish_decrypt_1024() 7203 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_1024() 7206 tmp = b3 ^ b4; threefish_decrypt_1024() 7207 b3 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 7210 tmp = b5 ^ b2; threefish_decrypt_1024() 7211 b5 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 7214 tmp = b7 ^ b0; threefish_decrypt_1024() 7215 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 7218 tmp = b1 ^ b8; threefish_decrypt_1024() 7219 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 7222 tmp = b5 ^ b14; threefish_decrypt_1024() 7223 b5 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 7226 tmp = b3 ^ b12; threefish_decrypt_1024() 7227 b3 = (tmp >> 53) | (tmp << (64 - 53)); threefish_decrypt_1024() 7230 tmp = b7 ^ b10; threefish_decrypt_1024() 7231 b7 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 7234 tmp = b15 ^ b4; threefish_decrypt_1024() 7235 b15 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 7238 tmp = b11 ^ b6; threefish_decrypt_1024() 7239 b11 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_1024() 7242 tmp = b13 ^ b2; threefish_decrypt_1024() 7243 b13 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 7246 tmp = b9 ^ b0; threefish_decrypt_1024() 7247 b9 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 7250 tmp = b15 ^ b14; threefish_decrypt_1024() 7251 b15 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_1024() 7255 tmp = b13 ^ b12; threefish_decrypt_1024() 7256 b13 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 7260 tmp = b11 ^ b10; threefish_decrypt_1024() 7261 b11 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 7265 tmp = b9 ^ b8; threefish_decrypt_1024() 7266 b9 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_1024() 7270 tmp = b7 ^ b6; threefish_decrypt_1024() 7271 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 7275 tmp = b5 ^ b4; threefish_decrypt_1024() 7276 b5 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 7280 tmp = b3 ^ b2; threefish_decrypt_1024() 7281 b3 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 7285 tmp = b1 ^ b0; threefish_decrypt_1024() 7286 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 7290 tmp = b7 ^ b12; threefish_decrypt_1024() 7291 b7 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 7294 tmp = b3 ^ b10; threefish_decrypt_1024() 7295 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 7298 tmp = b5 ^ b8; threefish_decrypt_1024() 7299 b5 = (tmp >> 28) | (tmp << (64 - 28)); threefish_decrypt_1024() 7302 tmp = b1 ^ b14; threefish_decrypt_1024() 7303 b1 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 7306 tmp = b9 ^ b4; threefish_decrypt_1024() 7307 b9 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 7310 tmp = b13 ^ b6; threefish_decrypt_1024() 7311 b13 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 7314 tmp = b11 ^ b2; threefish_decrypt_1024() 7315 b11 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 7318 tmp = b15 ^ b0; threefish_decrypt_1024() 7319 b15 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_1024() 7322 tmp = b9 ^ b10; threefish_decrypt_1024() 7323 b9 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 7326 tmp = b11 ^ b8; threefish_decrypt_1024() 7327 b11 = (tmp >> 59) | (tmp << (64 - 59)); threefish_decrypt_1024() 7330 tmp = b13 ^ b14; threefish_decrypt_1024() 7331 b13 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 7334 tmp = b15 ^ b12; threefish_decrypt_1024() 7335 b15 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 7338 tmp = b1 ^ b6; threefish_decrypt_1024() 7339 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 7342 tmp = b3 ^ b4; threefish_decrypt_1024() 7343 b3 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 7346 tmp = b5 ^ b2; threefish_decrypt_1024() 7347 b5 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 7350 tmp = b7 ^ b0; threefish_decrypt_1024() 7351 b7 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_1024() 7354 tmp = b1 ^ b8; threefish_decrypt_1024() 7355 b1 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 7358 tmp = b5 ^ b14; threefish_decrypt_1024() 7359 b5 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 7362 tmp = b3 ^ b12; threefish_decrypt_1024() 7363 b3 = (tmp >> 18) | (tmp << (64 - 18)); threefish_decrypt_1024() 7366 tmp = b7 ^ b10; threefish_decrypt_1024() 7367 b7 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_1024() 7370 tmp = b15 ^ b4; threefish_decrypt_1024() 7371 b15 = (tmp >> 55) | (tmp << (64 - 55)); threefish_decrypt_1024() 7374 tmp = b11 ^ b6; threefish_decrypt_1024() 7375 b11 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_1024() 7378 tmp = b13 ^ b2; threefish_decrypt_1024() 7379 b13 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 7382 tmp = b9 ^ b0; threefish_decrypt_1024() 7383 b9 = (tmp >> 38) | (tmp << (64 - 38)); threefish_decrypt_1024() 7386 tmp = b15 ^ b14; threefish_decrypt_1024() 7387 b15 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 7391 tmp = b13 ^ b12; threefish_decrypt_1024() 7392 b13 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_1024() 7396 tmp = b11 ^ b10; threefish_decrypt_1024() 7397 b11 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 7401 tmp = b9 ^ b8; threefish_decrypt_1024() 7402 b9 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 7406 tmp = b7 ^ b6; threefish_decrypt_1024() 7407 b7 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 7411 tmp = b5 ^ b4; threefish_decrypt_1024() 7412 b5 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 7416 tmp = b3 ^ b2; threefish_decrypt_1024() 7417 b3 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 7421 tmp = b1 ^ b0; threefish_decrypt_1024() 7422 b1 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_1024() 7426 tmp = b7 ^ b12; threefish_decrypt_1024() 7427 b7 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 7430 tmp = b3 ^ b10; threefish_decrypt_1024() 7431 b3 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 7434 tmp = b5 ^ b8; threefish_decrypt_1024() 7435 b5 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 7438 tmp = b1 ^ b14; threefish_decrypt_1024() 7439 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 7442 tmp = b9 ^ b4; threefish_decrypt_1024() 7443 b9 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 7446 tmp = b13 ^ b6; threefish_decrypt_1024() 7447 b13 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_1024() 7450 tmp = b11 ^ b2; threefish_decrypt_1024() 7451 b11 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 7454 tmp = b15 ^ b0; threefish_decrypt_1024() 7455 b15 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 7458 tmp = b9 ^ b10; threefish_decrypt_1024() 7459 b9 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 7462 tmp = b11 ^ b8; threefish_decrypt_1024() 7463 b11 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 7466 tmp = b13 ^ b14; threefish_decrypt_1024() 7467 b13 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 7470 tmp = b15 ^ b12; threefish_decrypt_1024() 7471 b15 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 7474 tmp = b1 ^ b6; threefish_decrypt_1024() 7475 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_1024() 7478 tmp = b3 ^ b4; threefish_decrypt_1024() 7479 b3 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 7482 tmp = b5 ^ b2; threefish_decrypt_1024() 7483 b5 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 7486 tmp = b7 ^ b0; threefish_decrypt_1024() 7487 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 7490 tmp = b1 ^ b8; threefish_decrypt_1024() 7491 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 7494 tmp = b5 ^ b14; threefish_decrypt_1024() 7495 b5 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 7498 tmp = b3 ^ b12; threefish_decrypt_1024() 7499 b3 = (tmp >> 53) | (tmp << (64 - 53)); threefish_decrypt_1024() 7502 tmp = b7 ^ b10; threefish_decrypt_1024() 7503 b7 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 7506 tmp = b15 ^ b4; threefish_decrypt_1024() 7507 b15 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 7510 tmp = b11 ^ b6; threefish_decrypt_1024() 7511 b11 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_1024() 7514 tmp = b13 ^ b2; threefish_decrypt_1024() 7515 b13 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 7518 tmp = b9 ^ b0; threefish_decrypt_1024() 7519 b9 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 7522 tmp = b15 ^ b14; threefish_decrypt_1024() 7523 b15 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_1024() 7527 tmp = b13 ^ b12; threefish_decrypt_1024() 7528 b13 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 7532 tmp = b11 ^ b10; threefish_decrypt_1024() 7533 b11 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 7537 tmp = b9 ^ b8; threefish_decrypt_1024() 7538 b9 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_1024() 7542 tmp = b7 ^ b6; threefish_decrypt_1024() 7543 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 7547 tmp = b5 ^ b4; threefish_decrypt_1024() 7548 b5 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 7552 tmp = b3 ^ b2; threefish_decrypt_1024() 7553 b3 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 7557 tmp = b1 ^ b0; threefish_decrypt_1024() 7558 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 7562 tmp = b7 ^ b12; threefish_decrypt_1024() 7563 b7 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 7566 tmp = b3 ^ b10; threefish_decrypt_1024() 7567 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 7570 tmp = b5 ^ b8; threefish_decrypt_1024() 7571 b5 = (tmp >> 28) | (tmp << (64 - 28)); threefish_decrypt_1024() 7574 tmp = b1 ^ b14; threefish_decrypt_1024() 7575 b1 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 7578 tmp = b9 ^ b4; threefish_decrypt_1024() 7579 b9 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 7582 tmp = b13 ^ b6; threefish_decrypt_1024() 7583 b13 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 7586 tmp = b11 ^ b2; threefish_decrypt_1024() 7587 b11 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 7590 tmp = b15 ^ b0; threefish_decrypt_1024() 7591 b15 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_1024() 7594 tmp = b9 ^ b10; threefish_decrypt_1024() 7595 b9 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 7598 tmp = b11 ^ b8; threefish_decrypt_1024() 7599 b11 = (tmp >> 59) | (tmp << (64 - 59)); threefish_decrypt_1024() 7602 tmp = b13 ^ b14; threefish_decrypt_1024() 7603 b13 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 7606 tmp = b15 ^ b12; threefish_decrypt_1024() 7607 b15 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 7610 tmp = b1 ^ b6; threefish_decrypt_1024() 7611 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 7614 tmp = b3 ^ b4; threefish_decrypt_1024() 7615 b3 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 7618 tmp = b5 ^ b2; threefish_decrypt_1024() 7619 b5 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 7622 tmp = b7 ^ b0; threefish_decrypt_1024() 7623 b7 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_1024() 7626 tmp = b1 ^ b8; threefish_decrypt_1024() 7627 b1 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 7630 tmp = b5 ^ b14; threefish_decrypt_1024() 7631 b5 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 7634 tmp = b3 ^ b12; threefish_decrypt_1024() 7635 b3 = (tmp >> 18) | (tmp << (64 - 18)); threefish_decrypt_1024() 7638 tmp = b7 ^ b10; threefish_decrypt_1024() 7639 b7 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_1024() 7642 tmp = b15 ^ b4; threefish_decrypt_1024() 7643 b15 = (tmp >> 55) | (tmp << (64 - 55)); threefish_decrypt_1024() 7646 tmp = b11 ^ b6; threefish_decrypt_1024() 7647 b11 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_1024() 7650 tmp = b13 ^ b2; threefish_decrypt_1024() 7651 b13 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 7654 tmp = b9 ^ b0; threefish_decrypt_1024() 7655 b9 = (tmp >> 38) | (tmp << (64 - 38)); threefish_decrypt_1024() 7658 tmp = b15 ^ b14; threefish_decrypt_1024() 7659 b15 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 7663 tmp = b13 ^ b12; threefish_decrypt_1024() 7664 b13 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_1024() 7668 tmp = b11 ^ b10; threefish_decrypt_1024() 7669 b11 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 7673 tmp = b9 ^ b8; threefish_decrypt_1024() 7674 b9 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 7678 tmp = b7 ^ b6; threefish_decrypt_1024() 7679 b7 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 7683 tmp = b5 ^ b4; threefish_decrypt_1024() 7684 b5 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 7688 tmp = b3 ^ b2; threefish_decrypt_1024() 7689 b3 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 7693 tmp = b1 ^ b0; threefish_decrypt_1024() 7694 b1 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_1024() 7698 tmp = b7 ^ b12; threefish_decrypt_1024() 7699 b7 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 7702 tmp = b3 ^ b10; threefish_decrypt_1024() 7703 b3 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 7706 tmp = b5 ^ b8; threefish_decrypt_1024() 7707 b5 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 7710 tmp = b1 ^ b14; threefish_decrypt_1024() 7711 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 7714 tmp = b9 ^ b4; threefish_decrypt_1024() 7715 b9 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 7718 tmp = b13 ^ b6; threefish_decrypt_1024() 7719 b13 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_1024() 7722 tmp = b11 ^ b2; threefish_decrypt_1024() 7723 b11 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 7726 tmp = b15 ^ b0; threefish_decrypt_1024() 7727 b15 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 7730 tmp = b9 ^ b10; threefish_decrypt_1024() 7731 b9 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 7734 tmp = b11 ^ b8; threefish_decrypt_1024() 7735 b11 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 7738 tmp = b13 ^ b14; threefish_decrypt_1024() 7739 b13 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 7742 tmp = b15 ^ b12; threefish_decrypt_1024() 7743 b15 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 7746 tmp = b1 ^ b6; threefish_decrypt_1024() 7747 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_1024() 7750 tmp = b3 ^ b4; threefish_decrypt_1024() 7751 b3 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 7754 tmp = b5 ^ b2; threefish_decrypt_1024() 7755 b5 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 7758 tmp = b7 ^ b0; threefish_decrypt_1024() 7759 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 7762 tmp = b1 ^ b8; threefish_decrypt_1024() 7763 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 7766 tmp = b5 ^ b14; threefish_decrypt_1024() 7767 b5 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 7770 tmp = b3 ^ b12; threefish_decrypt_1024() 7771 b3 = (tmp >> 53) | (tmp << (64 - 53)); threefish_decrypt_1024() 7774 tmp = b7 ^ b10; threefish_decrypt_1024() 7775 b7 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 7778 tmp = b15 ^ b4; threefish_decrypt_1024() 7779 b15 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 7782 tmp = b11 ^ b6; threefish_decrypt_1024() 7783 b11 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_1024() 7786 tmp = b13 ^ b2; threefish_decrypt_1024() 7787 b13 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 7790 tmp = b9 ^ b0; threefish_decrypt_1024() 7791 b9 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 7794 tmp = b15 ^ b14; threefish_decrypt_1024() 7795 b15 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_1024() 7799 tmp = b13 ^ b12; threefish_decrypt_1024() 7800 b13 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 7804 tmp = b11 ^ b10; threefish_decrypt_1024() 7805 b11 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 7809 tmp = b9 ^ b8; threefish_decrypt_1024() 7810 b9 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_1024() 7814 tmp = b7 ^ b6; threefish_decrypt_1024() 7815 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 7819 tmp = b5 ^ b4; threefish_decrypt_1024() 7820 b5 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 7824 tmp = b3 ^ b2; threefish_decrypt_1024() 7825 b3 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 7829 tmp = b1 ^ b0; threefish_decrypt_1024() 7830 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 7834 tmp = b7 ^ b12; threefish_decrypt_1024() 7835 b7 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 7838 tmp = b3 ^ b10; threefish_decrypt_1024() 7839 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 7842 tmp = b5 ^ b8; threefish_decrypt_1024() 7843 b5 = (tmp >> 28) | (tmp << (64 - 28)); threefish_decrypt_1024() 7846 tmp = b1 ^ b14; threefish_decrypt_1024() 7847 b1 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 7850 tmp = b9 ^ b4; threefish_decrypt_1024() 7851 b9 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 7854 tmp = b13 ^ b6; threefish_decrypt_1024() 7855 b13 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 7858 tmp = b11 ^ b2; threefish_decrypt_1024() 7859 b11 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 7862 tmp = b15 ^ b0; threefish_decrypt_1024() 7863 b15 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_1024() 7866 tmp = b9 ^ b10; threefish_decrypt_1024() 7867 b9 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 7870 tmp = b11 ^ b8; threefish_decrypt_1024() 7871 b11 = (tmp >> 59) | (tmp << (64 - 59)); threefish_decrypt_1024() 7874 tmp = b13 ^ b14; threefish_decrypt_1024() 7875 b13 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 7878 tmp = b15 ^ b12; threefish_decrypt_1024() 7879 b15 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 7882 tmp = b1 ^ b6; threefish_decrypt_1024() 7883 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 7886 tmp = b3 ^ b4; threefish_decrypt_1024() 7887 b3 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 7890 tmp = b5 ^ b2; threefish_decrypt_1024() 7891 b5 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 7894 tmp = b7 ^ b0; threefish_decrypt_1024() 7895 b7 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_1024() 7898 tmp = b1 ^ b8; threefish_decrypt_1024() 7899 b1 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 7902 tmp = b5 ^ b14; threefish_decrypt_1024() 7903 b5 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 7906 tmp = b3 ^ b12; threefish_decrypt_1024() 7907 b3 = (tmp >> 18) | (tmp << (64 - 18)); threefish_decrypt_1024() 7910 tmp = b7 ^ b10; threefish_decrypt_1024() 7911 b7 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_1024() 7914 tmp = b15 ^ b4; threefish_decrypt_1024() 7915 b15 = (tmp >> 55) | (tmp << (64 - 55)); threefish_decrypt_1024() 7918 tmp = b11 ^ b6; threefish_decrypt_1024() 7919 b11 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_1024() 7922 tmp = b13 ^ b2; threefish_decrypt_1024() 7923 b13 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 7926 tmp = b9 ^ b0; threefish_decrypt_1024() 7927 b9 = (tmp >> 38) | (tmp << (64 - 38)); threefish_decrypt_1024() 7930 tmp = b15 ^ b14; threefish_decrypt_1024() 7931 b15 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 7935 tmp = b13 ^ b12; threefish_decrypt_1024() 7936 b13 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_1024() 7940 tmp = b11 ^ b10; threefish_decrypt_1024() 7941 b11 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 7945 tmp = b9 ^ b8; threefish_decrypt_1024() 7946 b9 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 7950 tmp = b7 ^ b6; threefish_decrypt_1024() 7951 b7 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 7955 tmp = b5 ^ b4; threefish_decrypt_1024() 7956 b5 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 7960 tmp = b3 ^ b2; threefish_decrypt_1024() 7961 b3 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 7965 tmp = b1 ^ b0; threefish_decrypt_1024() 7966 b1 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_1024() 7970 tmp = b7 ^ b12; threefish_decrypt_1024() 7971 b7 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 7974 tmp = b3 ^ b10; threefish_decrypt_1024() 7975 b3 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 7978 tmp = b5 ^ b8; threefish_decrypt_1024() 7979 b5 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 7982 tmp = b1 ^ b14; threefish_decrypt_1024() 7983 b1 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 7986 tmp = b9 ^ b4; threefish_decrypt_1024() 7987 b9 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 7990 tmp = b13 ^ b6; threefish_decrypt_1024() 7991 b13 = (tmp >> 35) | (tmp << (64 - 35)); threefish_decrypt_1024() 7994 tmp = b11 ^ b2; threefish_decrypt_1024() 7995 b11 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 7998 tmp = b15 ^ b0; threefish_decrypt_1024() 7999 b15 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 8002 tmp = b9 ^ b10; threefish_decrypt_1024() 8003 b9 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 8006 tmp = b11 ^ b8; threefish_decrypt_1024() 8007 b11 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 8010 tmp = b13 ^ b14; threefish_decrypt_1024() 8011 b13 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 8014 tmp = b15 ^ b12; threefish_decrypt_1024() 8015 b15 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 8018 tmp = b1 ^ b6; threefish_decrypt_1024() 8019 b1 = (tmp >> 46) | (tmp << (64 - 46)); threefish_decrypt_1024() 8022 tmp = b3 ^ b4; threefish_decrypt_1024() 8023 b3 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 8026 tmp = b5 ^ b2; threefish_decrypt_1024() 8027 b5 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 8030 tmp = b7 ^ b0; threefish_decrypt_1024() 8031 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 8034 tmp = b1 ^ b8; threefish_decrypt_1024() 8035 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 8038 tmp = b5 ^ b14; threefish_decrypt_1024() 8039 b5 = (tmp >> 42) | (tmp << (64 - 42)); threefish_decrypt_1024() 8042 tmp = b3 ^ b12; threefish_decrypt_1024() 8043 b3 = (tmp >> 53) | (tmp << (64 - 53)); threefish_decrypt_1024() 8046 tmp = b7 ^ b10; threefish_decrypt_1024() 8047 b7 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 8050 tmp = b15 ^ b4; threefish_decrypt_1024() 8051 b15 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 8054 tmp = b11 ^ b6; threefish_decrypt_1024() 8055 b11 = (tmp >> 56) | (tmp << (64 - 56)); threefish_decrypt_1024() 8058 tmp = b13 ^ b2; threefish_decrypt_1024() 8059 b13 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 8062 tmp = b9 ^ b0; threefish_decrypt_1024() 8063 b9 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 8066 tmp = b15 ^ b14; threefish_decrypt_1024() 8067 b15 = (tmp >> 30) | (tmp << (64 - 30)); threefish_decrypt_1024() 8071 tmp = b13 ^ b12; threefish_decrypt_1024() 8072 b13 = (tmp >> 44) | (tmp << (64 - 44)); threefish_decrypt_1024() 8076 tmp = b11 ^ b10; threefish_decrypt_1024() 8077 b11 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 8081 tmp = b9 ^ b8; threefish_decrypt_1024() 8082 b9 = (tmp >> 12) | (tmp << (64 - 12)); threefish_decrypt_1024() 8086 tmp = b7 ^ b6; threefish_decrypt_1024() 8087 b7 = (tmp >> 31) | (tmp << (64 - 31)); threefish_decrypt_1024() 8091 tmp = b5 ^ b4; threefish_decrypt_1024() 8092 b5 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 8096 tmp = b3 ^ b2; threefish_decrypt_1024() 8097 b3 = (tmp >> 9) | (tmp << (64 - 9)); threefish_decrypt_1024() 8101 tmp = b1 ^ b0; threefish_decrypt_1024() 8102 b1 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 8106 tmp = b7 ^ b12; threefish_decrypt_1024() 8107 b7 = (tmp >> 25) | (tmp << (64 - 25)); threefish_decrypt_1024() 8110 tmp = b3 ^ b10; threefish_decrypt_1024() 8111 b3 = (tmp >> 16) | (tmp << (64 - 16)); threefish_decrypt_1024() 8114 tmp = b5 ^ b8; threefish_decrypt_1024() 8115 b5 = (tmp >> 28) | (tmp << (64 - 28)); threefish_decrypt_1024() 8118 tmp = b1 ^ b14; threefish_decrypt_1024() 8119 b1 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 8122 tmp = b9 ^ b4; threefish_decrypt_1024() 8123 b9 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 8126 tmp = b13 ^ b6; threefish_decrypt_1024() 8127 b13 = (tmp >> 48) | (tmp << (64 - 48)); threefish_decrypt_1024() 8130 tmp = b11 ^ b2; threefish_decrypt_1024() 8131 b11 = (tmp >> 20) | (tmp << (64 - 20)); threefish_decrypt_1024() 8134 tmp = b15 ^ b0; threefish_decrypt_1024() 8135 b15 = (tmp >> 5) | (tmp << (64 - 5)); threefish_decrypt_1024() 8138 tmp = b9 ^ b10; threefish_decrypt_1024() 8139 b9 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 8142 tmp = b11 ^ b8; threefish_decrypt_1024() 8143 b11 = (tmp >> 59) | (tmp << (64 - 59)); threefish_decrypt_1024() 8146 tmp = b13 ^ b14; threefish_decrypt_1024() 8147 b13 = (tmp >> 41) | (tmp << (64 - 41)); threefish_decrypt_1024() 8150 tmp = b15 ^ b12; threefish_decrypt_1024() 8151 b15 = (tmp >> 34) | (tmp << (64 - 34)); threefish_decrypt_1024() 8154 tmp = b1 ^ b6; threefish_decrypt_1024() 8155 b1 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 8158 tmp = b3 ^ b4; threefish_decrypt_1024() 8159 b3 = (tmp >> 51) | (tmp << (64 - 51)); threefish_decrypt_1024() 8162 tmp = b5 ^ b2; threefish_decrypt_1024() 8163 b5 = (tmp >> 4) | (tmp << (64 - 4)); threefish_decrypt_1024() 8166 tmp = b7 ^ b0; threefish_decrypt_1024() 8167 b7 = (tmp >> 33) | (tmp << (64 - 33)); threefish_decrypt_1024() 8170 tmp = b1 ^ b8; threefish_decrypt_1024() 8171 b1 = (tmp >> 52) | (tmp << (64 - 52)); threefish_decrypt_1024() 8174 tmp = b5 ^ b14; threefish_decrypt_1024() 8175 b5 = (tmp >> 23) | (tmp << (64 - 23)); threefish_decrypt_1024() 8178 tmp = b3 ^ b12; threefish_decrypt_1024() 8179 b3 = (tmp >> 18) | (tmp << (64 - 18)); threefish_decrypt_1024() 8182 tmp = b7 ^ b10; threefish_decrypt_1024() 8183 b7 = (tmp >> 49) | (tmp << (64 - 49)); threefish_decrypt_1024() 8186 tmp = b15 ^ b4; threefish_decrypt_1024() 8187 b15 = (tmp >> 55) | (tmp << (64 - 55)); threefish_decrypt_1024() 8190 tmp = b11 ^ b6; threefish_decrypt_1024() 8191 b11 = (tmp >> 10) | (tmp << (64 - 10)); threefish_decrypt_1024() 8194 tmp = b13 ^ b2; threefish_decrypt_1024() 8195 b13 = (tmp >> 19) | (tmp << (64 - 19)); threefish_decrypt_1024() 8198 tmp = b9 ^ b0; threefish_decrypt_1024() 8199 b9 = (tmp >> 38) | (tmp << (64 - 38)); threefish_decrypt_1024() 8202 tmp = b15 ^ b14; threefish_decrypt_1024() 8203 b15 = (tmp >> 37) | (tmp << (64 - 37)); threefish_decrypt_1024() 8207 tmp = b13 ^ b12; threefish_decrypt_1024() 8208 b13 = (tmp >> 22) | (tmp << (64 - 22)); threefish_decrypt_1024() 8212 tmp = b11 ^ b10; threefish_decrypt_1024() 8213 b11 = (tmp >> 17) | (tmp << (64 - 17)); threefish_decrypt_1024() 8217 tmp = b9 ^ b8; threefish_decrypt_1024() 8218 b9 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 8222 tmp = b7 ^ b6; threefish_decrypt_1024() 8223 b7 = (tmp >> 47) | (tmp << (64 - 47)); threefish_decrypt_1024() 8227 tmp = b5 ^ b4; threefish_decrypt_1024() 8228 b5 = (tmp >> 8) | (tmp << (64 - 8)); threefish_decrypt_1024() 8232 tmp = b3 ^ b2; threefish_decrypt_1024() 8233 b3 = (tmp >> 13) | (tmp << (64 - 13)); threefish_decrypt_1024() 8237 tmp = b1 ^ b0; threefish_decrypt_1024() 8238 b1 = (tmp >> 24) | (tmp << (64 - 24)); threefish_decrypt_1024()
/linux-4.4.14/tools/build/feature/
H A D	test-cplus-demangle.c	7 char *tmp; main() local 9 tmp = cplus_demangle(symbol, 0); main() 11 printf("demangled symbol: {%s}\n", tmp); main()
H A D	test-libbfd.c	8 char *tmp; main() local 10 tmp = bfd_demangle(0, symbol, 0); main() 12 printf("demangled symbol: {%s}\n", tmp); main()
/linux-4.4.14/drivers/staging/fbtft/
H A D	fb_ssd1331.c	127 unsigned long tmp[GAMMA_NUM * GAMMA_LEN]; set_gamma() local 138 tmp[i] = acc; set_gamma() 148 tmp[0], tmp[1], tmp[2], tmp[3], tmp[4], tmp[5], tmp[6], tmp[7], set_gamma() 149 tmp[8], tmp[9], tmp[10], tmp[11], tmp[12], tmp[13], tmp[14], tmp[15], set_gamma() 150 tmp[16], tmp[17], tmp[18], tmp[19], tmp[20], tmp[21], tmp[22], tmp[23], set_gamma() 151 tmp[24], tmp[25], tmp[26], tmp[27], tmp[28], tmp[29], tmp[30], tmp[31], set_gamma() 152 tmp[32], tmp[33], tmp[34], tmp[35], tmp[36], tmp[37], tmp[38], tmp[39], set_gamma() 153 tmp[40], tmp[41], tmp[42], tmp[43], tmp[44], tmp[45], tmp[46], tmp[47], set_gamma() 154 tmp[48], tmp[49], tmp[50], tmp[51], tmp[52], tmp[53], tmp[54], tmp[55], set_gamma() 155 tmp[56], tmp[57], tmp[58], tmp[59], tmp[60], tmp[61], tmp[62]); set_gamma()
H A D	fb_ssd1351.c	122 unsigned long tmp[GAMMA_NUM * GAMMA_LEN]; set_gamma() local 133 tmp[i] = acc; set_gamma() 143 tmp[0], tmp[1], tmp[2], tmp[3], tmp[4], tmp[5], tmp[6], tmp[7], set_gamma() 144 tmp[8], tmp[9], tmp[10], tmp[11], tmp[12], tmp[13], tmp[14], tmp[15], set_gamma() 145 tmp[16], tmp[17], tmp[18], tmp[19], tmp[20], tmp[21], tmp[22], tmp[23], set_gamma() 146 tmp[24], tmp[25], tmp[26], tmp[27], tmp[28], tmp[29], tmp[30], tmp[31], set_gamma() 147 tmp[32], tmp[33], tmp[34], tmp[35], tmp[36], tmp[37], tmp[38], tmp[39], set_gamma() 148 tmp[40], tmp[41], tmp[42], tmp[43], tmp[44], tmp[45], tmp[46], tmp[47], set_gamma() 149 tmp[48], tmp[49], tmp[50], tmp[51], tmp[52], tmp[53], tmp[54], tmp[55], set_gamma() 150 tmp[56], tmp[57], tmp[58], tmp[59], tmp[60], tmp[61], tmp[62]); set_gamma()
/linux-4.4.14/arch/arm/mm/
H A D	abort-macro.S	12 .macro do_thumb_abort, fsr, pc, psr, tmp 15 ldrh \tmp, [\pc] @ Read aborted Thumb instruction 17 and \tmp, \tmp, # 0xfe00 @ Mask opcode field 18 cmp \tmp, # 0x5600 @ Is it ldrsb? 19 orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes 20 tst \tmp, #1 << 11 @ L = 0 -> write 33 .macro teq_ldrd, tmp, insn 34 mov \tmp, #0x0e100000 35 orr \tmp, #0x000000f0 36 and \tmp, \insn, \tmp 37 teq \tmp, #0x000000d0
H A D	proc-v7-3level.S	129 .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp 130 ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address 131 cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET? 132 mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister 133 orr \tmp, \tmp, #TTB_EAE 134 ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP) 135 ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP) 136 ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16) 137 ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP << 16) 143 orrls \tmp, \tmp, #TTBR1_SIZE @ TTBCR.T1SZ 144 mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR 145 mov \tmp, \ttbr1, lsr #20 148 mcrr p15, 1, \ttbr1, \tmp, c2 @ load TTBR1
/linux-4.4.14/drivers/video/fbdev/kyro/
H A D	STG4000Ramdac.c	29 u32 tmp = 0; InitialiseRamdac() local 35 tmp = STG_READ_REG(SoftwareReset); InitialiseRamdac() 37 if (tmp & 0x1) { InitialiseRamdac() 39 STG_WRITE_REG(SoftwareReset, tmp); InitialiseRamdac() 43 tmp = STG_READ_REG(DACPixelFormat); InitialiseRamdac() 53 tmp |= _16BPP; InitialiseRamdac() 60 tmp |= _32BPP; InitialiseRamdac() 67 STG_WRITE_REG(DACPixelFormat, tmp); InitialiseRamdac() 76 tmp = STG_READ_REG(DACPrimSize); InitialiseRamdac() 79 tmp |= InitialiseRamdac() 83 STG_WRITE_REG(DACPrimSize, tmp); InitialiseRamdac() 90 tmp = STG_READ_REG(DACPLLMode); InitialiseRamdac() 92 /* tmp |= ((P-1) | ((F-2) << 2) | ((R-2) << 11)); */ InitialiseRamdac() 93 tmp |= ((P) | ((F - 2) << 2) | ((R - 2) << 11)); InitialiseRamdac() 94 STG_WRITE_REG(DACPLLMode, tmp); InitialiseRamdac() 97 tmp = STG_READ_REG(DACPrimAddress); InitialiseRamdac() 100 STG_WRITE_REG(DACPrimAddress, tmp); InitialiseRamdac() 103 tmp = STG_READ_REG(DACCursorCtrl); InitialiseRamdac() 104 tmp &= ~SET_BIT(31); InitialiseRamdac() 105 STG_WRITE_REG(DACCursorCtrl, tmp); InitialiseRamdac() 107 tmp = STG_READ_REG(DACCursorAddr); InitialiseRamdac() 109 STG_WRITE_REG(DACCursorAddr, tmp); InitialiseRamdac() 112 tmp = STG_READ_REG(DACVidWinStart); InitialiseRamdac() 115 STG_WRITE_REG(DACVidWinStart, tmp); InitialiseRamdac() 117 tmp = STG_READ_REG(DACVidWinEnd); InitialiseRamdac() 120 STG_WRITE_REG(DACVidWinEnd, tmp); InitialiseRamdac() 123 tmp = STG_READ_REG(DACBorderColor); InitialiseRamdac() 125 STG_WRITE_REG(DACBorderColor, tmp); InitialiseRamdac() 131 tmp = STG_READ_REG(DACCrcTrigger); InitialiseRamdac() 133 STG_WRITE_REG(DACCrcTrigger, tmp); InitialiseRamdac() 136 tmp = STG_READ_REG(DigVidPortCtrl); InitialiseRamdac() 141 STG_WRITE_REG(DigVidPortCtrl, tmp); InitialiseRamdac() 149 u32 tmp; DisableRamdacOutput() local 152 tmp = (STG_READ_REG(DACStreamCtrl)) & ~SET_BIT(0); DisableRamdacOutput() 153 STG_WRITE_REG(DACStreamCtrl, tmp); DisableRamdacOutput() 158 u32 tmp; EnableRamdacOutput() local 161 tmp = (STG_READ_REG(DACStreamCtrl)) | SET_BIT(0); EnableRamdacOutput() 162 STG_WRITE_REG(DACStreamCtrl, tmp); EnableRamdacOutput()
H A D	STG4000VTG.c	19 u32 tmp; DisableVGA() local 23 tmp = STG_READ_REG(SoftwareReset); DisableVGA() 25 STG_WRITE_REG(SoftwareReset, tmp); DisableVGA() 33 tmp = STG_READ_REG(SoftwareReset); DisableVGA() 34 tmp |= SET_BIT(8); DisableVGA() 35 STG_WRITE_REG(SoftwareReset, tmp); DisableVGA() 40 u32 tmp = 0; StopVTG() local 43 tmp = (STG_READ_REG(DACSyncCtrl)) | SET_BIT(0) | SET_BIT(2); StopVTG() 45 STG_WRITE_REG(DACSyncCtrl, tmp); StopVTG() 50 u32 tmp = 0; StartVTG() local 53 tmp = ((STG_READ_REG(DACSyncCtrl)) | SET_BIT(31)); StartVTG() 56 STG_WRITE_REG(DACSyncCtrl, tmp); StartVTG() 62 u32 tmp = 0; SetupVTG() local 119 tmp = STG_READ_REG(DACHorTim1); SetupVTG() 122 tmp |= (HTotal) | (HBackPorcStrt << 16); SetupVTG() 123 STG_WRITE_REG(DACHorTim1, tmp); SetupVTG() 125 tmp = STG_READ_REG(DACHorTim2); SetupVTG() 128 tmp |= (HDisplayStrt << 16) | HLeftBorderStrt; SetupVTG() 129 STG_WRITE_REG(DACHorTim2, tmp); SetupVTG() 131 tmp = STG_READ_REG(DACHorTim3); SetupVTG() 134 tmp |= (HFrontPorchStrt << 16) | HRightBorderStrt; SetupVTG() 135 STG_WRITE_REG(DACHorTim3, tmp); SetupVTG() 138 tmp = STG_READ_REG(DACVerTim1); SetupVTG() 141 tmp |= (VBackPorchStrt << 16) | (VTotal); SetupVTG() 142 STG_WRITE_REG(DACVerTim1, tmp); SetupVTG() 144 tmp = STG_READ_REG(DACVerTim2); SetupVTG() 147 tmp |= (VDisplayStrt << 16) | VTopBorderStrt; SetupVTG() 148 STG_WRITE_REG(DACVerTim2, tmp); SetupVTG() 150 tmp = STG_READ_REG(DACVerTim3); SetupVTG() 153 tmp |= (VFrontPorchStrt << 16) | VBottomBorderStrt; SetupVTG() 154 STG_WRITE_REG(DACVerTim3, tmp); SetupVTG() 157 tmp = STG_READ_REG(DACSyncCtrl) | SET_BIT(3) | SET_BIT(1); SetupVTG() 160 tmp &= ~0x8; SetupVTG() 162 tmp &= ~0x2; SetupVTG() 164 tmp &= ~0xA; SetupVTG() 166 tmp &= ~0x0; SetupVTG() 169 STG_WRITE_REG(DACSyncCtrl, tmp); SetupVTG()
H A D	STG4000OverlayDevice.c	81 u32 tmp; ResetOverlayRegisters() local 84 tmp = STG_READ_REG(DACOverlayAddr); ResetOverlayRegisters() 87 STG_WRITE_REG(DACOverlayAddr, tmp); ResetOverlayRegisters() 90 tmp = STG_READ_REG(DACOverlayUAddr); ResetOverlayRegisters() 92 STG_WRITE_REG(DACOverlayUAddr, tmp); ResetOverlayRegisters() 95 tmp = STG_READ_REG(DACOverlayVAddr); ResetOverlayRegisters() 97 STG_WRITE_REG(DACOverlayVAddr, tmp); ResetOverlayRegisters() 100 tmp = STG_READ_REG(DACOverlaySize); ResetOverlayRegisters() 103 STG_WRITE_REG(DACOverlaySize, tmp); ResetOverlayRegisters() 106 tmp = STG4000_NO_DECIMATION; ResetOverlayRegisters() 107 STG_WRITE_REG(DACOverlayVtDec, tmp); ResetOverlayRegisters() 110 tmp = STG_READ_REG(DACPixelFormat); ResetOverlayRegisters() 113 STG_WRITE_REG(DACPixelFormat, tmp); ResetOverlayRegisters() 116 tmp = STG_READ_REG(DACVerticalScal); ResetOverlayRegisters() 119 tmp |= STG4000_NO_SCALING; /* Set to no scaling */ ResetOverlayRegisters() 120 STG_WRITE_REG(DACVerticalScal, tmp); ResetOverlayRegisters() 123 tmp = STG_READ_REG(DACHorizontalScal); ResetOverlayRegisters() 126 tmp |= STG4000_NO_SCALING; /* Set to no scaling */ ResetOverlayRegisters() 127 STG_WRITE_REG(DACHorizontalScal, tmp); ResetOverlayRegisters() 133 tmp = STG_READ_REG(DACBlendCtrl); ResetOverlayRegisters() 135 tmp = (GRAPHICS_MODE << 28); ResetOverlayRegisters() 136 STG_WRITE_REG(DACBlendCtrl, tmp); ResetOverlayRegisters() 147 u32 tmp; CreateOverlaySurface() local 176 tmp = STG_READ_REG(DACOverlayAddr); CreateOverlaySurface() 181 tmp |= SET_BIT(31); /* Overlay format to Planer */ CreateOverlaySurface() 185 tmp |= (ulOverlayOffset >> 4); CreateOverlaySurface() 186 STG_WRITE_REG(DACOverlayAddr, tmp); CreateOverlaySurface() 206 tmp = STG_READ_REG(DACOverlayUAddr); CreateOverlaySurface() 208 tmp |= (ulOffset >> 4); CreateOverlaySurface() 209 STG_WRITE_REG(DACOverlayUAddr, tmp); CreateOverlaySurface() 216 tmp = STG_READ_REG(DACOverlayVAddr); CreateOverlaySurface() 218 tmp |= (ulOffset >> 4); CreateOverlaySurface() 219 STG_WRITE_REG(DACOverlayVAddr, tmp); CreateOverlaySurface() 228 tmp = STG_READ_REG(DACPixelFormat); CreateOverlaySurface() 231 STG_WRITE_REG(DACPixelFormat, tmp); CreateOverlaySurface() 246 u32 tmp; SetOverlayBlendMode() local 248 tmp = STG_READ_REG(DACBlendCtrl); SetOverlayBlendMode() 250 tmp |= (mode << 28); SetOverlayBlendMode() 255 tmp |= (ulColorKey & 0x00FFFFFF); SetOverlayBlendMode() 260 tmp |= ((ulAlpha & 0xF) << 24); SetOverlayBlendMode() 265 tmp |= (ulColorKey & 0x00FFFFFF); SetOverlayBlendMode() 270 tmp |= (ulColorKey & 0x00FFFFFF); SetOverlayBlendMode() 272 tmp |= ((ulAlpha & 0xF) << 24); SetOverlayBlendMode() 283 STG_WRITE_REG(DACBlendCtrl, tmp); SetOverlayBlendMode() 290 u32 tmp; EnableOverlayPlane() local 292 tmp = STG_READ_REG(DACPixelFormat); EnableOverlayPlane() 293 tmp |= SET_BIT(7); EnableOverlayPlane() 294 STG_WRITE_REG(DACPixelFormat, tmp); EnableOverlayPlane() 297 tmp = STG_READ_REG(DACStreamCtrl); EnableOverlayPlane() 298 tmp |= SET_BIT(1); /* video stream */ EnableOverlayPlane() 299 STG_WRITE_REG(DACStreamCtrl, tmp); EnableOverlayPlane() 342 u32 tmp, ulStride; SetOverlayViewPort() local 412 tmp = STG_READ_REG(DACOverlayVtDec); /* Decimation */ SetOverlayViewPort() 414 tmp = ulPattern; SetOverlayViewPort() 415 STG_WRITE_REG(DACOverlayVtDec, tmp); SetOverlayViewPort() 548 tmp = STG_READ_REG(DACVerticalScal); SetOverlayViewPort() 557 tmp |= ((ulStride << 16) | (ulDacYScale)); /* DAC_LS_CTRL = stride */ SetOverlayViewPort() 558 STG_WRITE_REG(DACVerticalScal, tmp); SetOverlayViewPort() 563 tmp = STG_READ_REG(DACOverlaySize); SetOverlayViewPort() 568 tmp |= SetOverlayViewPort() 572 tmp |= SetOverlayViewPort() 577 STG_WRITE_REG(DACOverlaySize, tmp); SetOverlayViewPort() 580 tmp = ((ulLeft << 16)) | (srcDest.ulDstY1); SetOverlayViewPort() 581 STG_WRITE_REG(DACVidWinStart, tmp); SetOverlayViewPort() 584 tmp = ((ulRight) << 16) | (srcDest.ulDstY2); SetOverlayViewPort() 585 STG_WRITE_REG(DACVidWinEnd, tmp); SetOverlayViewPort() 590 tmp = STG_READ_REG(DACPixelFormat); SetOverlayViewPort() 591 tmp = ((ulExcessPixels << 16) | tmp) & 0x7fffffff; SetOverlayViewPort() 592 STG_WRITE_REG(DACPixelFormat, tmp); SetOverlayViewPort() 594 tmp = STG_READ_REG(DACHorizontalScal); SetOverlayViewPort() 597 tmp |= ((ulhDecim << 16) | (ulDacXScale)); SetOverlayViewPort() 598 STG_WRITE_REG(DACHorizontalScal, tmp); SetOverlayViewPort()
/linux-4.4.14/include/linux/unaligned/
H A D	memmove.h	11 u16 tmp; __get_unaligned_memmove16() local 12 memmove(&tmp, p, 2); __get_unaligned_memmove16() 13 return tmp; __get_unaligned_memmove16() 18 u32 tmp; __get_unaligned_memmove32() local 19 memmove(&tmp, p, 4); __get_unaligned_memmove32() 20 return tmp; __get_unaligned_memmove32() 25 u64 tmp; __get_unaligned_memmove64() local 26 memmove(&tmp, p, 8); __get_unaligned_memmove64() 27 return tmp; __get_unaligned_memmove64()
/linux-4.4.14/drivers/gpu/drm/radeon/
H A D	vce_v2_0.c	40 u32 tmp; vce_v2_0_set_sw_cg() local 43 tmp = RREG32(VCE_CLOCK_GATING_B); vce_v2_0_set_sw_cg() 44 tmp |= 0xe70000; vce_v2_0_set_sw_cg() 45 WREG32(VCE_CLOCK_GATING_B, tmp); vce_v2_0_set_sw_cg() 47 tmp = RREG32(VCE_UENC_CLOCK_GATING); vce_v2_0_set_sw_cg() 48 tmp |= 0xff000000; vce_v2_0_set_sw_cg() 49 WREG32(VCE_UENC_CLOCK_GATING, tmp); vce_v2_0_set_sw_cg() 51 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); vce_v2_0_set_sw_cg() 52 tmp &= ~0x3fc; vce_v2_0_set_sw_cg() 53 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); vce_v2_0_set_sw_cg() 57 tmp = RREG32(VCE_CLOCK_GATING_B); vce_v2_0_set_sw_cg() 58 tmp |= 0xe7; vce_v2_0_set_sw_cg() 59 tmp &= ~0xe70000; vce_v2_0_set_sw_cg() 60 WREG32(VCE_CLOCK_GATING_B, tmp); vce_v2_0_set_sw_cg() 62 tmp = RREG32(VCE_UENC_CLOCK_GATING); vce_v2_0_set_sw_cg() 63 tmp |= 0x1fe000; vce_v2_0_set_sw_cg() 64 tmp &= ~0xff000000; vce_v2_0_set_sw_cg() 65 WREG32(VCE_UENC_CLOCK_GATING, tmp); vce_v2_0_set_sw_cg() 67 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); vce_v2_0_set_sw_cg() 68 tmp |= 0x3fc; vce_v2_0_set_sw_cg() 69 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); vce_v2_0_set_sw_cg() 75 u32 orig, tmp; vce_v2_0_set_dyn_cg() local 77 tmp = RREG32(VCE_CLOCK_GATING_B); vce_v2_0_set_dyn_cg() 78 tmp &= ~0x00060006; vce_v2_0_set_dyn_cg() 80 tmp |= 0xe10000; vce_v2_0_set_dyn_cg() 82 tmp |= 0xe1; vce_v2_0_set_dyn_cg() 83 tmp &= ~0xe10000; vce_v2_0_set_dyn_cg() 85 WREG32(VCE_CLOCK_GATING_B, tmp); vce_v2_0_set_dyn_cg() 87 orig = tmp = RREG32(VCE_UENC_CLOCK_GATING); vce_v2_0_set_dyn_cg() 88 tmp &= ~0x1fe000; vce_v2_0_set_dyn_cg() 89 tmp &= ~0xff000000; vce_v2_0_set_dyn_cg() 90 if (tmp != orig) vce_v2_0_set_dyn_cg() 91 WREG32(VCE_UENC_CLOCK_GATING, tmp); vce_v2_0_set_dyn_cg() 93 orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); vce_v2_0_set_dyn_cg() 94 tmp &= ~0x3fc; vce_v2_0_set_dyn_cg() 95 if (tmp != orig) vce_v2_0_set_dyn_cg() 96 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); vce_v2_0_set_dyn_cg() 128 u32 tmp; vce_v2_0_init_cg() local 130 tmp = RREG32(VCE_CLOCK_GATING_A); vce_v2_0_init_cg() 131 tmp &= ~(CGC_CLK_GATE_DLY_TIMER_MASK | CGC_CLK_GATER_OFF_DLY_TIMER_MASK); vce_v2_0_init_cg() 132 tmp |= (CGC_CLK_GATE_DLY_TIMER(0) | CGC_CLK_GATER_OFF_DLY_TIMER(4)); vce_v2_0_init_cg() 133 tmp |= CGC_UENC_WAIT_AWAKE; vce_v2_0_init_cg() 134 WREG32(VCE_CLOCK_GATING_A, tmp); vce_v2_0_init_cg() 136 tmp = RREG32(VCE_UENC_CLOCK_GATING); vce_v2_0_init_cg() 137 tmp &= ~(CLOCK_ON_DELAY_MASK | CLOCK_OFF_DELAY_MASK); vce_v2_0_init_cg() 138 tmp |= (CLOCK_ON_DELAY(0) | CLOCK_OFF_DELAY(4)); vce_v2_0_init_cg() 139 WREG32(VCE_UENC_CLOCK_GATING, tmp); vce_v2_0_init_cg() 141 tmp = RREG32(VCE_CLOCK_GATING_B); vce_v2_0_init_cg() 142 tmp |= 0x10; vce_v2_0_init_cg() 143 tmp &= ~0x100000; vce_v2_0_init_cg() 144 WREG32(VCE_CLOCK_GATING_B, tmp); vce_v2_0_init_cg()
H A D	radeon_clocks.c	195 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); radeon_get_clock_info() local 198 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; radeon_get_clock_info() 200 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; radeon_get_clock_info() 388 uint32_t tmp; radeon_legacy_set_engine_clock() local 395 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); radeon_legacy_set_engine_clock() 396 tmp &= ~RADEON_DONT_USE_XTALIN; radeon_legacy_set_engine_clock() 397 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); radeon_legacy_set_engine_clock() 399 tmp = RREG32_PLL(RADEON_SCLK_CNTL); radeon_legacy_set_engine_clock() 400 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; radeon_legacy_set_engine_clock() 401 WREG32_PLL(RADEON_SCLK_CNTL, tmp); radeon_legacy_set_engine_clock() 405 tmp = RREG32_PLL(RADEON_SPLL_CNTL); radeon_legacy_set_engine_clock() 406 tmp |= RADEON_SPLL_SLEEP; radeon_legacy_set_engine_clock() 407 WREG32_PLL(RADEON_SPLL_CNTL, tmp); radeon_legacy_set_engine_clock() 411 tmp = RREG32_PLL(RADEON_SPLL_CNTL); radeon_legacy_set_engine_clock() 412 tmp |= RADEON_SPLL_RESET; radeon_legacy_set_engine_clock() 413 WREG32_PLL(RADEON_SPLL_CNTL, tmp); radeon_legacy_set_engine_clock() 417 tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); radeon_legacy_set_engine_clock() 418 tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT); radeon_legacy_set_engine_clock() 419 tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT; radeon_legacy_set_engine_clock() 420 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp); radeon_legacy_set_engine_clock() 423 tmp = RREG32_PLL(RADEON_SPLL_CNTL); radeon_legacy_set_engine_clock() 424 tmp &= ~RADEON_SPLL_PVG_MASK; radeon_legacy_set_engine_clock() 426 tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT); radeon_legacy_set_engine_clock() 428 tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT); radeon_legacy_set_engine_clock() 429 WREG32_PLL(RADEON_SPLL_CNTL, tmp); radeon_legacy_set_engine_clock() 431 tmp = RREG32_PLL(RADEON_SPLL_CNTL); radeon_legacy_set_engine_clock() 432 tmp &= ~RADEON_SPLL_SLEEP; radeon_legacy_set_engine_clock() 433 WREG32_PLL(RADEON_SPLL_CNTL, tmp); radeon_legacy_set_engine_clock() 437 tmp = RREG32_PLL(RADEON_SPLL_CNTL); radeon_legacy_set_engine_clock() 438 tmp &= ~RADEON_SPLL_RESET; radeon_legacy_set_engine_clock() 439 WREG32_PLL(RADEON_SPLL_CNTL, tmp); radeon_legacy_set_engine_clock() 443 tmp = RREG32_PLL(RADEON_SCLK_CNTL); radeon_legacy_set_engine_clock() 444 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; radeon_legacy_set_engine_clock() 448 tmp |= 1; radeon_legacy_set_engine_clock() 451 tmp |= 2; radeon_legacy_set_engine_clock() 454 tmp |= 3; radeon_legacy_set_engine_clock() 457 tmp |= 4; radeon_legacy_set_engine_clock() 460 WREG32_PLL(RADEON_SCLK_CNTL, tmp); radeon_legacy_set_engine_clock() 464 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); radeon_legacy_set_engine_clock() 465 tmp |= RADEON_DONT_USE_XTALIN; radeon_legacy_set_engine_clock() 466 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); radeon_legacy_set_engine_clock() 473 uint32_t tmp; radeon_legacy_set_clock_gating() local 477 tmp = RREG32_PLL(RADEON_SCLK_CNTL); radeon_legacy_set_clock_gating() 481 tmp &= radeon_legacy_set_clock_gating() 485 tmp &= radeon_legacy_set_clock_gating() 491 WREG32_PLL(RADEON_SCLK_CNTL, tmp); radeon_legacy_set_clock_gating() 495 tmp = RREG32_PLL(RADEON_SCLK_CNTL); radeon_legacy_set_clock_gating() 496 tmp &= radeon_legacy_set_clock_gating() 510 tmp |= RADEON_DYN_STOP_LAT_MASK; radeon_legacy_set_clock_gating() 511 tmp |= radeon_legacy_set_clock_gating() 514 WREG32_PLL(RADEON_SCLK_CNTL, tmp); radeon_legacy_set_clock_gating() 516 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); radeon_legacy_set_clock_gating() 517 tmp &= ~RADEON_SCLK_MORE_FORCEON; radeon_legacy_set_clock_gating() 518 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; radeon_legacy_set_clock_gating() 519 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); radeon_legacy_set_clock_gating() 521 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); radeon_legacy_set_clock_gating() 522 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | radeon_legacy_set_clock_gating() 524 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); radeon_legacy_set_clock_gating() 526 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); radeon_legacy_set_clock_gating() 527 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | radeon_legacy_set_clock_gating() 540 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); radeon_legacy_set_clock_gating() 542 tmp = RREG32_PLL(R300_SCLK_CNTL2); radeon_legacy_set_clock_gating() 543 tmp &= ~(R300_SCLK_FORCE_TCL | radeon_legacy_set_clock_gating() 546 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT | radeon_legacy_set_clock_gating() 549 WREG32_PLL(R300_SCLK_CNTL2, tmp); radeon_legacy_set_clock_gating() 551 tmp = RREG32_PLL(RADEON_SCLK_CNTL); radeon_legacy_set_clock_gating() 552 tmp &= radeon_legacy_set_clock_gating() 566 tmp |= RADEON_DYN_STOP_LAT_MASK; radeon_legacy_set_clock_gating() 567 WREG32_PLL(RADEON_SCLK_CNTL, tmp); radeon_legacy_set_clock_gating() 569 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); radeon_legacy_set_clock_gating() 570 tmp &= ~RADEON_SCLK_MORE_FORCEON; radeon_legacy_set_clock_gating() 571 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; radeon_legacy_set_clock_gating() 572 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); radeon_legacy_set_clock_gating() 574 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); radeon_legacy_set_clock_gating() 575 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | radeon_legacy_set_clock_gating() 577 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); radeon_legacy_set_clock_gating() 579 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); radeon_legacy_set_clock_gating() 580 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | radeon_legacy_set_clock_gating() 593 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); radeon_legacy_set_clock_gating() 595 tmp = RREG32_PLL(RADEON_MCLK_MISC); radeon_legacy_set_clock_gating() 596 tmp |= (RADEON_MC_MCLK_DYN_ENABLE | radeon_legacy_set_clock_gating() 598 WREG32_PLL(RADEON_MCLK_MISC, tmp); radeon_legacy_set_clock_gating() 600 tmp = RREG32_PLL(RADEON_MCLK_CNTL); radeon_legacy_set_clock_gating() 601 tmp |= (RADEON_FORCEON_MCLKA | radeon_legacy_set_clock_gating() 604 tmp &= ~(RADEON_FORCEON_YCLKA | radeon_legacy_set_clock_gating() 612 if ((tmp & R300_DISABLE_MC_MCLKA) && radeon_legacy_set_clock_gating() 613 (tmp & R300_DISABLE_MC_MCLKB)) { radeon_legacy_set_clock_gating() 615 tmp = RREG32_PLL(RADEON_MCLK_CNTL); radeon_legacy_set_clock_gating() 619 tmp &= radeon_legacy_set_clock_gating() 622 tmp &= radeon_legacy_set_clock_gating() 625 tmp &= ~(R300_DISABLE_MC_MCLKA | radeon_legacy_set_clock_gating() 630 WREG32_PLL(RADEON_MCLK_CNTL, tmp); radeon_legacy_set_clock_gating() 632 tmp = RREG32_PLL(RADEON_SCLK_CNTL); radeon_legacy_set_clock_gating() 633 tmp &= ~(R300_SCLK_FORCE_VAP); radeon_legacy_set_clock_gating() 634 tmp |= RADEON_SCLK_FORCE_CP; radeon_legacy_set_clock_gating() 635 WREG32_PLL(RADEON_SCLK_CNTL, tmp); radeon_legacy_set_clock_gating() 638 tmp = RREG32_PLL(R300_SCLK_CNTL2); radeon_legacy_set_clock_gating() 639 tmp &= ~(R300_SCLK_FORCE_TCL | radeon_legacy_set_clock_gating() 642 WREG32_PLL(R300_SCLK_CNTL2, tmp); radeon_legacy_set_clock_gating() 645 tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); radeon_legacy_set_clock_gating() 647 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK | radeon_legacy_set_clock_gating() 651 tmp |= (RADEON_ENGIN_DYNCLK_MODE | radeon_legacy_set_clock_gating() 653 WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp); radeon_legacy_set_clock_gating() 656 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); radeon_legacy_set_clock_gating() 657 tmp |= RADEON_SCLK_DYN_START_CNTL; radeon_legacy_set_clock_gating() 658 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); radeon_legacy_set_clock_gating() 664 tmp = RREG32_PLL(RADEON_SCLK_CNTL); radeon_legacy_set_clock_gating() 665 /*tmp &= RADEON_SCLK_SRC_SEL_MASK; */ radeon_legacy_set_clock_gating() 666 tmp &= ~RADEON_SCLK_FORCEON_MASK; radeon_legacy_set_clock_gating() 678 tmp |= RADEON_SCLK_FORCE_CP; radeon_legacy_set_clock_gating() 679 tmp |= RADEON_SCLK_FORCE_VIP; radeon_legacy_set_clock_gating() 682 WREG32_PLL(RADEON_SCLK_CNTL, tmp); radeon_legacy_set_clock_gating() 687 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); radeon_legacy_set_clock_gating() 688 tmp &= ~RADEON_SCLK_MORE_FORCEON; radeon_legacy_set_clock_gating() 696 tmp |= RADEON_SCLK_MORE_FORCEON; radeon_legacy_set_clock_gating() 698 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); radeon_legacy_set_clock_gating() 708 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); radeon_legacy_set_clock_gating() 709 tmp |= RADEON_TCL_BYPASS_DISABLE; radeon_legacy_set_clock_gating() 710 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); radeon_legacy_set_clock_gating() 715 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); radeon_legacy_set_clock_gating() 716 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | radeon_legacy_set_clock_gating() 724 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); radeon_legacy_set_clock_gating() 727 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); radeon_legacy_set_clock_gating() 728 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | radeon_legacy_set_clock_gating() 731 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); radeon_legacy_set_clock_gating() 737 tmp = RREG32_PLL(RADEON_SCLK_CNTL); radeon_legacy_set_clock_gating() 738 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP | radeon_legacy_set_clock_gating() 745 WREG32_PLL(RADEON_SCLK_CNTL, tmp); radeon_legacy_set_clock_gating() 748 tmp = RREG32_PLL(RADEON_SCLK_CNTL); radeon_legacy_set_clock_gating() 749 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | radeon_legacy_set_clock_gating() 757 WREG32_PLL(RADEON_SCLK_CNTL, tmp); radeon_legacy_set_clock_gating() 759 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); radeon_legacy_set_clock_gating() 760 tmp |= RADEON_SCLK_MORE_FORCEON; radeon_legacy_set_clock_gating() 761 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); radeon_legacy_set_clock_gating() 763 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); radeon_legacy_set_clock_gating() 764 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | radeon_legacy_set_clock_gating() 767 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); radeon_legacy_set_clock_gating() 769 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); radeon_legacy_set_clock_gating() 770 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | radeon_legacy_set_clock_gating() 784 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); radeon_legacy_set_clock_gating() 787 tmp = RREG32_PLL(R300_SCLK_CNTL2); radeon_legacy_set_clock_gating() 788 tmp |= (R300_SCLK_FORCE_TCL | radeon_legacy_set_clock_gating() 790 WREG32_PLL(R300_SCLK_CNTL2, tmp); radeon_legacy_set_clock_gating() 792 tmp = RREG32_PLL(RADEON_SCLK_CNTL); radeon_legacy_set_clock_gating() 793 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | radeon_legacy_set_clock_gating() 801 WREG32_PLL(RADEON_SCLK_CNTL, tmp); radeon_legacy_set_clock_gating() 803 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); radeon_legacy_set_clock_gating() 804 tmp |= RADEON_SCLK_MORE_FORCEON; radeon_legacy_set_clock_gating() 805 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); radeon_legacy_set_clock_gating() 807 tmp = RREG32_PLL(RADEON_MCLK_CNTL); radeon_legacy_set_clock_gating() 808 tmp |= (RADEON_FORCEON_MCLKA | radeon_legacy_set_clock_gating() 812 WREG32_PLL(RADEON_MCLK_CNTL, tmp); radeon_legacy_set_clock_gating() 814 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); radeon_legacy_set_clock_gating() 815 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | radeon_legacy_set_clock_gating() 818 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); radeon_legacy_set_clock_gating() 820 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); radeon_legacy_set_clock_gating() 821 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | radeon_legacy_set_clock_gating() 835 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); radeon_legacy_set_clock_gating() 837 tmp = RREG32_PLL(RADEON_SCLK_CNTL); radeon_legacy_set_clock_gating() 838 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2); radeon_legacy_set_clock_gating() 839 tmp |= RADEON_SCLK_FORCE_SE; radeon_legacy_set_clock_gating() 842 tmp |= (RADEON_SCLK_FORCE_RB | radeon_legacy_set_clock_gating() 855 tmp |= (RADEON_SCLK_FORCE_HDP | radeon_legacy_set_clock_gating() 862 WREG32_PLL(RADEON_SCLK_CNTL, tmp); radeon_legacy_set_clock_gating() 868 tmp = RREG32_PLL(R300_SCLK_CNTL2); radeon_legacy_set_clock_gating() 869 tmp |= (R300_SCLK_FORCE_TCL | radeon_legacy_set_clock_gating() 872 WREG32_PLL(R300_SCLK_CNTL2, tmp); radeon_legacy_set_clock_gating() 877 tmp = RREG32_PLL(RADEON_MCLK_CNTL); radeon_legacy_set_clock_gating() 878 tmp &= ~(RADEON_FORCEON_MCLKA | radeon_legacy_set_clock_gating() 880 WREG32_PLL(RADEON_MCLK_CNTL, tmp); radeon_legacy_set_clock_gating() 887 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); radeon_legacy_set_clock_gating() 888 tmp |= RADEON_SCLK_MORE_FORCEON; radeon_legacy_set_clock_gating() 889 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); radeon_legacy_set_clock_gating() 893 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); radeon_legacy_set_clock_gating() 894 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | radeon_legacy_set_clock_gating() 902 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); radeon_legacy_set_clock_gating() 905 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); radeon_legacy_set_clock_gating() 906 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | radeon_legacy_set_clock_gating() 908 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); radeon_legacy_set_clock_gating()
H A D	rs400.c	62 uint32_t tmp; rs400_gart_tlb_flush() local 67 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); rs400_gart_tlb_flush() 68 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) rs400_gart_tlb_flush() 110 uint32_t tmp; rs400_gart_enable() local 112 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); rs400_gart_enable() 113 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; rs400_gart_enable() 114 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); rs400_gart_enable() 149 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); rs400_gart_enable() 150 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); rs400_gart_enable() 152 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); rs400_gart_enable() 153 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; rs400_gart_enable() 154 WREG32(RADEON_BUS_CNTL, tmp); rs400_gart_enable() 156 WREG32(RADEON_MC_AGP_LOCATION, tmp); rs400_gart_enable() 157 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; rs400_gart_enable() 158 WREG32(RADEON_BUS_CNTL, tmp); rs400_gart_enable() 161 tmp = (u32)rdev->gart.table_addr & 0xfffff000; rs400_gart_enable() 162 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; rs400_gart_enable() 164 WREG32_MC(RS480_GART_BASE, tmp); rs400_gart_enable() 176 tmp = RREG32_MC(RS480_MC_MISC_CNTL); rs400_gart_enable() 177 tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN; rs400_gart_enable() 178 WREG32_MC(RS480_MC_MISC_CNTL, tmp); rs400_gart_enable() 180 tmp = RREG32_MC(RS480_MC_MISC_CNTL); rs400_gart_enable() 181 tmp |= RS480_GART_INDEX_REG_EN; rs400_gart_enable() 182 WREG32_MC(RS480_MC_MISC_CNTL, tmp); rs400_gart_enable() 196 uint32_t tmp; rs400_gart_disable() local 198 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); rs400_gart_disable() 199 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; rs400_gart_disable() 200 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); rs400_gart_disable() 240 uint32_t tmp; rs400_mc_wait_for_idle() local 244 tmp = RREG32(RADEON_MC_STATUS); rs400_mc_wait_for_idle() 245 if (tmp & RADEON_MC_IDLE) { rs400_mc_wait_for_idle() 310 uint32_t tmp; rs400_debugfs_gart_info() local 312 tmp = RREG32(RADEON_HOST_PATH_CNTL); rs400_debugfs_gart_info() 313 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); rs400_debugfs_gart_info() 314 tmp = RREG32(RADEON_BUS_CNTL); rs400_debugfs_gart_info() 315 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); rs400_debugfs_gart_info() 316 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); rs400_debugfs_gart_info() 317 seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); rs400_debugfs_gart_info() 319 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); rs400_debugfs_gart_info() 320 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); rs400_debugfs_gart_info() 321 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); rs400_debugfs_gart_info() 322 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); rs400_debugfs_gart_info() 323 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); rs400_debugfs_gart_info() 324 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); rs400_debugfs_gart_info() 325 tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION); rs400_debugfs_gart_info() 326 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); rs400_debugfs_gart_info() 327 tmp = RREG32(RS690_HDP_FB_LOCATION); rs400_debugfs_gart_info() 328 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); rs400_debugfs_gart_info() 330 tmp = RREG32(RADEON_AGP_BASE); rs400_debugfs_gart_info() 331 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); rs400_debugfs_gart_info() 332 tmp = RREG32(RS480_AGP_BASE_2); rs400_debugfs_gart_info() 333 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); rs400_debugfs_gart_info() 334 tmp = RREG32(RADEON_MC_AGP_LOCATION); rs400_debugfs_gart_info() 335 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); rs400_debugfs_gart_info() 337 tmp = RREG32_MC(RS480_GART_BASE); rs400_debugfs_gart_info() 338 seq_printf(m, "GART_BASE 0x%08x\n", tmp); rs400_debugfs_gart_info() 339 tmp = RREG32_MC(RS480_GART_FEATURE_ID); rs400_debugfs_gart_info() 340 seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); rs400_debugfs_gart_info() 341 tmp = RREG32_MC(RS480_AGP_MODE_CNTL); rs400_debugfs_gart_info() 342 seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); rs400_debugfs_gart_info() 343 tmp = RREG32_MC(RS480_MC_MISC_CNTL); rs400_debugfs_gart_info() 344 seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); rs400_debugfs_gart_info() 345 tmp = RREG32_MC(0x5F); rs400_debugfs_gart_info() 346 seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); rs400_debugfs_gart_info() 347 tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); rs400_debugfs_gart_info() 348 seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); rs400_debugfs_gart_info() 349 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); rs400_debugfs_gart_info() 350 seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); rs400_debugfs_gart_info() 351 tmp = RREG32_MC(0x3B); rs400_debugfs_gart_info() 352 seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); rs400_debugfs_gart_info() 353 tmp = RREG32_MC(0x3C); rs400_debugfs_gart_info() 354 seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); rs400_debugfs_gart_info() 355 tmp = RREG32_MC(0x30); rs400_debugfs_gart_info() 356 seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); rs400_debugfs_gart_info() 357 tmp = RREG32_MC(0x31); rs400_debugfs_gart_info() 358 seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); rs400_debugfs_gart_info() 359 tmp = RREG32_MC(0x32); rs400_debugfs_gart_info() 360 seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); rs400_debugfs_gart_info() 361 tmp = RREG32_MC(0x33); rs400_debugfs_gart_info() 362 seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); rs400_debugfs_gart_info() 363 tmp = RREG32_MC(0x34); rs400_debugfs_gart_info() 364 seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); rs400_debugfs_gart_info() 365 tmp = RREG32_MC(0x35); rs400_debugfs_gart_info() 366 seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); rs400_debugfs_gart_info() 367 tmp = RREG32_MC(0x36); rs400_debugfs_gart_info() 368 seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); rs400_debugfs_gart_info() 369 tmp = RREG32_MC(0x37); rs400_debugfs_gart_info() 370 seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); rs400_debugfs_gart_info()
H A D	vce_v1_0.c	104 u32 tmp; vce_v1_0_enable_mgcg() local 107 tmp = RREG32(VCE_CLOCK_GATING_A); vce_v1_0_enable_mgcg() 108 tmp |= CGC_DYN_CLOCK_MODE; vce_v1_0_enable_mgcg() 109 WREG32(VCE_CLOCK_GATING_A, tmp); vce_v1_0_enable_mgcg() 111 tmp = RREG32(VCE_UENC_CLOCK_GATING); vce_v1_0_enable_mgcg() 112 tmp &= ~0x1ff000; vce_v1_0_enable_mgcg() 113 tmp |= 0xff800000; vce_v1_0_enable_mgcg() 114 WREG32(VCE_UENC_CLOCK_GATING, tmp); vce_v1_0_enable_mgcg() 116 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); vce_v1_0_enable_mgcg() 117 tmp &= ~0x3ff; vce_v1_0_enable_mgcg() 118 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); vce_v1_0_enable_mgcg() 120 tmp = RREG32(VCE_CLOCK_GATING_A); vce_v1_0_enable_mgcg() 121 tmp &= ~CGC_DYN_CLOCK_MODE; vce_v1_0_enable_mgcg() 122 WREG32(VCE_CLOCK_GATING_A, tmp); vce_v1_0_enable_mgcg() 124 tmp = RREG32(VCE_UENC_CLOCK_GATING); vce_v1_0_enable_mgcg() 125 tmp |= 0x1ff000; vce_v1_0_enable_mgcg() 126 tmp &= ~0xff800000; vce_v1_0_enable_mgcg() 127 WREG32(VCE_UENC_CLOCK_GATING, tmp); vce_v1_0_enable_mgcg() 129 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); vce_v1_0_enable_mgcg() 130 tmp |= 0x3ff; vce_v1_0_enable_mgcg() 131 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); vce_v1_0_enable_mgcg() 137 u32 tmp; vce_v1_0_init_cg() local 139 tmp = RREG32(VCE_CLOCK_GATING_A); vce_v1_0_init_cg() 140 tmp |= CGC_DYN_CLOCK_MODE; vce_v1_0_init_cg() 141 WREG32(VCE_CLOCK_GATING_A, tmp); vce_v1_0_init_cg() 143 tmp = RREG32(VCE_CLOCK_GATING_B); vce_v1_0_init_cg() 144 tmp |= 0x1e; vce_v1_0_init_cg() 145 tmp &= ~0xe100e1; vce_v1_0_init_cg() 146 WREG32(VCE_CLOCK_GATING_B, tmp); vce_v1_0_init_cg() 148 tmp = RREG32(VCE_UENC_CLOCK_GATING); vce_v1_0_init_cg() 149 tmp &= ~0xff9ff000; vce_v1_0_init_cg() 150 WREG32(VCE_UENC_CLOCK_GATING, tmp); vce_v1_0_init_cg() 152 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); vce_v1_0_init_cg() 153 tmp &= ~0x3ff; vce_v1_0_init_cg() 154 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); vce_v1_0_init_cg()
H A D	radeon_dp_auxch.c	62 uint32_t tmp, ack = 0; radeon_dp_aux_transfer_native() local 99 tmp = RREG32(chan->rec.mask_clk_reg); radeon_dp_aux_transfer_native() 100 tmp |= (1 << 16); radeon_dp_aux_transfer_native() 101 WREG32(chan->rec.mask_clk_reg, tmp); radeon_dp_aux_transfer_native() 104 tmp = RREG32(AUX_CONTROL + aux_offset[instance]); radeon_dp_aux_transfer_native() 106 tmp &= AUX_HPD_SEL(0x7); radeon_dp_aux_transfer_native() 107 tmp |= AUX_HPD_SEL(chan->rec.hpd); radeon_dp_aux_transfer_native() 108 tmp |= AUX_EN | AUX_LS_READ_EN | AUX_HPD_DISCON(0x1); radeon_dp_aux_transfer_native() 110 WREG32(AUX_CONTROL + aux_offset[instance], tmp); radeon_dp_aux_transfer_native() 153 tmp = RREG32(AUX_SW_STATUS + aux_offset[instance]); radeon_dp_aux_transfer_native() 154 if (tmp & AUX_SW_DONE) { radeon_dp_aux_transfer_native() 161 DRM_ERROR("auxch hw never signalled completion, error %08x\n", tmp); radeon_dp_aux_transfer_native() 166 if (tmp & AUX_SW_RX_TIMEOUT) { radeon_dp_aux_transfer_native() 171 if (tmp & AUX_RX_ERROR_FLAGS) { radeon_dp_aux_transfer_native() 172 DRM_DEBUG_KMS("dp_aux_ch flags not zero: %08x\n", tmp); radeon_dp_aux_transfer_native() 177 bytes = AUX_SW_REPLY_GET_BYTE_COUNT(tmp); radeon_dp_aux_transfer_native() 182 tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); radeon_dp_aux_transfer_native() 183 ack = (tmp >> 8) & 0xff; radeon_dp_aux_transfer_native() 186 tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); radeon_dp_aux_transfer_native() 188 buf[i] = (tmp >> 8) & 0xff; radeon_dp_aux_transfer_native()
H A D	dce6_afmt.c	64 u32 offset, tmp; dce6_afmt_get_connected_pins() local 68 tmp = RREG32_ENDPOINT(offset, dce6_afmt_get_connected_pins() 70 if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1) dce6_afmt_get_connected_pins() 130 u32 tmp = 0; dce6_afmt_write_latency_fields() local 137 tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | dce6_afmt_write_latency_fields() 140 tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); dce6_afmt_write_latency_fields() 143 tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | dce6_afmt_write_latency_fields() 146 tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); dce6_afmt_write_latency_fields() 149 AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); dce6_afmt_write_latency_fields() 158 u32 tmp; dce6_afmt_hdmi_write_speaker_allocation() local 164 tmp = RREG32_ENDPOINT(dig->pin->offset, dce6_afmt_hdmi_write_speaker_allocation() 166 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); dce6_afmt_hdmi_write_speaker_allocation() 168 tmp |= HDMI_CONNECTION; dce6_afmt_hdmi_write_speaker_allocation() 170 tmp |= SPEAKER_ALLOCATION(sadb[0]); dce6_afmt_hdmi_write_speaker_allocation() 172 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ dce6_afmt_hdmi_write_speaker_allocation() 174 AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); dce6_afmt_hdmi_write_speaker_allocation() 183 u32 tmp; dce6_afmt_dp_write_speaker_allocation() local 189 tmp = RREG32_ENDPOINT(dig->pin->offset, dce6_afmt_dp_write_speaker_allocation() 191 tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK); dce6_afmt_dp_write_speaker_allocation() 193 tmp |= DP_CONNECTION; dce6_afmt_dp_write_speaker_allocation() 195 tmp |= SPEAKER_ALLOCATION(sadb[0]); dce6_afmt_dp_write_speaker_allocation() 197 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ dce6_afmt_dp_write_speaker_allocation() 199 AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); dce6_afmt_dp_write_speaker_allocation()
H A D	r600.c	298 u32 tmp = 0; dce3_program_fmt() local 323 tmp |= FMT_SPATIAL_DITHER_EN; dce3_program_fmt() 325 tmp |= FMT_TRUNCATE_EN; dce3_program_fmt() 330 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); dce3_program_fmt() 332 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); dce3_program_fmt() 340 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); dce3_program_fmt() 856 u32 tmp; r600_hpd_set_polarity() local 862 tmp = RREG32(DC_HPD1_INT_CONTROL); r600_hpd_set_polarity() 864 tmp &= ~DC_HPDx_INT_POLARITY; r600_hpd_set_polarity() 866 tmp |= DC_HPDx_INT_POLARITY; r600_hpd_set_polarity() 867 WREG32(DC_HPD1_INT_CONTROL, tmp); r600_hpd_set_polarity() 870 tmp = RREG32(DC_HPD2_INT_CONTROL); r600_hpd_set_polarity() 872 tmp &= ~DC_HPDx_INT_POLARITY; r600_hpd_set_polarity() 874 tmp |= DC_HPDx_INT_POLARITY; r600_hpd_set_polarity() 875 WREG32(DC_HPD2_INT_CONTROL, tmp); r600_hpd_set_polarity() 878 tmp = RREG32(DC_HPD3_INT_CONTROL); r600_hpd_set_polarity() 880 tmp &= ~DC_HPDx_INT_POLARITY; r600_hpd_set_polarity() 882 tmp |= DC_HPDx_INT_POLARITY; r600_hpd_set_polarity() 883 WREG32(DC_HPD3_INT_CONTROL, tmp); r600_hpd_set_polarity() 886 tmp = RREG32(DC_HPD4_INT_CONTROL); r600_hpd_set_polarity() 888 tmp &= ~DC_HPDx_INT_POLARITY; r600_hpd_set_polarity() 890 tmp |= DC_HPDx_INT_POLARITY; r600_hpd_set_polarity() 891 WREG32(DC_HPD4_INT_CONTROL, tmp); r600_hpd_set_polarity() 894 tmp = RREG32(DC_HPD5_INT_CONTROL); r600_hpd_set_polarity() 896 tmp &= ~DC_HPDx_INT_POLARITY; r600_hpd_set_polarity() 898 tmp |= DC_HPDx_INT_POLARITY; r600_hpd_set_polarity() 899 WREG32(DC_HPD5_INT_CONTROL, tmp); r600_hpd_set_polarity() 903 tmp = RREG32(DC_HPD6_INT_CONTROL); r600_hpd_set_polarity() 905 tmp &= ~DC_HPDx_INT_POLARITY; r600_hpd_set_polarity() 907 tmp |= DC_HPDx_INT_POLARITY; r600_hpd_set_polarity() 908 WREG32(DC_HPD6_INT_CONTROL, tmp); r600_hpd_set_polarity() 916 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); r600_hpd_set_polarity() 918 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; r600_hpd_set_polarity() 920 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; r600_hpd_set_polarity() 921 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); r600_hpd_set_polarity() 924 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); r600_hpd_set_polarity() 926 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; r600_hpd_set_polarity() 928 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; r600_hpd_set_polarity() 929 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); r600_hpd_set_polarity() 932 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); r600_hpd_set_polarity() 934 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; r600_hpd_set_polarity() 936 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; r600_hpd_set_polarity() 937 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); r600_hpd_set_polarity() 963 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); r600_hpd_init() local 965 tmp |= DC_HPDx_EN; r600_hpd_init() 969 WREG32(DC_HPD1_CONTROL, tmp); r600_hpd_init() 972 WREG32(DC_HPD2_CONTROL, tmp); r600_hpd_init() 975 WREG32(DC_HPD3_CONTROL, tmp); r600_hpd_init() 978 WREG32(DC_HPD4_CONTROL, tmp); r600_hpd_init() 982 WREG32(DC_HPD5_CONTROL, tmp); r600_hpd_init() 985 WREG32(DC_HPD6_CONTROL, tmp); r600_hpd_init() 1069 u32 tmp; r600_pcie_gart_tlb_flush() local 1075 u32 tmp; r600_pcie_gart_tlb_flush() local 1083 tmp = readl((void __iomem *)ptr); r600_pcie_gart_tlb_flush() 1092 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); r600_pcie_gart_tlb_flush() 1093 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; r600_pcie_gart_tlb_flush() 1094 if (tmp == 2) { r600_pcie_gart_tlb_flush() 1098 if (tmp) { r600_pcie_gart_tlb_flush() 1123 u32 tmp; r600_pcie_gart_enable() local 1141 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | r600_pcie_gart_enable() 1145 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); r600_pcie_gart_enable() 1146 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); r600_pcie_gart_enable() 1147 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); r600_pcie_gart_enable() 1148 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); r600_pcie_gart_enable() 1149 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); r600_pcie_gart_enable() 1150 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); r600_pcie_gart_enable() 1151 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); r600_pcie_gart_enable() 1152 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); r600_pcie_gart_enable() 1153 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); r600_pcie_gart_enable() 1154 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); r600_pcie_gart_enable() 1155 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); r600_pcie_gart_enable() 1156 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); r600_pcie_gart_enable() 1157 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); r600_pcie_gart_enable() 1158 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); r600_pcie_gart_enable() 1159 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); r600_pcie_gart_enable() 1160 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); r600_pcie_gart_enable() 1181 u32 tmp; r600_pcie_gart_disable() local 1193 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | r600_pcie_gart_disable() 1195 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); r600_pcie_gart_disable() 1196 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); r600_pcie_gart_disable() 1197 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); r600_pcie_gart_disable() 1198 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); r600_pcie_gart_disable() 1199 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); r600_pcie_gart_disable() 1200 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); r600_pcie_gart_disable() 1201 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); r600_pcie_gart_disable() 1202 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); r600_pcie_gart_disable() 1203 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); r600_pcie_gart_disable() 1204 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); r600_pcie_gart_disable() 1205 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); r600_pcie_gart_disable() 1206 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); r600_pcie_gart_disable() 1207 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); r600_pcie_gart_disable() 1208 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); r600_pcie_gart_disable() 1209 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); r600_pcie_gart_disable() 1210 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); r600_pcie_gart_disable() 1223 u32 tmp; r600_agp_enable() local 1233 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | r600_agp_enable() 1237 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); r600_agp_enable() 1238 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); r600_agp_enable() 1239 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); r600_agp_enable() 1240 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); r600_agp_enable() 1241 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); r600_agp_enable() 1242 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); r600_agp_enable() 1243 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); r600_agp_enable() 1244 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); r600_agp_enable() 1245 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); r600_agp_enable() 1246 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); r600_agp_enable() 1247 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); r600_agp_enable() 1248 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); r600_agp_enable() 1249 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); r600_agp_enable() 1250 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); r600_agp_enable() 1258 u32 tmp; r600_mc_wait_for_idle() local 1262 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; r600_mc_wait_for_idle() 1263 if (!tmp) r600_mc_wait_for_idle() 1298 u32 tmp; r600_mc_program() local 1337 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; r600_mc_program() 1338 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); r600_mc_program() 1339 WREG32(MC_VM_FB_LOCATION, tmp); r600_mc_program() 1428 u32 tmp; r600_mc_init() local 1435 tmp = RREG32(RAMCFG); r600_mc_init() 1436 if (tmp & CHANSIZE_OVERRIDE) { r600_mc_init() 1438 } else if (tmp & CHANSIZE_MASK) { r600_mc_init() 1443 tmp = RREG32(CHMAP); r600_mc_init() 1444 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { r600_mc_init() 1549 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); r600_set_bios_scratch_engine_hung() local 1552 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; r600_set_bios_scratch_engine_hung() 1554 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; r600_set_bios_scratch_engine_hung() 1556 WREG32(R600_BIOS_3_SCRATCH, tmp); r600_set_bios_scratch_engine_hung() 1583 u32 i, j, tmp; r600_is_display_hung() local 1595 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); r600_is_display_hung() 1596 if (tmp != crtc_status[i]) r600_is_display_hung() 1611 u32 tmp; r600_gpu_check_soft_reset() local 1614 tmp = RREG32(R_008010_GRBM_STATUS); r600_gpu_check_soft_reset() 1616 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | r600_gpu_check_soft_reset() 1617 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | r600_gpu_check_soft_reset() 1618 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | r600_gpu_check_soft_reset() 1619 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | r600_gpu_check_soft_reset() 1620 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) r600_gpu_check_soft_reset() 1623 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | r600_gpu_check_soft_reset() 1624 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | r600_gpu_check_soft_reset() 1625 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | r600_gpu_check_soft_reset() 1626 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | r600_gpu_check_soft_reset() 1627 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) r600_gpu_check_soft_reset() 1631 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | r600_gpu_check_soft_reset() 1632 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) r600_gpu_check_soft_reset() 1635 if (G_008010_GRBM_EE_BUSY(tmp)) r600_gpu_check_soft_reset() 1639 tmp = RREG32(DMA_STATUS_REG); r600_gpu_check_soft_reset() 1640 if (!(tmp & DMA_IDLE)) r600_gpu_check_soft_reset() 1644 tmp = RREG32(R_000E50_SRBM_STATUS); r600_gpu_check_soft_reset() 1645 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) r600_gpu_check_soft_reset() 1648 if (G_000E50_IH_BUSY(tmp)) r600_gpu_check_soft_reset() 1651 if (G_000E50_SEM_BUSY(tmp)) r600_gpu_check_soft_reset() 1654 if (G_000E50_GRBM_RQ_PENDING(tmp)) r600_gpu_check_soft_reset() 1657 if (G_000E50_VMC_BUSY(tmp)) r600_gpu_check_soft_reset() 1660 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | r600_gpu_check_soft_reset() 1661 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | r600_gpu_check_soft_reset() 1662 G_000E50_MCDW_BUSY(tmp)) r600_gpu_check_soft_reset() 1681 u32 tmp; r600_gpu_soft_reset() local 1701 tmp = RREG32(DMA_RB_CNTL); r600_gpu_soft_reset() 1702 tmp &= ~DMA_RB_ENABLE; r600_gpu_soft_reset() 1703 WREG32(DMA_RB_CNTL, tmp); r600_gpu_soft_reset() 1777 tmp = RREG32(R_008020_GRBM_SOFT_RESET); r600_gpu_soft_reset() 1778 tmp |= grbm_soft_reset; r600_gpu_soft_reset() 1779 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); r600_gpu_soft_reset() 1780 WREG32(R_008020_GRBM_SOFT_RESET, tmp); r600_gpu_soft_reset() 1781 tmp = RREG32(R_008020_GRBM_SOFT_RESET); r600_gpu_soft_reset() 1785 tmp &= ~grbm_soft_reset; r600_gpu_soft_reset() 1786 WREG32(R_008020_GRBM_SOFT_RESET, tmp); r600_gpu_soft_reset() 1787 tmp = RREG32(R_008020_GRBM_SOFT_RESET); r600_gpu_soft_reset() 1791 tmp = RREG32(SRBM_SOFT_RESET); r600_gpu_soft_reset() 1792 tmp |= srbm_soft_reset; r600_gpu_soft_reset() 1793 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); r600_gpu_soft_reset() 1794 WREG32(SRBM_SOFT_RESET, tmp); r600_gpu_soft_reset() 1795 tmp = RREG32(SRBM_SOFT_RESET); r600_gpu_soft_reset() 1799 tmp &= ~srbm_soft_reset; r600_gpu_soft_reset() 1800 WREG32(SRBM_SOFT_RESET, tmp); r600_gpu_soft_reset() 1801 tmp = RREG32(SRBM_SOFT_RESET); r600_gpu_soft_reset() 1816 u32 tmp, i; r600_gpu_pci_config_reset() local 1832 tmp = RREG32(DMA_RB_CNTL); r600_gpu_pci_config_reset() 1833 tmp &= ~DMA_RB_ENABLE; r600_gpu_pci_config_reset() 1834 WREG32(DMA_RB_CNTL, tmp); r600_gpu_pci_config_reset() 1850 tmp = RREG32(BUS_CNTL); r600_gpu_pci_config_reset() 1851 tmp |= VGA_COHE_SPEC_TIMER_DIS; r600_gpu_pci_config_reset() 1852 WREG32(BUS_CNTL, tmp); r600_gpu_pci_config_reset() 1854 tmp = RREG32(BIF_SCRATCH0); r600_gpu_pci_config_reset() 1861 tmp = SOFT_RESET_BIF; r600_gpu_pci_config_reset() 1862 WREG32(SRBM_SOFT_RESET, tmp); r600_gpu_pci_config_reset() 1929 u32 pipe_rb_ratio, pipe_rb_remain, tmp; r6xx_remap_render_backend() local 1934 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); r6xx_remap_render_backend() 1936 if ((tmp & 0xff) != 0xff) r6xx_remap_render_backend() 1937 disabled_rb_mask = tmp; r6xx_remap_render_backend() 1982 u32 tmp; r600_gpu_init() local 2097 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; r600_gpu_init() 2098 if (tmp > 3) { r600_gpu_init() 2102 tiling_config |= ROW_TILING(tmp); r600_gpu_init() 2103 tiling_config |= SAMPLE_SPLIT(tmp); r600_gpu_init() 2108 tmp = rdev->config.r600.max_simds - r600_gpu_init() 2110 rdev->config.r600.active_simds = tmp; r600_gpu_init() 2113 tmp = 0; r600_gpu_init() 2115 tmp |= (1 << i); r600_gpu_init() 2117 if ((disabled_rb_mask & tmp) == tmp) { r600_gpu_init() 2121 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; r600_gpu_init() 2122 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, r600_gpu_init() 2124 tiling_config |= tmp << 16; r600_gpu_init() 2125 rdev->config.r600.backend_map = tmp; r600_gpu_init() 2133 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); r600_gpu_init() 2134 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); r600_gpu_init() 2135 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); r600_gpu_init() 2147 tmp = RREG32(SX_DEBUG_1); r600_gpu_init() 2148 tmp |= SMX_EVENT_RELEASE; r600_gpu_init() 2150 tmp |= ENABLE_NEW_SMX_ADDRESS; r600_gpu_init() 2151 WREG32(SX_DEBUG_1, tmp); r600_gpu_init() 2172 tmp = RREG32(SQ_MS_FIFO_SIZES); r600_gpu_init() 2177 tmp = (CACHE_FIFO_SIZE(0xa) | r600_gpu_init() 2183 tmp &= ~DONE_FIFO_HIWATER(0xff); r600_gpu_init() 2184 tmp |= DONE_FIFO_HIWATER(0x4); r600_gpu_init() 2186 WREG32(SQ_MS_FIFO_SIZES, tmp); r600_gpu_init() 2301 tmp = rdev->config.r600.max_pipes * 16; r600_gpu_init() 2307 tmp += 32; r600_gpu_init() 2310 tmp += 128; r600_gpu_init() 2315 if (tmp > 256) { r600_gpu_init() 2316 tmp = 256; r600_gpu_init() 2319 WREG32(VGT_GS_PER_ES, tmp); r600_gpu_init() 2350 tmp = TC_L2_SIZE(8); r600_gpu_init() 2354 tmp = TC_L2_SIZE(4); r600_gpu_init() 2357 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; r600_gpu_init() 2360 tmp = TC_L2_SIZE(0); r600_gpu_init() 2363 WREG32(TC_CNTL, tmp); r600_gpu_init() 2365 tmp = RREG32(HDP_HOST_PATH_CNTL); r600_gpu_init() 2366 WREG32(HDP_HOST_PATH_CNTL, tmp); r600_gpu_init() 2368 tmp = RREG32(ARB_POP); r600_gpu_init() 2369 tmp |= ENABLE_TC128; r600_gpu_init() 2370 WREG32(ARB_POP, tmp); r600_gpu_init() 2716 u32 tmp; r600_cp_resume() local 2728 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; r600_cp_resume() 2730 tmp |= BUF_SWAP_32BIT; r600_cp_resume() 2732 WREG32(CP_RB_CNTL, tmp); r600_cp_resume() 2739 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); r600_cp_resume() 2753 tmp |= RB_NO_UPDATE; r600_cp_resume() 2758 WREG32(CP_RB_CNTL, tmp); r600_cp_resume() 2823 uint32_t tmp = 0; r600_ring_test() local 2844 tmp = RREG32(scratch); r600_ring_test() 2845 if (tmp == 0xDEADBEEF) r600_ring_test() 2853 ring->idx, scratch, tmp); r600_ring_test() 2970 u32 size_in_bytes, cur_size_in_bytes, tmp; r600_copy_cpdma() local 2996 tmp = upper_32_bits(src_offset) & 0xff; r600_copy_cpdma() 2998 tmp |= PACKET3_CP_DMA_CP_SYNC; r600_copy_cpdma() 3001 radeon_ring_write(ring, tmp); r600_copy_cpdma() 3360 uint32_t tmp = 0; r600_ib_test() local 3390 tmp = RREG32(scratch); r600_ib_test() 3391 if (tmp == 0xDEADBEEF) r600_ib_test() 3399 scratch, tmp); r600_ib_test() 3574 u32 tmp; r600_disable_interrupt_state() local 3577 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; r600_disable_interrupt_state() 3578 WREG32(DMA_CNTL, tmp); r600_disable_interrupt_state() 3586 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; r600_disable_interrupt_state() 3587 WREG32(DC_HPD1_INT_CONTROL, tmp); r600_disable_interrupt_state() 3588 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; r600_disable_interrupt_state() 3589 WREG32(DC_HPD2_INT_CONTROL, tmp); r600_disable_interrupt_state() 3590 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; r600_disable_interrupt_state() 3591 WREG32(DC_HPD3_INT_CONTROL, tmp); r600_disable_interrupt_state() 3592 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; r600_disable_interrupt_state() 3593 WREG32(DC_HPD4_INT_CONTROL, tmp); r600_disable_interrupt_state() 3595 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; r600_disable_interrupt_state() 3596 WREG32(DC_HPD5_INT_CONTROL, tmp); r600_disable_interrupt_state() 3597 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; r600_disable_interrupt_state() 3598 WREG32(DC_HPD6_INT_CONTROL, tmp); r600_disable_interrupt_state() 3599 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; r600_disable_interrupt_state() 3600 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); r600_disable_interrupt_state() 3601 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; r600_disable_interrupt_state() 3602 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); r600_disable_interrupt_state() 3604 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; r600_disable_interrupt_state() 3605 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); r600_disable_interrupt_state() 3606 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; r600_disable_interrupt_state() 3607 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); r600_disable_interrupt_state() 3612 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; r600_disable_interrupt_state() 3613 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); r600_disable_interrupt_state() 3614 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; r600_disable_interrupt_state() 3615 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); r600_disable_interrupt_state() 3616 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; r600_disable_interrupt_state() 3617 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); r600_disable_interrupt_state() 3618 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; r600_disable_interrupt_state() 3619 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); r600_disable_interrupt_state() 3620 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; r600_disable_interrupt_state() 3621 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); r600_disable_interrupt_state() 3868 u32 tmp; r600_irq_ack() local 3905 tmp = RREG32(DC_HPD1_INT_CONTROL); r600_irq_ack() 3906 tmp |= DC_HPDx_INT_ACK; r600_irq_ack() 3907 WREG32(DC_HPD1_INT_CONTROL, tmp); r600_irq_ack() 3909 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); r600_irq_ack() 3910 tmp |= DC_HPDx_INT_ACK; r600_irq_ack() 3911 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); r600_irq_ack() 3916 tmp = RREG32(DC_HPD2_INT_CONTROL); r600_irq_ack() 3917 tmp |= DC_HPDx_INT_ACK; r600_irq_ack() 3918 WREG32(DC_HPD2_INT_CONTROL, tmp); r600_irq_ack() 3920 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); r600_irq_ack() 3921 tmp |= DC_HPDx_INT_ACK; r600_irq_ack() 3922 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); r600_irq_ack() 3927 tmp = RREG32(DC_HPD3_INT_CONTROL); r600_irq_ack() 3928 tmp |= DC_HPDx_INT_ACK; r600_irq_ack() 3929 WREG32(DC_HPD3_INT_CONTROL, tmp); r600_irq_ack() 3931 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); r600_irq_ack() 3932 tmp |= DC_HPDx_INT_ACK; r600_irq_ack() 3933 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); r600_irq_ack() 3937 tmp = RREG32(DC_HPD4_INT_CONTROL); r600_irq_ack() 3938 tmp |= DC_HPDx_INT_ACK; r600_irq_ack() 3939 WREG32(DC_HPD4_INT_CONTROL, tmp); r600_irq_ack() 3943 tmp = RREG32(DC_HPD5_INT_CONTROL); r600_irq_ack() 3944 tmp |= DC_HPDx_INT_ACK; r600_irq_ack() 3945 WREG32(DC_HPD5_INT_CONTROL, tmp); r600_irq_ack() 3948 tmp = RREG32(DC_HPD5_INT_CONTROL); r600_irq_ack() 3949 tmp |= DC_HPDx_INT_ACK; r600_irq_ack() 3950 WREG32(DC_HPD6_INT_CONTROL, tmp); r600_irq_ack() 3953 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); r600_irq_ack() 3954 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; r600_irq_ack() 3955 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); r600_irq_ack() 3958 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); r600_irq_ack() 3959 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; r600_irq_ack() 3960 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); r600_irq_ack() 3964 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); r600_irq_ack() 3965 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; r600_irq_ack() 3966 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); r600_irq_ack() 3970 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); r600_irq_ack() 3971 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; r600_irq_ack() 3972 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); r600_irq_ack() 3974 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); r600_irq_ack() 3975 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; r600_irq_ack() 3976 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); r600_irq_ack() 3993 u32 wptr, tmp; r600_get_ih_wptr() local 4009 tmp = RREG32(IH_RB_CNTL); r600_get_ih_wptr() 4010 tmp |= IH_WPTR_OVERFLOW_CLEAR; r600_get_ih_wptr() 4011 WREG32(IH_RB_CNTL, tmp); r600_get_ih_wptr() 4344 u32 tmp; r600_mmio_hdp_flush() local 4347 tmp = readl((void __iomem *)ptr); r600_mmio_hdp_flush() 4444 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; r600_pcie_gen2_enable() local 4520 tmp = RREG32(0x541c); r600_pcie_gen2_enable() 4521 WREG32(0x541c, tmp | 0x8); r600_pcie_gen2_enable()
H A D	r300.c	84 uint32_t tmp; rv370_pcie_gart_tlb_flush() local 89 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); rv370_pcie_gart_tlb_flush() 90 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); rv370_pcie_gart_tlb_flush() 92 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); rv370_pcie_gart_tlb_flush() 150 uint32_t tmp; rv370_pcie_gart_enable() local 161 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; rv370_pcie_gart_enable() 162 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); rv370_pcie_gart_enable() 164 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; rv370_pcie_gart_enable() 165 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); rv370_pcie_gart_enable() 175 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); rv370_pcie_gart_enable() 176 tmp |= RADEON_PCIE_TX_GART_EN; rv370_pcie_gart_enable() 177 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; rv370_pcie_gart_enable() 178 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); rv370_pcie_gart_enable() 189 u32 tmp; rv370_pcie_gart_disable() local 195 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); rv370_pcie_gart_disable() 196 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; rv370_pcie_gart_disable() 197 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); rv370_pcie_gart_disable() 345 uint32_t tmp; r300_mc_wait_for_idle() local 349 tmp = RREG32(RADEON_MC_STATUS); r300_mc_wait_for_idle() 350 if (tmp & R300_MC_IDLE) { r300_mc_wait_for_idle() 360 uint32_t gb_tile_config, tmp; r300_gpu_init() local 394 tmp = RREG32(R300_DST_PIPE_CONFIG); r300_gpu_init() 395 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); r300_gpu_init() 416 u32 status, tmp; r300_asic_reset() local 428 tmp = RREG32(RADEON_CP_RB_CNTL); r300_asic_reset() 429 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); r300_asic_reset() 432 WREG32(RADEON_CP_RB_CNTL, tmp); r300_asic_reset() 476 u32 tmp; r300_mc_init() local 480 tmp = RREG32(RADEON_MEM_CNTL); r300_mc_init() 481 tmp &= R300_MEM_NUM_CHANNELS_MASK; r300_mc_init() 482 switch (tmp) { r300_mc_init() 595 uint32_t tmp; rv370_debugfs_pcie_gart_info() local 597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); rv370_debugfs_pcie_gart_info() 598 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); rv370_debugfs_pcie_gart_info() 599 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); rv370_debugfs_pcie_gart_info() 600 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); rv370_debugfs_pcie_gart_info() 601 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); rv370_debugfs_pcie_gart_info() 602 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); rv370_debugfs_pcie_gart_info() 603 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); rv370_debugfs_pcie_gart_info() 604 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); rv370_debugfs_pcie_gart_info() 605 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); rv370_debugfs_pcie_gart_info() 606 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); rv370_debugfs_pcie_gart_info() 607 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); rv370_debugfs_pcie_gart_info() 608 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); rv370_debugfs_pcie_gart_info() 609 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); rv370_debugfs_pcie_gart_info() 610 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); rv370_debugfs_pcie_gart_info() 635 uint32_t tmp, tile_flags = 0; r300_packet0_check() local 727 tmp = idx_value + ((u32)reloc->gpu_offset); r300_packet0_check() 728 tmp |= tile_flags; r300_packet0_check() 729 ib[idx] = tmp; r300_packet0_check() 796 tmp = idx_value & ~(0x7 << 16); r300_packet0_check() 797 tmp |= tile_flags; r300_packet0_check() 798 ib[idx] = tmp; r300_packet0_check() 881 tmp = idx_value & ~(0x7 << 16); r300_packet0_check() 882 tmp |= tile_flags; r300_packet0_check() 883 ib[idx] = tmp; r300_packet0_check() 916 tmp = (idx_value >> 25) & 0x3; r300_packet0_check() 917 track->textures[i].tex_coord_type = tmp; r300_packet0_check() 1002 tmp = idx_value & 0x7; r300_packet0_check() 1003 if (tmp == 2 || tmp == 4 || tmp == 6) { r300_packet0_check() 1006 tmp = (idx_value >> 3) & 0x7; r300_packet0_check() 1007 if (tmp == 2 || tmp == 4 || tmp == 6) { r300_packet0_check() 1030 tmp = idx_value & 0x3FFF; r300_packet0_check() 1031 track->textures[i].pitch = tmp + 1; r300_packet0_check() 1033 tmp = ((idx_value >> 15) & 1) << 11; r300_packet0_check() 1034 track->textures[i].width_11 = tmp; r300_packet0_check() 1035 tmp = ((idx_value >> 16) & 1) << 11; r300_packet0_check() 1036 track->textures[i].height_11 = tmp; r300_packet0_check() 1068 tmp = idx_value & 0x7FF; r300_packet0_check() 1069 track->textures[i].width = tmp + 1; r300_packet0_check() 1070 tmp = (idx_value >> 11) & 0x7FF; r300_packet0_check() 1071 track->textures[i].height = tmp + 1; r300_packet0_check() 1072 tmp = (idx_value >> 26) & 0xF; r300_packet0_check() 1073 track->textures[i].num_levels = tmp; r300_packet0_check() 1074 tmp = idx_value & (1 << 31); r300_packet0_check() 1075 track->textures[i].use_pitch = !!tmp; r300_packet0_check() 1076 tmp = (idx_value >> 22) & 0xF; r300_packet0_check() 1077 track->textures[i].txdepth = tmp; r300_packet0_check() 1363 u32 tmp; r300_clock_startup() local 1368 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); r300_clock_startup() 1369 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); r300_clock_startup() 1371 tmp |= S_00000D_FORCE_VAP(1); r300_clock_startup() 1372 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); r300_clock_startup()
H A D	si_smc.c	115 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); si_start_smc() local 117 tmp &= ~RST_REG; si_start_smc() 119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); si_start_smc() 124 u32 tmp; si_reset_smc() local 131 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); si_reset_smc() 132 tmp |= RST_REG; si_reset_smc() 133 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); si_reset_smc() 145 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); si_stop_smc_clock() local 147 tmp |= CK_DISABLE; si_stop_smc_clock() 149 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); si_stop_smc_clock() 154 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); si_start_smc_clock() local 156 tmp &= ~CK_DISABLE; si_start_smc_clock() 158 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); si_start_smc_clock() 174 u32 tmp; si_send_msg_to_smc() local 183 tmp = RREG32(SMC_RESP_0); si_send_msg_to_smc() 184 if (tmp != 0) si_send_msg_to_smc() 188 tmp = RREG32(SMC_RESP_0); si_send_msg_to_smc() 190 return (PPSMC_Result)tmp; si_send_msg_to_smc() 195 u32 tmp; si_wait_for_smc_inactive() local 202 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); si_wait_for_smc_inactive() 203 if ((tmp & CKEN) == 0) si_wait_for_smc_inactive()
H A D	rs600.c	116 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); rs600_page_flip() local 120 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; rs600_page_flip() 121 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); rs600_page_flip() 138 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; rs600_page_flip() 139 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); rs600_page_flip() 158 u32 tmp = 0; avivo_program_fmt() local 178 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; avivo_program_fmt() 180 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN; avivo_program_fmt() 185 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN | avivo_program_fmt() 188 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN | avivo_program_fmt() 199 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp); avivo_program_fmt() 202 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp); avivo_program_fmt() 205 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp); avivo_program_fmt() 208 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp); avivo_program_fmt() 220 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl; rs600_pm_misc() local 225 tmp = RREG32(voltage->gpio.reg); rs600_pm_misc() 227 tmp |= voltage->gpio.mask; rs600_pm_misc() 229 tmp &= ~(voltage->gpio.mask); rs600_pm_misc() 230 WREG32(voltage->gpio.reg, tmp); rs600_pm_misc() 234 tmp = RREG32(voltage->gpio.reg); rs600_pm_misc() 236 tmp &= ~voltage->gpio.mask; rs600_pm_misc() 238 tmp |= voltage->gpio.mask; rs600_pm_misc() 239 WREG32(voltage->gpio.reg, tmp); rs600_pm_misc() 314 u32 tmp; rs600_pm_prepare() local 320 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); rs600_pm_prepare() 321 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; rs600_pm_prepare() 322 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); rs600_pm_prepare() 332 u32 tmp; rs600_pm_finish() local 338 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); rs600_pm_finish() 339 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; rs600_pm_finish() 340 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); rs600_pm_finish() 348 u32 tmp; rs600_hpd_sense() local 353 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); rs600_hpd_sense() 354 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) rs600_hpd_sense() 358 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); rs600_hpd_sense() 359 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) rs600_hpd_sense() 371 u32 tmp; rs600_hpd_set_polarity() local 376 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); rs600_hpd_set_polarity() 378 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); rs600_hpd_set_polarity() 380 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); rs600_hpd_set_polarity() 381 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); rs600_hpd_set_polarity() 384 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); rs600_hpd_set_polarity() 386 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); rs600_hpd_set_polarity() 388 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); rs600_hpd_set_polarity() 389 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); rs600_hpd_set_polarity() 450 u32 status, tmp; rs600_asic_reset() local 463 tmp = RREG32(RADEON_CP_RB_CNTL); rs600_asic_reset() 464 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); rs600_asic_reset() 467 WREG32(RADEON_CP_RB_CNTL, tmp); rs600_asic_reset() 514 uint32_t tmp; rs600_gart_tlb_flush() local 516 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); rs600_gart_tlb_flush() 517 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; rs600_gart_tlb_flush() 518 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); rs600_gart_tlb_flush() 520 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); rs600_gart_tlb_flush() 521 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); rs600_gart_tlb_flush() 522 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); rs600_gart_tlb_flush() 524 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); rs600_gart_tlb_flush() 525 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; rs600_gart_tlb_flush() 526 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); rs600_gart_tlb_flush() 527 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); rs600_gart_tlb_flush() 549 u32 tmp; rs600_gart_enable() local 560 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; rs600_gart_enable() 561 WREG32(RADEON_BUS_CNTL, tmp); rs600_gart_enable() 599 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); rs600_gart_enable() 600 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); rs600_gart_enable() 601 tmp = RREG32_MC(R_000009_MC_CNTL1); rs600_gart_enable() 602 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); rs600_gart_enable() 613 u32 tmp; rs600_gart_disable() local 617 tmp = RREG32_MC(R_000009_MC_CNTL1); rs600_gart_disable() 618 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); rs600_gart_disable() 653 uint32_t tmp = 0; rs600_irq_set() local 672 tmp |= S_000040_SW_INT_EN(1); rs600_irq_set() 691 WREG32(R_000040_GEN_INT_CNTL, tmp); rs600_irq_set() 708 u32 tmp; rs600_irq_ack() local 721 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); rs600_irq_ack() 722 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); rs600_irq_ack() 723 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); rs600_irq_ack() 726 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); rs600_irq_ack() 727 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); rs600_irq_ack() 728 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); rs600_irq_ack() 738 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); rs600_irq_ack() 739 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); rs600_irq_ack() 740 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); rs600_irq_ack()
H A D	ci_smc.c	116 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); ci_start_smc() local 118 tmp &= ~RST_REG; ci_start_smc() 119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); ci_start_smc() 124 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); ci_reset_smc() local 126 tmp |= RST_REG; ci_reset_smc() 127 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); ci_reset_smc() 139 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); ci_stop_smc_clock() local 141 tmp |= CK_DISABLE; ci_stop_smc_clock() 143 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); ci_stop_smc_clock() 148 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); ci_start_smc_clock() local 150 tmp &= ~CK_DISABLE; ci_start_smc_clock() 152 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); ci_start_smc_clock() 168 u32 tmp; ci_send_msg_to_smc() local 177 tmp = RREG32(SMC_RESP_0); ci_send_msg_to_smc() 178 if (tmp != 0) ci_send_msg_to_smc() 182 tmp = RREG32(SMC_RESP_0); ci_send_msg_to_smc() 184 return (PPSMC_Result)tmp; ci_send_msg_to_smc() 190 u32 tmp; 197 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 198 if ((tmp & CKEN) == 0)
H A D	evergreen.c	1295 u32 tmp = 0; dce4_program_fmt() local 1320 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE | dce4_program_fmt() 1323 tmp |= FMT_TRUNCATE_EN; dce4_program_fmt() 1328 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE | dce4_program_fmt() 1332 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); dce4_program_fmt() 1340 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); dce4_program_fmt() 1665 u32 tmp; evergreen_pm_prepare() local 1671 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); evergreen_pm_prepare() 1672 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; evergreen_pm_prepare() 1673 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); evergreen_pm_prepare() 1690 u32 tmp; evergreen_pm_finish() local 1696 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); evergreen_pm_finish() 1697 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; evergreen_pm_finish() 1698 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); evergreen_pm_finish() 1759 u32 tmp; evergreen_hpd_set_polarity() local 1764 tmp = RREG32(DC_HPD1_INT_CONTROL); evergreen_hpd_set_polarity() 1766 tmp &= ~DC_HPDx_INT_POLARITY; evergreen_hpd_set_polarity() 1768 tmp |= DC_HPDx_INT_POLARITY; evergreen_hpd_set_polarity() 1769 WREG32(DC_HPD1_INT_CONTROL, tmp); evergreen_hpd_set_polarity() 1772 tmp = RREG32(DC_HPD2_INT_CONTROL); evergreen_hpd_set_polarity() 1774 tmp &= ~DC_HPDx_INT_POLARITY; evergreen_hpd_set_polarity() 1776 tmp |= DC_HPDx_INT_POLARITY; evergreen_hpd_set_polarity() 1777 WREG32(DC_HPD2_INT_CONTROL, tmp); evergreen_hpd_set_polarity() 1780 tmp = RREG32(DC_HPD3_INT_CONTROL); evergreen_hpd_set_polarity() 1782 tmp &= ~DC_HPDx_INT_POLARITY; evergreen_hpd_set_polarity() 1784 tmp |= DC_HPDx_INT_POLARITY; evergreen_hpd_set_polarity() 1785 WREG32(DC_HPD3_INT_CONTROL, tmp); evergreen_hpd_set_polarity() 1788 tmp = RREG32(DC_HPD4_INT_CONTROL); evergreen_hpd_set_polarity() 1790 tmp &= ~DC_HPDx_INT_POLARITY; evergreen_hpd_set_polarity() 1792 tmp |= DC_HPDx_INT_POLARITY; evergreen_hpd_set_polarity() 1793 WREG32(DC_HPD4_INT_CONTROL, tmp); evergreen_hpd_set_polarity() 1796 tmp = RREG32(DC_HPD5_INT_CONTROL); evergreen_hpd_set_polarity() 1798 tmp &= ~DC_HPDx_INT_POLARITY; evergreen_hpd_set_polarity() 1800 tmp |= DC_HPDx_INT_POLARITY; evergreen_hpd_set_polarity() 1801 WREG32(DC_HPD5_INT_CONTROL, tmp); evergreen_hpd_set_polarity() 1804 tmp = RREG32(DC_HPD6_INT_CONTROL); evergreen_hpd_set_polarity() 1806 tmp &= ~DC_HPDx_INT_POLARITY; evergreen_hpd_set_polarity() 1808 tmp |= DC_HPDx_INT_POLARITY; evergreen_hpd_set_polarity() 1809 WREG32(DC_HPD6_INT_CONTROL, tmp); evergreen_hpd_set_polarity() 1829 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | evergreen_hpd_init() local 1846 WREG32(DC_HPD1_CONTROL, tmp); evergreen_hpd_init() 1849 WREG32(DC_HPD2_CONTROL, tmp); evergreen_hpd_init() 1852 WREG32(DC_HPD3_CONTROL, tmp); evergreen_hpd_init() 1855 WREG32(DC_HPD4_CONTROL, tmp); evergreen_hpd_init() 1858 WREG32(DC_HPD5_CONTROL, tmp); evergreen_hpd_init() 1861 WREG32(DC_HPD6_CONTROL, tmp); evergreen_hpd_init() 1922 u32 tmp, buffer_alloc, i; evergreen_line_buffer_adjust() local 1947 tmp = 0; /* 1/2 */ evergreen_line_buffer_adjust() 1950 tmp = 2; /* whole */ evergreen_line_buffer_adjust() 1954 tmp = 0; evergreen_line_buffer_adjust() 1960 tmp += 4; evergreen_line_buffer_adjust() 1961 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); evergreen_line_buffer_adjust() 1975 switch (tmp) { evergreen_line_buffer_adjust() 2010 u32 tmp = RREG32(MC_SHARED_CHMAP); evergreen_get_number_of_dram_channels() local 2012 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { evergreen_get_number_of_dram_channels() 2266 u32 tmp, arb_control3; evergreen_program_watermarks() local 2382 tmp = arb_control3; evergreen_program_watermarks() 2383 tmp &= ~LATENCY_WATERMARK_MASK(3); evergreen_program_watermarks() 2384 tmp |= LATENCY_WATERMARK_MASK(1); evergreen_program_watermarks() 2385 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); evergreen_program_watermarks() 2390 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); evergreen_program_watermarks() 2391 tmp &= ~LATENCY_WATERMARK_MASK(3); evergreen_program_watermarks() 2392 tmp |= LATENCY_WATERMARK_MASK(2); evergreen_program_watermarks() 2393 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); evergreen_program_watermarks() 2456 u32 tmp; evergreen_mc_wait_for_idle() local 2460 tmp = RREG32(SRBM_STATUS) & 0x1F00; evergreen_mc_wait_for_idle() 2461 if (!tmp) evergreen_mc_wait_for_idle() 2474 u32 tmp; evergreen_pcie_gart_tlb_flush() local 2481 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); evergreen_pcie_gart_tlb_flush() 2482 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; evergreen_pcie_gart_tlb_flush() 2483 if (tmp == 2) { evergreen_pcie_gart_tlb_flush() 2487 if (tmp) { evergreen_pcie_gart_tlb_flush() 2496 u32 tmp; evergreen_pcie_gart_enable() local 2513 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | evergreen_pcie_gart_enable() 2518 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp); evergreen_pcie_gart_enable() 2519 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp); evergreen_pcie_gart_enable() 2520 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp); evergreen_pcie_gart_enable() 2522 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); evergreen_pcie_gart_enable() 2523 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); evergreen_pcie_gart_enable() 2524 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); evergreen_pcie_gart_enable() 2529 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); evergreen_pcie_gart_enable() 2531 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); evergreen_pcie_gart_enable() 2532 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); evergreen_pcie_gart_enable() 2533 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); evergreen_pcie_gart_enable() 2534 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); evergreen_pcie_gart_enable() 2554 u32 tmp; evergreen_pcie_gart_disable() local 2566 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); evergreen_pcie_gart_disable() 2567 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); evergreen_pcie_gart_disable() 2568 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); evergreen_pcie_gart_disable() 2569 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); evergreen_pcie_gart_disable() 2570 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); evergreen_pcie_gart_disable() 2571 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); evergreen_pcie_gart_disable() 2572 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); evergreen_pcie_gart_disable() 2573 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); evergreen_pcie_gart_disable() 2587 u32 tmp; evergreen_agp_enable() local 2596 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | evergreen_agp_enable() 2600 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); evergreen_agp_enable() 2601 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); evergreen_agp_enable() 2602 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); evergreen_agp_enable() 2603 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); evergreen_agp_enable() 2604 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); evergreen_agp_enable() 2605 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); evergreen_agp_enable() 2606 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); evergreen_agp_enable() 2754 u32 crtc_enabled, tmp, frame_count, blackout; evergreen_mc_stop() local 2771 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); evergreen_mc_stop() 2772 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) { evergreen_mc_stop() 2775 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; evergreen_mc_stop() 2776 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); evergreen_mc_stop() 2780 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); evergreen_mc_stop() 2781 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) { evergreen_mc_stop() 2784 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; evergreen_mc_stop() 2785 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); evergreen_mc_stop() 2809 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); evergreen_mc_stop() 2810 tmp &= ~EVERGREEN_CRTC_MASTER_EN; evergreen_mc_stop() 2811 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); evergreen_mc_stop() 2836 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); evergreen_mc_stop() 2837 if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) { evergreen_mc_stop() 2838 tmp |= EVERGREEN_GRPH_UPDATE_LOCK; evergreen_mc_stop() 2839 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); evergreen_mc_stop() 2841 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); evergreen_mc_stop() 2842 if (!(tmp & 1)) { evergreen_mc_stop() 2843 tmp |= 1; evergreen_mc_stop() 2844 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); evergreen_mc_stop() 2852 u32 tmp, frame_count; evergreen_mc_resume() local 2875 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]); evergreen_mc_resume() 2876 if ((tmp & 0x7) != 3) { evergreen_mc_resume() 2877 tmp &= ~0x7; evergreen_mc_resume() 2878 tmp |= 0x3; evergreen_mc_resume() 2879 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); evergreen_mc_resume() 2881 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); evergreen_mc_resume() 2882 if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) { evergreen_mc_resume() 2883 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; evergreen_mc_resume() 2884 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); evergreen_mc_resume() 2886 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); evergreen_mc_resume() 2887 if (tmp & 1) { evergreen_mc_resume() 2888 tmp &= ~1; evergreen_mc_resume() 2889 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); evergreen_mc_resume() 2892 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); evergreen_mc_resume() 2893 if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0) evergreen_mc_resume() 2901 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); evergreen_mc_resume() 2902 tmp &= ~BLACKOUT_MODE_MASK; evergreen_mc_resume() 2903 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp); evergreen_mc_resume() 2910 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); evergreen_mc_resume() 2911 tmp &= ~EVERGREEN_CRTC_BLANK_DATA_EN; evergreen_mc_resume() 2913 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); evergreen_mc_resume() 2916 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); evergreen_mc_resume() 2917 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; evergreen_mc_resume() 2919 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); evergreen_mc_resume() 2942 u32 tmp; evergreen_mc_program() local 2987 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF; evergreen_mc_program() 2988 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24; evergreen_mc_program() 2989 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20; evergreen_mc_program() 2990 WREG32(MC_FUS_VM_FB_OFFSET, tmp); evergreen_mc_program() 2992 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; evergreen_mc_program() 2993 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); evergreen_mc_program() 2994 WREG32(MC_VM_FB_LOCATION, tmp); evergreen_mc_program() 3155 u32 tmp; evergreen_cp_resume() local 3173 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; evergreen_cp_resume() 3175 tmp |= BUF_SWAP_32BIT; evergreen_cp_resume() 3177 WREG32(CP_RB_CNTL, tmp); evergreen_cp_resume() 3185 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); evergreen_cp_resume() 3199 tmp |= RB_NO_UPDATE; evergreen_cp_resume() 3204 WREG32(CP_RB_CNTL, tmp); evergreen_cp_resume() 3239 u32 hdp_host_path_cntl, tmp; evergreen_gpu_init() local 3547 tmp = (((efuse_straps_4 & 0xf) << 4) | evergreen_gpu_init() 3550 tmp = 0; evergreen_gpu_init() 3557 tmp <<= 4; evergreen_gpu_init() 3558 tmp |= rb_disable_bitmap; evergreen_gpu_init() 3562 disabled_rb_mask = tmp; evergreen_gpu_init() 3563 tmp = 0; evergreen_gpu_init() 3565 tmp |= (1 << i); evergreen_gpu_init() 3567 if ((disabled_rb_mask & tmp) == tmp) { evergreen_gpu_init() 3579 tmp <<= 16; evergreen_gpu_init() 3580 tmp |= simd_disable_bitmap; evergreen_gpu_init() 3582 rdev->config.evergreen.active_simds = hweight32(~tmp); evergreen_gpu_init() 3599 tmp = 0x11111111; evergreen_gpu_init() 3602 tmp = 0x00000000; evergreen_gpu_init() 3605 tmp = gb_addr_config & NUM_PIPES_MASK; evergreen_gpu_init() 3606 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends, evergreen_gpu_init() 3609 WREG32(GB_BACKEND_MAP, tmp); evergreen_gpu_init() 3785 tmp = RREG32(HDP_MISC_CNTL); evergreen_gpu_init() 3786 tmp |= HDP_FLUSH_INVALIDATE_CACHE; evergreen_gpu_init() 3787 WREG32(HDP_MISC_CNTL, tmp); evergreen_gpu_init() 3800 u32 tmp; evergreen_mc_init() local 3808 tmp = RREG32(FUS_MC_ARB_RAMCFG); evergreen_mc_init() 3810 tmp = RREG32(MC_ARB_RAMCFG); evergreen_mc_init() 3811 if (tmp & CHANSIZE_OVERRIDE) { evergreen_mc_init() 3813 } else if (tmp & CHANSIZE_MASK) { evergreen_mc_init() 3818 tmp = RREG32(MC_SHARED_CHMAP); evergreen_mc_init() 3819 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { evergreen_mc_init() 3889 u32 i, j, tmp; evergreen_is_display_hung() local 3901 tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]); evergreen_is_display_hung() 3902 if (tmp != crtc_status[i]) evergreen_is_display_hung() 3917 u32 tmp; evergreen_gpu_check_soft_reset() local 3920 tmp = RREG32(GRBM_STATUS); evergreen_gpu_check_soft_reset() 3921 if (tmp & (PA_BUSY | SC_BUSY | evergreen_gpu_check_soft_reset() 3928 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING | evergreen_gpu_check_soft_reset() 3932 if (tmp & GRBM_EE_BUSY) evergreen_gpu_check_soft_reset() 3936 tmp = RREG32(DMA_STATUS_REG); evergreen_gpu_check_soft_reset() 3937 if (!(tmp & DMA_IDLE)) evergreen_gpu_check_soft_reset() 3941 tmp = RREG32(SRBM_STATUS2); evergreen_gpu_check_soft_reset() 3942 if (tmp & DMA_BUSY) evergreen_gpu_check_soft_reset() 3946 tmp = RREG32(SRBM_STATUS); evergreen_gpu_check_soft_reset() 3947 if (tmp & (RLC_RQ_PENDING | RLC_BUSY)) evergreen_gpu_check_soft_reset() 3950 if (tmp & IH_BUSY) evergreen_gpu_check_soft_reset() 3953 if (tmp & SEM_BUSY) evergreen_gpu_check_soft_reset() 3956 if (tmp & GRBM_RQ_PENDING) evergreen_gpu_check_soft_reset() 3959 if (tmp & VMC_BUSY) evergreen_gpu_check_soft_reset() 3962 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY | evergreen_gpu_check_soft_reset() 3970 tmp = RREG32(VM_L2_STATUS); evergreen_gpu_check_soft_reset() 3971 if (tmp & L2_BUSY) evergreen_gpu_check_soft_reset() 3987 u32 tmp; evergreen_gpu_soft_reset() local 4001 tmp = RREG32(DMA_RB_CNTL); evergreen_gpu_soft_reset() 4002 tmp &= ~DMA_RB_ENABLE; evergreen_gpu_soft_reset() 4003 WREG32(DMA_RB_CNTL, tmp); evergreen_gpu_soft_reset() 4061 tmp = RREG32(GRBM_SOFT_RESET); evergreen_gpu_soft_reset() 4062 tmp |= grbm_soft_reset; evergreen_gpu_soft_reset() 4063 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); evergreen_gpu_soft_reset() 4064 WREG32(GRBM_SOFT_RESET, tmp); evergreen_gpu_soft_reset() 4065 tmp = RREG32(GRBM_SOFT_RESET); evergreen_gpu_soft_reset() 4069 tmp &= ~grbm_soft_reset; evergreen_gpu_soft_reset() 4070 WREG32(GRBM_SOFT_RESET, tmp); evergreen_gpu_soft_reset() 4071 tmp = RREG32(GRBM_SOFT_RESET); evergreen_gpu_soft_reset() 4075 tmp = RREG32(SRBM_SOFT_RESET); evergreen_gpu_soft_reset() 4076 tmp |= srbm_soft_reset; evergreen_gpu_soft_reset() 4077 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); evergreen_gpu_soft_reset() 4078 WREG32(SRBM_SOFT_RESET, tmp); evergreen_gpu_soft_reset() 4079 tmp = RREG32(SRBM_SOFT_RESET); evergreen_gpu_soft_reset() 4083 tmp &= ~srbm_soft_reset; evergreen_gpu_soft_reset() 4084 WREG32(SRBM_SOFT_RESET, tmp); evergreen_gpu_soft_reset() 4085 tmp = RREG32(SRBM_SOFT_RESET); evergreen_gpu_soft_reset() 4100 u32 tmp, i; evergreen_gpu_pci_config_reset() local 4110 tmp = RREG32(DMA_RB_CNTL); evergreen_gpu_pci_config_reset() 4111 tmp &= ~DMA_RB_ENABLE; evergreen_gpu_pci_config_reset() 4112 WREG32(DMA_RB_CNTL, tmp); evergreen_gpu_pci_config_reset() 4481 u32 tmp = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; evergreen_rlc_resume() local 4482 tmp |= 0xffffffff << rdev->config.cayman.max_simds_per_se; evergreen_rlc_resume() 4483 tmp = hweight32(~tmp); evergreen_rlc_resume() 4484 if (tmp == rdev->config.cayman.max_simds_per_se) { evergreen_rlc_resume() 4543 u32 tmp; evergreen_disable_interrupt_state() local 4550 tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; evergreen_disable_interrupt_state() 4551 WREG32(CAYMAN_DMA1_CNTL, tmp); evergreen_disable_interrupt_state() 4554 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; evergreen_disable_interrupt_state() 4555 WREG32(DMA_CNTL, tmp); evergreen_disable_interrupt_state() 4585 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; evergreen_disable_interrupt_state() 4586 WREG32(DC_HPD1_INT_CONTROL, tmp); evergreen_disable_interrupt_state() 4587 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; evergreen_disable_interrupt_state() 4588 WREG32(DC_HPD2_INT_CONTROL, tmp); evergreen_disable_interrupt_state() 4589 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; evergreen_disable_interrupt_state() 4590 WREG32(DC_HPD3_INT_CONTROL, tmp); evergreen_disable_interrupt_state() 4591 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; evergreen_disable_interrupt_state() 4592 WREG32(DC_HPD4_INT_CONTROL, tmp); evergreen_disable_interrupt_state() 4593 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; evergreen_disable_interrupt_state() 4594 WREG32(DC_HPD5_INT_CONTROL, tmp); evergreen_disable_interrupt_state() 4595 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; evergreen_disable_interrupt_state() 4596 WREG32(DC_HPD6_INT_CONTROL, tmp); evergreen_disable_interrupt_state() 4832 u32 tmp; evergreen_irq_ack() local 4902 tmp = RREG32(DC_HPD1_INT_CONTROL); evergreen_irq_ack() 4903 tmp |= DC_HPDx_INT_ACK; evergreen_irq_ack() 4904 WREG32(DC_HPD1_INT_CONTROL, tmp); evergreen_irq_ack() 4907 tmp = RREG32(DC_HPD2_INT_CONTROL); evergreen_irq_ack() 4908 tmp |= DC_HPDx_INT_ACK; evergreen_irq_ack() 4909 WREG32(DC_HPD2_INT_CONTROL, tmp); evergreen_irq_ack() 4912 tmp = RREG32(DC_HPD3_INT_CONTROL); evergreen_irq_ack() 4913 tmp |= DC_HPDx_INT_ACK; evergreen_irq_ack() 4914 WREG32(DC_HPD3_INT_CONTROL, tmp); evergreen_irq_ack() 4917 tmp = RREG32(DC_HPD4_INT_CONTROL); evergreen_irq_ack() 4918 tmp |= DC_HPDx_INT_ACK; evergreen_irq_ack() 4919 WREG32(DC_HPD4_INT_CONTROL, tmp); evergreen_irq_ack() 4922 tmp = RREG32(DC_HPD5_INT_CONTROL); evergreen_irq_ack() 4923 tmp |= DC_HPDx_INT_ACK; evergreen_irq_ack() 4924 WREG32(DC_HPD5_INT_CONTROL, tmp); evergreen_irq_ack() 4927 tmp = RREG32(DC_HPD5_INT_CONTROL); evergreen_irq_ack() 4928 tmp |= DC_HPDx_INT_ACK; evergreen_irq_ack() 4929 WREG32(DC_HPD6_INT_CONTROL, tmp); evergreen_irq_ack() 4933 tmp = RREG32(DC_HPD1_INT_CONTROL); evergreen_irq_ack() 4934 tmp |= DC_HPDx_RX_INT_ACK; evergreen_irq_ack() 4935 WREG32(DC_HPD1_INT_CONTROL, tmp); evergreen_irq_ack() 4938 tmp = RREG32(DC_HPD2_INT_CONTROL); evergreen_irq_ack() 4939 tmp |= DC_HPDx_RX_INT_ACK; evergreen_irq_ack() 4940 WREG32(DC_HPD2_INT_CONTROL, tmp); evergreen_irq_ack() 4943 tmp = RREG32(DC_HPD3_INT_CONTROL); evergreen_irq_ack() 4944 tmp |= DC_HPDx_RX_INT_ACK; evergreen_irq_ack() 4945 WREG32(DC_HPD3_INT_CONTROL, tmp); evergreen_irq_ack() 4948 tmp = RREG32(DC_HPD4_INT_CONTROL); evergreen_irq_ack() 4949 tmp |= DC_HPDx_RX_INT_ACK; evergreen_irq_ack() 4950 WREG32(DC_HPD4_INT_CONTROL, tmp); evergreen_irq_ack() 4953 tmp = RREG32(DC_HPD5_INT_CONTROL); evergreen_irq_ack() 4954 tmp |= DC_HPDx_RX_INT_ACK; evergreen_irq_ack() 4955 WREG32(DC_HPD5_INT_CONTROL, tmp); evergreen_irq_ack() 4958 tmp = RREG32(DC_HPD5_INT_CONTROL); evergreen_irq_ack() 4959 tmp |= DC_HPDx_RX_INT_ACK; evergreen_irq_ack() 4960 WREG32(DC_HPD6_INT_CONTROL, tmp); evergreen_irq_ack() 4964 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); evergreen_irq_ack() 4965 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; evergreen_irq_ack() 4966 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp); evergreen_irq_ack() 4969 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); evergreen_irq_ack() 4970 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; evergreen_irq_ack() 4971 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp); evergreen_irq_ack() 4974 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); evergreen_irq_ack() 4975 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; evergreen_irq_ack() 4976 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp); evergreen_irq_ack() 4979 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); evergreen_irq_ack() 4980 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; evergreen_irq_ack() 4981 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp); evergreen_irq_ack() 4984 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); evergreen_irq_ack() 4985 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; evergreen_irq_ack() 4986 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp); evergreen_irq_ack() 4989 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); evergreen_irq_ack() 4990 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; evergreen_irq_ack() 4991 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp); evergreen_irq_ack() 5012 u32 wptr, tmp; evergreen_get_ih_wptr() local 5028 tmp = RREG32(IH_RB_CNTL); evergreen_get_ih_wptr() 5029 tmp |= IH_WPTR_OVERFLOW_CLEAR; evergreen_get_ih_wptr() 5030 WREG32(IH_RB_CNTL, tmp); evergreen_get_ih_wptr()
H A D	rv515.c	133 uint32_t tmp; rv515_mc_wait_for_idle() local 137 tmp = RREG32_MC(MC_STATUS); rv515_mc_wait_for_idle() 138 if (tmp & MC_STATUS_IDLE) { rv515_mc_wait_for_idle() 154 unsigned pipe_select_current, gb_pipe_select, tmp; rv515_gpu_init() local 163 tmp = RREG32(R300_DST_PIPE_CONFIG); rv515_gpu_init() 164 pipe_select_current = (tmp >> 2) & 3; rv515_gpu_init() 165 tmp = (1 << pipe_select_current) | rv515_gpu_init() 167 WREG32_PLL(0x000D, tmp); rv515_gpu_init() 180 uint32_t tmp; rv515_vram_get_type() local 184 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; rv515_vram_get_type() 185 switch (tmp) { rv515_vram_get_type() 241 uint32_t tmp; rv515_debugfs_pipes_info() local 243 tmp = RREG32(GB_PIPE_SELECT); rv515_debugfs_pipes_info() 244 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); rv515_debugfs_pipes_info() 245 tmp = RREG32(SU_REG_DEST); rv515_debugfs_pipes_info() 246 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); rv515_debugfs_pipes_info() 247 tmp = RREG32(GB_TILE_CONFIG); rv515_debugfs_pipes_info() 248 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); rv515_debugfs_pipes_info() 249 tmp = RREG32(DST_PIPE_CONFIG); rv515_debugfs_pipes_info() 250 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); rv515_debugfs_pipes_info() 259 uint32_t tmp; rv515_debugfs_ga_info() local 261 tmp = RREG32(0x2140); rv515_debugfs_ga_info() 262 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); rv515_debugfs_ga_info() 264 tmp = RREG32(0x425C); rv515_debugfs_ga_info() 265 seq_printf(m, "GA_IDLE 0x%08x\n", tmp); rv515_debugfs_ga_info() 298 u32 crtc_enabled, tmp, frame_count, blackout; rv515_mc_stop() local 311 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); rv515_mc_stop() 312 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { rv515_mc_stop() 315 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; rv515_mc_stop() 316 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); rv515_mc_stop() 329 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); rv515_mc_stop() 330 tmp &= ~AVIVO_CRTC_EN; rv515_mc_stop() 331 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); rv515_mc_stop() 364 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); rv515_mc_stop() 365 if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) { rv515_mc_stop() 366 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; rv515_mc_stop() 367 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); rv515_mc_stop() 369 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); rv515_mc_stop() 370 if (!(tmp & 1)) { rv515_mc_stop() 371 tmp |= 1; rv515_mc_stop() 372 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); rv515_mc_stop() 380 u32 tmp, frame_count; rv515_mc_resume() local 408 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); rv515_mc_resume() 409 if ((tmp & 0x7) != 3) { rv515_mc_resume() 410 tmp &= ~0x7; rv515_mc_resume() 411 tmp |= 0x3; rv515_mc_resume() 412 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); rv515_mc_resume() 414 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); rv515_mc_resume() 415 if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) { rv515_mc_resume() 416 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; rv515_mc_resume() 417 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); rv515_mc_resume() 419 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); rv515_mc_resume() 420 if (tmp & 1) { rv515_mc_resume() 421 tmp &= ~1; rv515_mc_resume() 422 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); rv515_mc_resume() 425 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); rv515_mc_resume() 426 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0) rv515_mc_resume() 436 tmp = RREG32(R700_MC_CITF_CNTL); rv515_mc_resume() 438 tmp = RREG32(R600_CITF_CNTL); rv515_mc_resume() 439 tmp &= ~R600_BLACKOUT_MASK; rv515_mc_resume() 441 WREG32(R700_MC_CITF_CNTL, tmp); rv515_mc_resume() 443 WREG32(R600_CITF_CNTL, tmp); rv515_mc_resume() 450 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); rv515_mc_resume() 451 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; rv515_mc_resume() 452 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); rv515_mc_resume() 1239 u32 tmp; rv515_bandwidth_avivo_update() local 1255 tmp = wm0_high.lb_request_fifo_depth; rv515_bandwidth_avivo_update() 1256 tmp |= wm1_high.lb_request_fifo_depth << 16; rv515_bandwidth_avivo_update() 1257 WREG32(LB_MAX_REQ_OUTSTANDING, tmp); rv515_bandwidth_avivo_update() 1276 uint32_t tmp; rv515_bandwidth_update() local 1296 tmp = RREG32_MC(MC_MISC_LAT_TIMER); rv515_bandwidth_update() 1297 tmp &= ~MC_DISP1R_INIT_LAT_MASK; rv515_bandwidth_update() 1298 tmp &= ~MC_DISP0R_INIT_LAT_MASK; rv515_bandwidth_update() 1300 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); rv515_bandwidth_update() 1302 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); rv515_bandwidth_update() 1303 WREG32_MC(MC_MISC_LAT_TIMER, tmp); rv515_bandwidth_update()
/linux-4.4.14/arch/arm/mach-zx/
H A D	zx296702-pm-domain.c	42 u32 tmp; normal_power_off() local 44 tmp = readl_relaxed(pcubase + PCU_DM_CLKEN); normal_power_off() 45 tmp &= ~BIT(zpd->bit); normal_power_off() 46 writel_relaxed(tmp, pcubase + PCU_DM_CLKEN); normal_power_off() 49 tmp = readl_relaxed(pcubase + PCU_DM_ISOEN); normal_power_off() 50 tmp &= ~BIT(zpd->bit); normal_power_off() 51 writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_ISOEN); normal_power_off() 54 tmp = readl_relaxed(pcubase + PCU_DM_RSTEN); normal_power_off() 55 tmp &= ~BIT(zpd->bit); normal_power_off() 56 writel_relaxed(tmp, pcubase + PCU_DM_RSTEN); normal_power_off() 59 tmp = readl_relaxed(pcubase + PCU_DM_PWRDN); normal_power_off() 60 tmp &= ~BIT(zpd->bit); normal_power_off() 61 writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_PWRDN); normal_power_off() 63 tmp = readl_relaxed(pcubase + PCU_DM_ACK_SYNC) & BIT(zpd->bit); normal_power_off() 64 } while (--loop && !tmp); normal_power_off() 78 u32 tmp; normal_power_on() local 80 tmp = readl_relaxed(pcubase + PCU_DM_PWRDN); normal_power_on() 81 tmp &= ~BIT(zpd->bit); normal_power_on() 82 writel_relaxed(tmp, pcubase + PCU_DM_PWRDN); normal_power_on() 84 tmp = readl_relaxed(pcubase + PCU_DM_ACK_SYNC) & BIT(zpd->bit); normal_power_on() 85 } while (--loop && tmp); normal_power_on() 92 tmp = readl_relaxed(pcubase + PCU_DM_RSTEN); normal_power_on() 93 tmp &= ~BIT(zpd->bit); normal_power_on() 94 writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_RSTEN); normal_power_on() 97 tmp = readl_relaxed(pcubase + PCU_DM_ISOEN); normal_power_on() 98 tmp &= ~BIT(zpd->bit); normal_power_on() 99 writel_relaxed(tmp, pcubase + PCU_DM_ISOEN); normal_power_on() 102 tmp = readl_relaxed(pcubase + PCU_DM_CLKEN); normal_power_on() 103 tmp &= ~BIT(zpd->bit); normal_power_on() 104 writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_CLKEN); normal_power_on()
/linux-4.4.14/arch/alpha/math-emu/
H A D	qrnnd.S	41 #define tmp $3 define 52 $loop1: cmplt n0,0,tmp 54 bis n1,tmp,n1 57 subq n1,d,tmp 58 cmovne qb,tmp,n1 60 cmplt n0,0,tmp 62 bis n1,tmp,n1 65 subq n1,d,tmp 66 cmovne qb,tmp,n1 68 cmplt n0,0,tmp 70 bis n1,tmp,n1 73 subq n1,d,tmp 74 cmovne qb,tmp,n1 76 cmplt n0,0,tmp 78 bis n1,tmp,n1 81 subq n1,d,tmp 82 cmovne qb,tmp,n1 94 sll n1,63,tmp 95 or tmp,n0,n0 102 $loop2: cmplt n0,0,tmp 104 bis n1,tmp,n1 107 subq n1,$5,tmp 108 cmovne qb,tmp,n1 110 cmplt n0,0,tmp 112 bis n1,tmp,n1 115 subq n1,$5,tmp 116 cmovne qb,tmp,n1 118 cmplt n0,0,tmp 120 bis n1,tmp,n1 123 subq n1,$5,tmp 124 cmovne qb,tmp,n1 126 cmplt n0,0,tmp 128 bis n1,tmp,n1 131 subq n1,$5,tmp 132 cmovne qb,tmp,n1 148 cmpult n1,n0,tmp # tmp := carry from addq 150 addq n0,tmp,n0 151 cmovne tmp,AT,n1 153 cmpult n1,d,tmp 155 cmoveq tmp,AT,n0 157 cmoveq tmp,AT,n1
/linux-4.4.14/drivers/scsi/mvsas/
H A D	mv_64xx.c	47 u32 tmp; mvs_64xx_enable_xmt() local 49 tmp = mr32(MVS_PCS); mvs_64xx_enable_xmt() 51 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT); mvs_64xx_enable_xmt() 53 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); mvs_64xx_enable_xmt() 54 mw32(MVS_PCS, tmp); mvs_64xx_enable_xmt() 86 u32 reg, tmp; mvs_64xx_stp_reset() local 97 tmp = reg; mvs_64xx_stp_reset() 99 tmp |= (1U << phy_id) << PCTL_LINK_OFFS; mvs_64xx_stp_reset() 101 tmp |= (1U << (phy_id - MVS_SOC_PORTS)) << PCTL_LINK_OFFS; mvs_64xx_stp_reset() 105 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); mvs_64xx_stp_reset() 109 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); mvs_64xx_stp_reset() 114 mw32(MVS_PHY_CTL, tmp); mvs_64xx_stp_reset() 122 u32 tmp; mvs_64xx_phy_reset() local 123 tmp = mvs_read_port_irq_stat(mvi, phy_id); mvs_64xx_phy_reset() 124 tmp &= ~PHYEV_RDY_CH; mvs_64xx_phy_reset() 125 mvs_write_port_irq_stat(mvi, phy_id, tmp); mvs_64xx_phy_reset() 126 tmp = mvs_read_phy_ctl(mvi, phy_id); mvs_64xx_phy_reset() 128 tmp |= PHY_RST_HARD; mvs_64xx_phy_reset() 130 tmp |= PHY_RST; mvs_64xx_phy_reset() 131 mvs_write_phy_ctl(mvi, phy_id, tmp); mvs_64xx_phy_reset() 134 tmp = mvs_read_phy_ctl(mvi, phy_id); mvs_64xx_phy_reset() 135 } while (tmp & PHY_RST_HARD); mvs_64xx_phy_reset() 142 u32 tmp; mvs_64xx_clear_srs_irq() local 144 tmp = mr32(MVS_INT_STAT_SRS_0); mvs_64xx_clear_srs_irq() 145 if (tmp) { mvs_64xx_clear_srs_irq() 146 printk(KERN_DEBUG "check SRS 0 %08X.\n", tmp); mvs_64xx_clear_srs_irq() 147 mw32(MVS_INT_STAT_SRS_0, tmp); mvs_64xx_clear_srs_irq() 150 tmp = mr32(MVS_INT_STAT_SRS_0); mvs_64xx_clear_srs_irq() 151 if (tmp & (1 << (reg_set % 32))) { mvs_64xx_clear_srs_irq() 162 u32 tmp; mvs_64xx_chip_reset() local 167 tmp = mr32(MVS_GBL_CTL); mvs_64xx_chip_reset() 170 if (!(tmp & HBA_RST)) { mvs_64xx_chip_reset() 172 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp); mvs_64xx_chip_reset() 173 tmp &= ~PCTL_PWR_OFF; mvs_64xx_chip_reset() 174 tmp |= PCTL_PHY_DSBL; mvs_64xx_chip_reset() 175 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); mvs_64xx_chip_reset() 177 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp); mvs_64xx_chip_reset() 178 tmp &= ~PCTL_PWR_OFF; mvs_64xx_chip_reset() 179 tmp |= PCTL_PHY_DSBL; mvs_64xx_chip_reset() 180 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); mvs_64xx_chip_reset() 186 tmp = mr32(MVS_GBL_CTL); mvs_64xx_chip_reset() 189 if (!(tmp & HBA_RST)) { mvs_64xx_chip_reset() 212 u32 tmp; mvs_64xx_phy_disable() local 221 pci_read_config_dword(mvi->pdev, offs, &tmp); mvs_64xx_phy_disable() 222 tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id); mvs_64xx_phy_disable() 223 pci_write_config_dword(mvi->pdev, offs, tmp); mvs_64xx_phy_disable() 225 tmp = mr32(MVS_PHY_CTL); mvs_64xx_phy_disable() 226 tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id); mvs_64xx_phy_disable() 227 mw32(MVS_PHY_CTL, tmp); mvs_64xx_phy_disable() 234 u32 tmp; mvs_64xx_phy_enable() local 243 pci_read_config_dword(mvi->pdev, offs, &tmp); mvs_64xx_phy_enable() 244 tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id)); mvs_64xx_phy_enable() 245 pci_write_config_dword(mvi->pdev, offs, tmp); mvs_64xx_phy_enable() 247 tmp = mr32(MVS_PHY_CTL); mvs_64xx_phy_enable() 248 tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id)); mvs_64xx_phy_enable() 249 mw32(MVS_PHY_CTL, tmp); mvs_64xx_phy_enable() 257 u32 tmp, cctl; mvs_64xx_init() local 263 tmp = mvs_64xx_chip_reset(mvi); mvs_64xx_init() 264 if (tmp) mvs_64xx_init() 265 return tmp; mvs_64xx_init() 267 tmp = mr32(MVS_PHY_CTL); mvs_64xx_init() 268 tmp &= ~PCTL_PWR_OFF; mvs_64xx_init() 269 tmp |= PCTL_PHY_DSBL; mvs_64xx_init() 270 mw32(MVS_PHY_CTL, tmp); mvs_64xx_init() 283 pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp); mvs_64xx_init() 284 tmp &= ~PRD_REQ_MASK; mvs_64xx_init() 285 tmp |= PRD_REQ_SIZE; mvs_64xx_init() 286 pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp); mvs_64xx_init() 288 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp); mvs_64xx_init() 289 tmp &= ~PCTL_PWR_OFF; mvs_64xx_init() 290 tmp &= ~PCTL_PHY_DSBL; mvs_64xx_init() 291 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); mvs_64xx_init() 293 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp); mvs_64xx_init() 294 tmp &= PCTL_PWR_OFF; mvs_64xx_init() 295 tmp &= ~PCTL_PHY_DSBL; mvs_64xx_init() 296 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); mvs_64xx_init() 298 tmp = mr32(MVS_PHY_CTL); mvs_64xx_init() 299 tmp &= ~PCTL_PWR_OFF; mvs_64xx_init() 300 tmp |= PCTL_COM_ON; mvs_64xx_init() 301 tmp &= ~PCTL_PHY_DSBL; mvs_64xx_init() 302 tmp |= PCTL_LINK_RST; mvs_64xx_init() 303 mw32(MVS_PHY_CTL, tmp); mvs_64xx_init() 305 tmp &= ~PCTL_LINK_RST; mvs_64xx_init() 306 mw32(MVS_PHY_CTL, tmp); mvs_64xx_init() 315 tmp = mvs_cr32(mvi, CMD_PHY_MODE_21); mvs_64xx_init() 316 tmp &= 0x0000ffff; mvs_64xx_init() 317 tmp |= 0x00fa0000; mvs_64xx_init() 318 mvs_cw32(mvi, CMD_PHY_MODE_21, tmp); mvs_64xx_init() 362 tmp = mvs_read_port_irq_stat(mvi, i); mvs_64xx_init() 363 tmp &= ~PHYEV_SIG_FIS; mvs_64xx_init() 364 mvs_write_port_irq_stat(mvi, i, tmp); mvs_64xx_init() 367 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | PHYEV_UNASSOC_FIS | mvs_64xx_init() 370 mvs_write_port_irq_mask(mvi, i, tmp); mvs_64xx_init() 385 tmp = mr32(MVS_PCS); mvs_64xx_init() 386 tmp |= PCS_CMD_RST; mvs_64xx_init() 387 tmp &= ~PCS_SELF_CLEAR; mvs_64xx_init() 388 mw32(MVS_PCS, tmp); mvs_64xx_init() 393 tmp = 0; mvs_64xx_init() 399 tmp = 0x10000 | interrupt_coalescing; mvs_64xx_init() 400 mw32(MVS_INT_COAL_TMOUT, tmp); mvs_64xx_init() 411 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP | mvs_64xx_init() 414 mw32(MVS_INT_MASK, tmp); mvs_64xx_init() 438 u32 tmp; mvs_64xx_interrupt_enable() local 440 tmp = mr32(MVS_GBL_CTL); mvs_64xx_interrupt_enable() 441 mw32(MVS_GBL_CTL, tmp | INT_EN); mvs_64xx_interrupt_enable() 447 u32 tmp; mvs_64xx_interrupt_disable() local 449 tmp = mr32(MVS_GBL_CTL); mvs_64xx_interrupt_disable() 450 mw32(MVS_GBL_CTL, tmp & ~INT_EN); mvs_64xx_interrupt_disable() 484 u32 tmp; mvs_64xx_command_active() local 488 tmp = mvs_cr32(mvi, 0x00 + (slot_idx >> 3)); mvs_64xx_command_active() 489 } while (tmp & 1 << (slot_idx % 32)); mvs_64xx_command_active() 491 tmp = mvs_cr32(mvi, 0x40 + (slot_idx >> 3)); mvs_64xx_command_active() 492 } while (tmp & 1 << (slot_idx % 32)); mvs_64xx_command_active() 499 u32 tmp; mvs_64xx_issue_stop() local 502 tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs); mvs_64xx_issue_stop() 503 mw32(MVS_INT_STAT_SRS_0, tmp); mvs_64xx_issue_stop() 506 tmp = mr32(MVS_PCS) | 0xFF00; mvs_64xx_issue_stop() 507 mw32(MVS_PCS, tmp); mvs_64xx_issue_stop() 513 u32 tmp, offs; mvs_64xx_free_reg_set() local 520 tmp = mr32(MVS_PCS); mvs_64xx_free_reg_set() 521 mw32(MVS_PCS, tmp & ~offs); mvs_64xx_free_reg_set() 523 tmp = mr32(MVS_CTL); mvs_64xx_free_reg_set() 524 mw32(MVS_CTL, tmp & ~offs); mvs_64xx_free_reg_set() 527 tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << *tfs); mvs_64xx_free_reg_set() 528 if (tmp) mvs_64xx_free_reg_set() 529 mw32(MVS_INT_STAT_SRS_0, tmp); mvs_64xx_free_reg_set() 538 u32 tmp, offs; mvs_64xx_assign_reg_set() local 544 tmp = mr32(MVS_PCS); mvs_64xx_assign_reg_set() 548 tmp = mr32(MVS_CTL); mvs_64xx_assign_reg_set() 550 if (!(tmp & offs)) { mvs_64xx_assign_reg_set() 554 mw32(MVS_PCS, tmp | offs); mvs_64xx_assign_reg_set() 556 mw32(MVS_CTL, tmp | offs); mvs_64xx_assign_reg_set() 557 tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << i); mvs_64xx_assign_reg_set() 558 if (tmp) mvs_64xx_assign_reg_set() 559 mw32(MVS_INT_STAT_SRS_0, tmp); mvs_64xx_assign_reg_set() 623 u32 tmp; mvs_64xx_phy_work_around() local 626 tmp = mvs_read_port_vsr_data(mvi, i); mvs_64xx_phy_work_around() 630 tmp &= ~PHY_MODE6_LATECLK; mvs_64xx_phy_work_around() 632 tmp |= PHY_MODE6_LATECLK; mvs_64xx_phy_work_around() 633 mvs_write_port_vsr_data(mvi, i, tmp); mvs_64xx_phy_work_around() 640 u32 tmp; mvs_64xx_phy_set_link_rate() local 642 tmp = mvs_read_phy_ctl(mvi, phy_id); mvs_64xx_phy_set_link_rate() 647 tmp &= ~(0xf << 8); mvs_64xx_phy_set_link_rate() 648 tmp |= lrmin; mvs_64xx_phy_set_link_rate() 651 tmp &= ~(0xf << 12); mvs_64xx_phy_set_link_rate() 652 tmp |= lrmax; mvs_64xx_phy_set_link_rate() 654 mvs_write_phy_ctl(mvi, phy_id, tmp); mvs_64xx_phy_set_link_rate() 660 u32 tmp; mvs_64xx_clear_active_cmds() local 662 tmp = mr32(MVS_PCS); mvs_64xx_clear_active_cmds() 663 mw32(MVS_PCS, tmp & 0xFFFF); mvs_64xx_clear_active_cmds() 664 mw32(MVS_PCS, tmp); mvs_64xx_clear_active_cmds() 665 tmp = mr32(MVS_CTL); mvs_64xx_clear_active_cmds() 666 mw32(MVS_CTL, tmp & 0xFFFF); mvs_64xx_clear_active_cmds() 667 mw32(MVS_CTL, tmp); mvs_64xx_clear_active_cmds() 756 u32 tmp = 0; mvs_64xx_tune_interrupt() local 770 tmp = 0x10000 | time; mvs_64xx_tune_interrupt() 771 mw32(MVS_INT_COAL_TMOUT, tmp); mvs_64xx_tune_interrupt()
H A D	mv_94xx.c	54 u32 tmp, setting_0 = 0, setting_1 = 0; set_phy_tuning() local 97 tmp = mvs_read_port_vsr_data(mvi, phy_id); set_phy_tuning() 98 tmp &= ~(0xFBE << 16); set_phy_tuning() 99 tmp |= (((phy_tuning.trans_emp_en << 11) | set_phy_tuning() 102 mvs_write_port_vsr_data(mvi, phy_id, tmp); set_phy_tuning() 106 tmp = mvs_read_port_vsr_data(mvi, phy_id); set_phy_tuning() 107 tmp &= ~(0xC000); set_phy_tuning() 108 tmp |= (phy_tuning.trans_amp_adj << 14); set_phy_tuning() 109 mvs_write_port_vsr_data(mvi, phy_id, tmp); set_phy_tuning() 116 u32 tmp; set_phy_ffe_tuning() local 131 tmp = mvs_read_port_vsr_data(mvi, phy_id); set_phy_ffe_tuning() 132 tmp &= ~0xFF; set_phy_ffe_tuning() 135 tmp |= ((0x1 << 7) | set_phy_ffe_tuning() 139 mvs_write_port_vsr_data(mvi, phy_id, tmp); set_phy_ffe_tuning() 146 tmp = mvs_read_port_vsr_data(mvi, phy_id); set_phy_ffe_tuning() 147 tmp &= ~0x40001; set_phy_ffe_tuning() 150 tmp |= (0 << 18); set_phy_ffe_tuning() 151 mvs_write_port_vsr_data(mvi, phy_id, tmp); set_phy_ffe_tuning() 159 tmp = mvs_read_port_vsr_data(mvi, phy_id); set_phy_ffe_tuning() 160 tmp &= ~0xFFF; set_phy_ffe_tuning() 163 tmp |= ((0x3F << 6) | (0x0 << 0)); set_phy_ffe_tuning() 164 mvs_write_port_vsr_data(mvi, phy_id, tmp); set_phy_ffe_tuning() 171 tmp = mvs_read_port_vsr_data(mvi, phy_id); set_phy_ffe_tuning() 172 tmp &= ~0x8; set_phy_ffe_tuning() 175 tmp |= (0 << 3); set_phy_ffe_tuning() 176 mvs_write_port_vsr_data(mvi, phy_id, tmp); set_phy_ffe_tuning() 263 u32 tmp; mvs_94xx_enable_xmt() local 265 tmp = mr32(MVS_PCS); mvs_94xx_enable_xmt() 266 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); mvs_94xx_enable_xmt() 267 mw32(MVS_PCS, tmp); mvs_94xx_enable_xmt() 272 u32 tmp; mvs_94xx_phy_reset() local 276 tmp = mvs_read_port_cfg_data(mvi, phy_id); mvs_94xx_phy_reset() 277 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x20000000); mvs_94xx_phy_reset() 278 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x100000); mvs_94xx_phy_reset() 281 tmp = mvs_read_port_irq_stat(mvi, phy_id); mvs_94xx_phy_reset() 282 tmp &= ~PHYEV_RDY_CH; mvs_94xx_phy_reset() 283 mvs_write_port_irq_stat(mvi, phy_id, tmp); mvs_94xx_phy_reset() 285 tmp = mvs_read_phy_ctl(mvi, phy_id); mvs_94xx_phy_reset() 286 tmp |= PHY_RST_HARD; mvs_94xx_phy_reset() 287 mvs_write_phy_ctl(mvi, phy_id, tmp); mvs_94xx_phy_reset() 289 tmp = mvs_read_phy_ctl(mvi, phy_id); mvs_94xx_phy_reset() 292 } while ((tmp & PHY_RST_HARD) && delay); mvs_94xx_phy_reset() 296 tmp = mvs_read_phy_ctl(mvi, phy_id); mvs_94xx_phy_reset() 297 tmp |= PHY_RST; mvs_94xx_phy_reset() 298 mvs_write_phy_ctl(mvi, phy_id, tmp); mvs_94xx_phy_reset() 304 u32 tmp; mvs_94xx_phy_disable() local 306 tmp = mvs_read_port_vsr_data(mvi, phy_id); mvs_94xx_phy_disable() 307 mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000); mvs_94xx_phy_disable() 312 u32 tmp; mvs_94xx_phy_enable() local 328 tmp = mvs_read_port_vsr_data(mvi, phy_id); mvs_94xx_phy_enable() 329 tmp |= bit(0); mvs_94xx_phy_enable() 330 mvs_write_port_vsr_data(mvi, phy_id, tmp & 0xfd7fffff); mvs_94xx_phy_enable() 337 u32 tmp, cctl; mvs_94xx_init() local 343 tmp = mr32(MVS_PHY_CTL); mvs_94xx_init() 344 tmp &= ~PCTL_PWR_OFF; mvs_94xx_init() 345 tmp |= PCTL_PHY_DSBL; mvs_94xx_init() 346 mw32(MVS_PHY_CTL, tmp); mvs_94xx_init() 358 tmp = mr32(MVS_PHY_CTL); mvs_94xx_init() 359 tmp &= ~PCTL_PWR_OFF; mvs_94xx_init() 360 tmp |= PCTL_COM_ON; mvs_94xx_init() 361 tmp &= ~PCTL_PHY_DSBL; mvs_94xx_init() 362 tmp |= PCTL_LINK_RST; mvs_94xx_init() 363 mw32(MVS_PHY_CTL, tmp); mvs_94xx_init() 365 tmp &= ~PCTL_LINK_RST; mvs_94xx_init() 366 mw32(MVS_PHY_CTL, tmp); mvs_94xx_init() 401 tmp = mvs_cr32(mvi, CMD_SAS_CTL1); mvs_94xx_init() 405 tmp &= ~0xffff; mvs_94xx_init() 406 tmp |= 0x007f; mvs_94xx_init() 407 mvs_cw32(mvi, CMD_SAS_CTL1, tmp); mvs_94xx_init() 412 tmp = mr32(MVS_PA_VSR_PORT); mvs_94xx_init() 413 tmp &= 0xFFFF00FF; mvs_94xx_init() 414 tmp |= 0x00003300; mvs_94xx_init() 415 mw32(MVS_PA_VSR_PORT, tmp); mvs_94xx_init() 459 tmp = mvs_read_port_irq_stat(mvi, i); mvs_94xx_init() 460 tmp &= ~PHYEV_SIG_FIS; mvs_94xx_init() 461 mvs_write_port_irq_stat(mvi, i, tmp); mvs_94xx_init() 464 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | mvs_94xx_init() 466 mvs_write_port_irq_mask(mvi, i, tmp); mvs_94xx_init() 480 tmp = mr32(MVS_PCS); mvs_94xx_init() 481 tmp |= PCS_CMD_RST; mvs_94xx_init() 482 tmp &= ~PCS_SELF_CLEAR; mvs_94xx_init() 483 mw32(MVS_PCS, tmp); mvs_94xx_init() 488 tmp = 0; mvs_94xx_init() 495 tmp = 0x10000 | interrupt_coalescing; mvs_94xx_init() 496 mw32(MVS_INT_COAL_TMOUT, tmp); mvs_94xx_init() 507 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP | mvs_94xx_init() 509 tmp |= CINT_PHY_MASK; mvs_94xx_init() 510 mw32(MVS_INT_MASK, tmp); mvs_94xx_init() 512 tmp = mvs_cr32(mvi, CMD_LINK_TIMER); mvs_94xx_init() 513 tmp |= 0xFFFF0000; mvs_94xx_init() 514 mvs_cw32(mvi, CMD_LINK_TIMER, tmp); mvs_94xx_init() 517 tmp = 0x003F003F; mvs_94xx_init() 518 mvs_cw32(mvi, CMD_PL_TIMER, tmp); mvs_94xx_init() 521 tmp = mvs_cr32(mvi, CMD_PORT_LAYER_TIMER1); mvs_94xx_init() 522 tmp |= 0xFFFF007F; mvs_94xx_init() 523 mvs_cw32(mvi, CMD_PORT_LAYER_TIMER1, tmp); mvs_94xx_init() 527 tmp = mvs_cr32(mvi, CMD_SL_MODE0); mvs_94xx_init() 528 tmp |= 0x00000300; mvs_94xx_init() 530 tmp &= 0xFFFFFFFE; mvs_94xx_init() 531 mvs_cw32(mvi, CMD_SL_MODE0, tmp); mvs_94xx_init() 564 u32 tmp; mvs_94xx_interrupt_enable() local 566 tmp = mr32(MVS_GBL_CTL); mvs_94xx_interrupt_enable() 567 tmp |= (MVS_IRQ_SAS_A | MVS_IRQ_SAS_B); mvs_94xx_interrupt_enable() 568 mw32(MVS_GBL_INT_STAT, tmp); mvs_94xx_interrupt_enable() 569 writel(tmp, regs + 0x0C); mvs_94xx_interrupt_enable() 570 writel(tmp, regs + 0x10); mvs_94xx_interrupt_enable() 571 writel(tmp, regs + 0x14); mvs_94xx_interrupt_enable() 572 writel(tmp, regs + 0x18); mvs_94xx_interrupt_enable() 573 mw32(MVS_GBL_CTL, tmp); mvs_94xx_interrupt_enable() 579 u32 tmp; mvs_94xx_interrupt_disable() local 581 tmp = mr32(MVS_GBL_CTL); mvs_94xx_interrupt_disable() 583 tmp &= ~(MVS_IRQ_SAS_A | MVS_IRQ_SAS_B); mvs_94xx_interrupt_disable() 584 mw32(MVS_GBL_INT_STAT, tmp); mvs_94xx_interrupt_disable() 585 writel(tmp, regs + 0x0C); mvs_94xx_interrupt_disable() 586 writel(tmp, regs + 0x10); mvs_94xx_interrupt_disable() 587 writel(tmp, regs + 0x14); mvs_94xx_interrupt_disable() 588 writel(tmp, regs + 0x18); mvs_94xx_interrupt_disable() 589 mw32(MVS_GBL_CTL, tmp); mvs_94xx_interrupt_disable() 622 u32 tmp; mvs_94xx_command_active() local 623 tmp = mvs_cr32(mvi, MVS_COMMAND_ACTIVE+(slot_idx >> 3)); mvs_94xx_command_active() 624 if (tmp && 1 << (slot_idx % 32)) { mvs_94xx_command_active() 625 mv_printk("command active %08X, slot [%x].\n", tmp, slot_idx); mvs_94xx_command_active() 629 tmp = mvs_cr32(mvi, mvs_94xx_command_active() 631 } while (tmp & 1 << (slot_idx % 32)); mvs_94xx_command_active() 638 u32 tmp; mvs_94xx_clear_srs_irq() local 641 tmp = mr32(MVS_INT_STAT_SRS_0); mvs_94xx_clear_srs_irq() 642 if (tmp) { mvs_94xx_clear_srs_irq() 643 mv_dprintk("check SRS 0 %08X.\n", tmp); mvs_94xx_clear_srs_irq() 644 mw32(MVS_INT_STAT_SRS_0, tmp); mvs_94xx_clear_srs_irq() 646 tmp = mr32(MVS_INT_STAT_SRS_1); mvs_94xx_clear_srs_irq() 647 if (tmp) { mvs_94xx_clear_srs_irq() 648 mv_dprintk("check SRS 1 %08X.\n", tmp); mvs_94xx_clear_srs_irq() 649 mw32(MVS_INT_STAT_SRS_1, tmp); mvs_94xx_clear_srs_irq() 653 tmp = mr32(MVS_INT_STAT_SRS_1); mvs_94xx_clear_srs_irq() 655 tmp = mr32(MVS_INT_STAT_SRS_0); mvs_94xx_clear_srs_irq() 657 if (tmp & (1 << (reg_set % 32))) { mvs_94xx_clear_srs_irq() 671 u32 tmp; mvs_94xx_issue_stop() local 674 tmp = mr32(MVS_INT_STAT); mvs_94xx_issue_stop() 675 mw32(MVS_INT_STAT, tmp | CINT_CI_STOP); mvs_94xx_issue_stop() 676 tmp = mr32(MVS_PCS) | 0xFF00; mvs_94xx_issue_stop() 677 mw32(MVS_PCS, tmp); mvs_94xx_issue_stop() 866 u32 tmp; mvs_94xx_phy_set_link_rate() local 868 tmp = mvs_read_phy_ctl(mvi, phy_id); mvs_94xx_phy_set_link_rate() 872 tmp &= ~(0x3 << 12); mvs_94xx_phy_set_link_rate() 873 tmp |= lrmax; mvs_94xx_phy_set_link_rate() 875 mvs_write_phy_ctl(mvi, phy_id, tmp); mvs_94xx_phy_set_link_rate() 881 u32 tmp; mvs_94xx_clear_active_cmds() local 883 tmp = mr32(MVS_STP_REG_SET_0); mvs_94xx_clear_active_cmds() 885 mw32(MVS_STP_REG_SET_0, tmp); mvs_94xx_clear_active_cmds() 886 tmp = mr32(MVS_STP_REG_SET_1); mvs_94xx_clear_active_cmds() 888 mw32(MVS_STP_REG_SET_1, tmp); mvs_94xx_clear_active_cmds() 988 u32 tmp = 0; mvs_94xx_tune_interrupt() local 1002 tmp = 0x10000 | time; mvs_94xx_tune_interrupt() 1003 mw32(MVS_INT_COAL_TMOUT, tmp); mvs_94xx_tune_interrupt()
/linux-4.4.14/drivers/phy/
H A D	phy-mt65xx-usb3.c	134 u32 tmp; phy_instance_init() local 137 tmp = readl(port_base + U3P_U2PHYDTM0); phy_instance_init() 138 tmp &= ~P2C_FORCE_UART_EN; phy_instance_init() 139 tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0); phy_instance_init() 140 writel(tmp, port_base + U3P_U2PHYDTM0); phy_instance_init() 142 tmp = readl(port_base + U3P_U2PHYDTM1); phy_instance_init() 143 tmp &= ~P2C_RG_UART_EN; phy_instance_init() 144 writel(tmp, port_base + U3P_U2PHYDTM1); phy_instance_init() 147 tmp = readl(port_base + U3P_U2PHYACR4); phy_instance_init() 148 tmp &= ~P2C_U2_GPIO_CTR_MSK; phy_instance_init() 149 writel(tmp, port_base + U3P_U2PHYACR4); phy_instance_init() 151 tmp = readl(port_base + U3P_USBPHYACR2); phy_instance_init() 152 tmp |= PA2_RG_SIF_U2PLL_FORCE_EN; phy_instance_init() 153 writel(tmp, port_base + U3P_USBPHYACR2); phy_instance_init() 155 tmp = readl(port_base + U3D_U2PHYDCR0); phy_instance_init() 156 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; phy_instance_init() 157 writel(tmp, port_base + U3D_U2PHYDCR0); phy_instance_init() 159 tmp = readl(port_base + U3D_U2PHYDCR0); phy_instance_init() 160 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; phy_instance_init() 161 writel(tmp, port_base + U3D_U2PHYDCR0); phy_instance_init() 163 tmp = readl(port_base + U3P_U2PHYDTM0); phy_instance_init() 164 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; phy_instance_init() 165 writel(tmp, port_base + U3P_U2PHYDTM0); phy_instance_init() 169 tmp = readl(port_base + U3P_USBPHYACR6); phy_instance_init() 170 tmp &= ~PA6_RG_U2_BC11_SW_EN; phy_instance_init() 171 writel(tmp, port_base + U3P_USBPHYACR6); phy_instance_init() 173 tmp = readl(port_base + U3P_U3PHYA_DA_REG0); phy_instance_init() 174 tmp &= ~P3A_RG_XTAL_EXT_EN_U3; phy_instance_init() 175 tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2); phy_instance_init() 176 writel(tmp, port_base + U3P_U3PHYA_DA_REG0); phy_instance_init() 178 tmp = readl(port_base + U3P_U3_PHYA_REG9); phy_instance_init() 179 tmp &= ~P3A_RG_RX_DAC_MUX; phy_instance_init() 180 tmp |= P3A_RG_RX_DAC_MUX_VAL(4); phy_instance_init() 181 writel(tmp, port_base + U3P_U3_PHYA_REG9); phy_instance_init() 183 tmp = readl(port_base + U3P_U3_PHYA_REG6); phy_instance_init() 184 tmp &= ~P3A_RG_TX_EIDLE_CM; phy_instance_init() 185 tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe); phy_instance_init() 186 writel(tmp, port_base + U3P_U3_PHYA_REG6); phy_instance_init() 188 tmp = readl(port_base + U3P_PHYD_CDR1); phy_instance_init() 189 tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1); phy_instance_init() 190 tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3); phy_instance_init() 191 writel(tmp, port_base + U3P_PHYD_CDR1); phy_instance_init() 201 u32 tmp; phy_instance_power_on() local 205 tmp = readl(port_base + U3P_U3_PHYA_REG0); phy_instance_power_on() 206 tmp |= P3A_RG_U3_VUSB10_ON; phy_instance_power_on() 207 writel(tmp, port_base + U3P_U3_PHYA_REG0); phy_instance_power_on() 211 tmp = readl(port_base + U3P_U2PHYDTM0); phy_instance_power_on() 212 tmp &= ~(P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL); phy_instance_power_on() 213 tmp &= ~(P2C_RG_DATAIN | P2C_DTM0_PART_MASK); phy_instance_power_on() 214 writel(tmp, port_base + U3P_U2PHYDTM0); phy_instance_power_on() 217 tmp = readl(port_base + U3P_USBPHYACR6); phy_instance_power_on() 218 tmp |= PA6_RG_U2_OTG_VBUSCMP_EN; phy_instance_power_on() 219 writel(tmp, port_base + U3P_USBPHYACR6); phy_instance_power_on() 222 tmp = readl(u3phy->sif_base + U3P_XTALCTL3); phy_instance_power_on() 223 tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD; phy_instance_power_on() 224 writel(tmp, u3phy->sif_base + U3P_XTALCTL3); phy_instance_power_on() 227 tmp = readl(port_base + U3P_USBPHYACR5); phy_instance_power_on() 228 tmp &= ~PA5_RG_U2_HS_100U_U3_EN; phy_instance_power_on() 229 writel(tmp, port_base + U3P_USBPHYACR5); phy_instance_power_on() 232 tmp = readl(port_base + U3P_U2PHYDTM1); phy_instance_power_on() 233 tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID; phy_instance_power_on() 234 tmp &= ~P2C_RG_SESSEND; phy_instance_power_on() 235 writel(tmp, port_base + U3P_U2PHYDTM1); phy_instance_power_on() 238 tmp = readl(port_base + U3P_USBPHYACR5); phy_instance_power_on() 239 tmp &= ~PA5_RG_U2_HSTX_SRCTRL; phy_instance_power_on() 240 tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(4); phy_instance_power_on() 241 writel(tmp, port_base + U3P_USBPHYACR5); phy_instance_power_on() 244 tmp = readl(port_base + U3D_U2PHYDCR0); phy_instance_power_on() 245 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; phy_instance_power_on() 246 writel(tmp, port_base + U3D_U2PHYDCR0); phy_instance_power_on() 248 tmp = readl(port_base + U3P_U2PHYDTM0); phy_instance_power_on() 249 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; phy_instance_power_on() 250 writel(tmp, port_base + U3P_U2PHYDTM0); phy_instance_power_on() 260 u32 tmp; phy_instance_power_off() local 262 tmp = readl(port_base + U3P_U2PHYDTM0); phy_instance_power_off() 263 tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN); phy_instance_power_off() 264 tmp |= P2C_FORCE_SUSPENDM; phy_instance_power_off() 265 writel(tmp, port_base + U3P_U2PHYDTM0); phy_instance_power_off() 268 tmp = readl(port_base + U3P_USBPHYACR6); phy_instance_power_off() 269 tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN; phy_instance_power_off() 270 writel(tmp, port_base + U3P_USBPHYACR6); phy_instance_power_off() 274 tmp = readl(port_base + U3P_USBPHYACR5); phy_instance_power_off() 275 tmp &= ~PA5_RG_U2_HS_100U_U3_EN; phy_instance_power_off() 276 writel(tmp, port_base + U3P_USBPHYACR5); phy_instance_power_off() 280 tmp = readl(port_base + U3P_U2PHYDTM0); phy_instance_power_off() 281 tmp &= ~P2C_RG_SUSPENDM; phy_instance_power_off() 282 writel(tmp, port_base + U3P_U2PHYDTM0); phy_instance_power_off() 285 tmp = readl(port_base + U3P_U2PHYDTM1); phy_instance_power_off() 286 tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID); phy_instance_power_off() 287 tmp |= P2C_RG_SESSEND; phy_instance_power_off() 288 writel(tmp, port_base + U3P_U2PHYDTM1); phy_instance_power_off() 291 tmp = readl(port_base + U3P_U3_PHYA_REG0); phy_instance_power_off() 292 tmp &= ~P3A_RG_U3_VUSB10_ON; phy_instance_power_off() 293 writel(tmp, port_base + U3P_U3_PHYA_REG0); phy_instance_power_off() 295 tmp = readl(port_base + U3D_U2PHYDCR0); phy_instance_power_off() 296 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; phy_instance_power_off() 297 writel(tmp, port_base + U3D_U2PHYDCR0); phy_instance_power_off() 308 u32 tmp; phy_instance_exit() local 311 tmp = readl(port_base + U3D_U2PHYDCR0); phy_instance_exit() 312 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; phy_instance_exit() 313 writel(tmp, port_base + U3D_U2PHYDCR0); phy_instance_exit() 315 tmp = readl(port_base + U3P_U2PHYDTM0); phy_instance_exit() 316 tmp &= ~P2C_FORCE_SUSPENDM; phy_instance_exit() 317 writel(tmp, port_base + U3P_U2PHYDTM0); phy_instance_exit()
H A D	phy-brcmstb-sata.c	76 u32 tmp; brcm_sata_mdio_wr() local 79 tmp = readl(addr + SATA_MDIO_REG_OFFSET(ofs)); brcm_sata_mdio_wr() 80 tmp = (tmp & msk) | value; brcm_sata_mdio_wr() 81 writel(tmp, addr + SATA_MDIO_REG_OFFSET(ofs)); brcm_sata_mdio_wr() 93 u32 tmp; brcm_sata_cfg_ssc_28nm() local 96 tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC; brcm_sata_cfg_ssc_28nm() 97 brcm_sata_mdio_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp); brcm_sata_cfg_ssc_28nm() 107 tmp = FMAX_VAL_SSC; brcm_sata_cfg_ssc_28nm() 109 tmp = FMAX_VAL_DEFAULT; brcm_sata_cfg_ssc_28nm() 113 ~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp); brcm_sata_cfg_ssc_28nm()
/linux-4.4.14/tools/power/cpupower/lib/
H A D	cpufreq.c	80 struct cpufreq_available_governors *tmp, *next; cpufreq_put_available_governors() local 85 tmp = any->first; cpufreq_put_available_governors() 86 while (tmp) { cpufreq_put_available_governors() 87 next = tmp->next; cpufreq_put_available_governors() 88 if (tmp->governor) cpufreq_put_available_governors() 89 free(tmp->governor); cpufreq_put_available_governors() 90 free(tmp); cpufreq_put_available_governors() 91 tmp = next; cpufreq_put_available_governors() 104 struct cpufreq_available_frequencies *tmp, *next; cpufreq_put_available_frequencies() local 109 tmp = any->first; cpufreq_put_available_frequencies() 110 while (tmp) { cpufreq_put_available_frequencies() 111 next = tmp->next; cpufreq_put_available_frequencies() 112 free(tmp); cpufreq_put_available_frequencies() 113 tmp = next; cpufreq_put_available_frequencies() 125 struct cpufreq_affected_cpus *tmp, *next; cpufreq_put_affected_cpus() local 130 tmp = any->first; cpufreq_put_affected_cpus() 131 while (tmp) { cpufreq_put_affected_cpus() 132 next = tmp->next; cpufreq_put_affected_cpus() 133 free(tmp); cpufreq_put_affected_cpus() 134 tmp = next; cpufreq_put_affected_cpus() 192 struct cpufreq_stats *tmp, *next; cpufreq_put_stats() local 197 tmp = any->first; cpufreq_put_stats() 198 while (tmp) { cpufreq_put_stats() 199 next = tmp->next; cpufreq_put_stats() 200 free(tmp); cpufreq_put_stats() 201 tmp = next; cpufreq_put_stats()
/linux-4.4.14/tools/power/cpupower/utils/idle_monitor/
H A D	cpuidle_sysfs.c	81 void fix_up_intel_idle_driver_name(char *tmp, int num) fix_up_intel_idle_driver_name() argument 84 if (!strncmp(tmp, "NHM-", 4)) { fix_up_intel_idle_driver_name() 87 strcpy(tmp, "C1"); fix_up_intel_idle_driver_name() 90 strcpy(tmp, "C3"); fix_up_intel_idle_driver_name() 93 strcpy(tmp, "C6"); fix_up_intel_idle_driver_name() 96 } else if (!strncmp(tmp, "SNB-", 4)) { fix_up_intel_idle_driver_name() 99 strcpy(tmp, "C1"); fix_up_intel_idle_driver_name() 102 strcpy(tmp, "C3"); fix_up_intel_idle_driver_name() 105 strcpy(tmp, "C6"); fix_up_intel_idle_driver_name() 108 strcpy(tmp, "C7"); fix_up_intel_idle_driver_name() 111 } else if (!strncmp(tmp, "ATM-", 4)) { fix_up_intel_idle_driver_name() 114 strcpy(tmp, "C1"); fix_up_intel_idle_driver_name() 117 strcpy(tmp, "C2"); fix_up_intel_idle_driver_name() 120 strcpy(tmp, "C4"); fix_up_intel_idle_driver_name() 123 strcpy(tmp, "C6"); fix_up_intel_idle_driver_name() 132 char *tmp; cpuidle_register() local 141 tmp = sysfs_get_idlestate_name(0, num); cpuidle_register() 142 if (tmp == NULL) cpuidle_register() 145 fix_up_intel_idle_driver_name(tmp, num); cpuidle_register() 146 strncpy(cpuidle_cstates[num].name, tmp, CSTATE_NAME_LEN - 1); cpuidle_register() 147 free(tmp); cpuidle_register() 149 tmp = sysfs_get_idlestate_desc(0, num); cpuidle_register() 150 if (tmp == NULL) cpuidle_register() 152 strncpy(cpuidle_cstates[num].desc, tmp, CSTATE_DESC_LEN - 1); cpuidle_register() 153 free(tmp); cpuidle_register()
/linux-4.4.14/arch/s390/lib/
H A D	find.c	20 unsigned long tmp; find_first_bit_inv() local 23 if ((tmp = *(p++))) find_first_bit_inv() 30 tmp = (*p) & (~0UL << (BITS_PER_LONG - size)); find_first_bit_inv() 31 if (!tmp) /* Are any bits set? */ find_first_bit_inv() 34 return result + (__fls(tmp) ^ (BITS_PER_LONG - 1)); find_first_bit_inv() 43 unsigned long tmp; find_next_bit_inv() local 50 tmp = *(p++); find_next_bit_inv() 51 tmp &= (~0UL >> offset); find_next_bit_inv() 54 if (tmp) find_next_bit_inv() 60 if ((tmp = *(p++))) find_next_bit_inv() 67 tmp = *p; find_next_bit_inv() 69 tmp &= (~0UL << (BITS_PER_LONG - size)); find_next_bit_inv() 70 if (!tmp) /* Are any bits set? */ find_next_bit_inv() 73 return result + (__fls(tmp) ^ (BITS_PER_LONG - 1)); find_next_bit_inv()
/linux-4.4.14/tools/lib/util/
H A D	find_next_bit.c	29 unsigned long tmp; find_next_bit() local 36 tmp = *(p++); find_next_bit() 37 tmp &= (~0UL << offset); find_next_bit() 40 if (tmp) find_next_bit() 46 if ((tmp = *(p++))) find_next_bit() 53 tmp = *p; find_next_bit() 56 tmp &= (~0UL >> (BITS_PER_LONG - size)); find_next_bit() 57 if (tmp == 0UL) /* Are any bits set? */ find_next_bit() 60 return result + __ffs(tmp); find_next_bit() 72 unsigned long tmp; find_first_bit() local 75 if ((tmp = *(p++))) find_first_bit() 83 tmp = (*p) & (~0UL >> (BITS_PER_LONG - size)); find_first_bit() 84 if (tmp == 0UL) /* Are any bits set? */ find_first_bit() 87 return result + __ffs(tmp); find_first_bit()
/linux-4.4.14/arch/xtensa/include/asm/
H A D	rwsem.h	40 int tmp; __down_read_trylock() local 42 while ((tmp = sem->count) >= 0) { __down_read_trylock() 43 if (tmp == cmpxchg(&sem->count, tmp, __down_read_trylock() 44 tmp + RWSEM_ACTIVE_READ_BIAS)) { __down_read_trylock() 57 int tmp; __down_write() local 59 tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS, __down_write() 61 if (tmp == RWSEM_ACTIVE_WRITE_BIAS) __down_write() 69 int tmp; __down_write_trylock() local 71 tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE, __down_write_trylock() 74 return tmp == RWSEM_UNLOCKED_VALUE; __down_write_trylock() 82 int tmp; __up_read() local 85 tmp = atomic_sub_return(1,(atomic_t *)(&sem->count)); __up_read() 86 if (tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0) __up_read() 114 int tmp; __downgrade_write() local 117 tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count)); __downgrade_write() 118 if (tmp < 0) __downgrade_write()
H A D	spinlock.h	39 unsigned long tmp; arch_spin_lock() local 47 : "=&a" (tmp) arch_spin_lock() 56 unsigned long tmp; arch_spin_trylock() local 63 : "=&a" (tmp) arch_spin_trylock() 67 return tmp == 0 ? 1 : 0; arch_spin_trylock() 72 unsigned long tmp; arch_spin_unlock() local 77 : "=&a" (tmp) arch_spin_unlock() 103 unsigned long tmp; arch_write_lock() local 112 : "=&a" (tmp) arch_write_lock() 121 unsigned long tmp; arch_write_trylock() local 129 : "=&a" (tmp) arch_write_trylock() 133 return tmp == 0 ? 1 : 0; arch_write_trylock() 138 unsigned long tmp; arch_write_unlock() local 143 : "=&a" (tmp) arch_write_unlock() 150 unsigned long tmp; arch_read_lock() local 160 : "=&a" (result), "=&a" (tmp) arch_read_lock() 170 unsigned long tmp; arch_read_trylock() local 180 : "=&a" (result), "=&a" (tmp) arch_read_trylock()
H A D	tlbflush.h	66 unsigned long tmp; itlb_probe() local 67 __asm__ __volatile__("pitlb %0, %1\n\t" : "=a" (tmp) : "a" (addr)); itlb_probe() 68 return tmp; itlb_probe() 73 unsigned long tmp; dtlb_probe() local 74 __asm__ __volatile__("pdtlb %0, %1\n\t" : "=a" (tmp) : "a" (addr)); dtlb_probe() 75 return tmp; dtlb_probe() 125 unsigned long tmp; read_ptevaddr_register() local 126 __asm__ __volatile__("rsr %0, ptevaddr\n\t" : "=a" (tmp)); read_ptevaddr_register() 127 return tmp; read_ptevaddr_register() 181 unsigned long tmp; read_dtlb_virtual() local 182 __asm__ __volatile__("rdtlb0 %0, %1\n\t" : "=a" (tmp), "+a" (way)); read_dtlb_virtual() 183 return tmp; read_dtlb_virtual() 188 unsigned long tmp; read_dtlb_translation() local 189 __asm__ __volatile__("rdtlb1 %0, %1\n\t" : "=a" (tmp), "+a" (way)); read_dtlb_translation() 190 return tmp; read_dtlb_translation() 195 unsigned long tmp; read_itlb_virtual() local 196 __asm__ __volatile__("ritlb0 %0, %1\n\t" : "=a" (tmp), "+a" (way)); read_itlb_virtual() 197 return tmp; read_itlb_virtual() 202 unsigned long tmp; read_itlb_translation() local 203 __asm__ __volatile__("ritlb1 %0, %1\n\t" : "=a" (tmp), "+a" (way)); read_itlb_translation() 204 return tmp; read_itlb_translation()
H A D	bitops.h	105 unsigned long tmp, value; set_bit() local 116 : "=&a" (tmp), "=&a" (value) set_bit() 123 unsigned long tmp, value; clear_bit() local 134 : "=&a" (tmp), "=&a" (value) clear_bit() 141 unsigned long tmp, value; change_bit() local 152 : "=&a" (tmp), "=&a" (value) change_bit() 160 unsigned long tmp, value; test_and_set_bit() local 171 : "=&a" (tmp), "=&a" (value) test_and_set_bit() 175 return tmp & mask; test_and_set_bit() 181 unsigned long tmp, value; test_and_clear_bit() local 192 : "=&a" (tmp), "=&a" (value) test_and_clear_bit() 196 return tmp & mask; test_and_clear_bit() 202 unsigned long tmp, value; test_and_change_bit() local 213 : "=&a" (tmp), "=&a" (value) test_and_change_bit() 217 return tmp & mask; test_and_change_bit()
/linux-4.4.14/include/asm-generic/
H A D	rwsem.h	42 long tmp; __down_read_trylock() local 44 while ((tmp = sem->count) >= 0) { __down_read_trylock() 45 if (tmp == cmpxchg_acquire(&sem->count, tmp, __down_read_trylock() 46 tmp + RWSEM_ACTIVE_READ_BIAS)) { __down_read_trylock() 58 long tmp; __down_write_nested() local 60 tmp = atomic_long_add_return_acquire(RWSEM_ACTIVE_WRITE_BIAS, __down_write_nested() 62 if (unlikely(tmp != RWSEM_ACTIVE_WRITE_BIAS)) __down_write_nested() 73 long tmp; __down_write_trylock() local 75 tmp = cmpxchg_acquire(&sem->count, RWSEM_UNLOCKED_VALUE, __down_write_trylock() 77 return tmp == RWSEM_UNLOCKED_VALUE; __down_write_trylock() 85 long tmp; __up_read() local 87 tmp = atomic_long_dec_return_release((atomic_long_t *)&sem->count); __up_read() 88 if (unlikely(tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0)) __up_read() 115 long tmp; __downgrade_write() local 124 tmp = atomic_long_add_return_release(-RWSEM_WAITING_BIAS, __downgrade_write() 126 if (tmp < 0) __downgrade_write()
H A D	termios-base.h	17 unsigned short tmp; user_termio_to_kernel_termios() local 19 if (get_user(tmp, &termio->c_iflag) < 0) user_termio_to_kernel_termios() 21 termios->c_iflag = (0xffff0000 & termios->c_iflag) | tmp; user_termio_to_kernel_termios() 23 if (get_user(tmp, &termio->c_oflag) < 0) user_termio_to_kernel_termios() 25 termios->c_oflag = (0xffff0000 & termios->c_oflag) | tmp; user_termio_to_kernel_termios() 27 if (get_user(tmp, &termio->c_cflag) < 0) user_termio_to_kernel_termios() 29 termios->c_cflag = (0xffff0000 & termios->c_cflag) | tmp; user_termio_to_kernel_termios() 31 if (get_user(tmp, &termio->c_lflag) < 0) user_termio_to_kernel_termios() 33 termios->c_lflag = (0xffff0000 & termios->c_lflag) | tmp; user_termio_to_kernel_termios()
H A D	termios.h	22 unsigned short tmp; user_termio_to_kernel_termios() local 24 if (get_user(tmp, &termio->c_iflag) < 0) user_termio_to_kernel_termios() 26 termios->c_iflag = (0xffff0000 & termios->c_iflag) | tmp; user_termio_to_kernel_termios() 28 if (get_user(tmp, &termio->c_oflag) < 0) user_termio_to_kernel_termios() 30 termios->c_oflag = (0xffff0000 & termios->c_oflag) | tmp; user_termio_to_kernel_termios() 32 if (get_user(tmp, &termio->c_cflag) < 0) user_termio_to_kernel_termios() 34 termios->c_cflag = (0xffff0000 & termios->c_cflag) | tmp; user_termio_to_kernel_termios() 36 if (get_user(tmp, &termio->c_lflag) < 0) user_termio_to_kernel_termios() 38 termios->c_lflag = (0xffff0000 & termios->c_lflag) | tmp; user_termio_to_kernel_termios()
/linux-4.4.14/arch/sh/include/asm/
H A D	rwsem.h	35 int tmp; __down_read_trylock() local 37 while ((tmp = sem->count) >= 0) { __down_read_trylock() 38 if (tmp == cmpxchg(&sem->count, tmp, __down_read_trylock() 39 tmp + RWSEM_ACTIVE_READ_BIAS)) { __down_read_trylock() 52 int tmp; __down_write() local 54 tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS, __down_write() 56 if (tmp == RWSEM_ACTIVE_WRITE_BIAS) __down_write() 64 int tmp; __down_write_trylock() local 66 tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE, __down_write_trylock() 69 return tmp == RWSEM_UNLOCKED_VALUE; __down_write_trylock() 77 int tmp; __up_read() local 80 tmp = atomic_dec_return((atomic_t *)(&sem->count)); __up_read() 81 if (tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0) __up_read() 109 int tmp; __downgrade_write() local 112 tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count)); __downgrade_write() 113 if (tmp < 0) __downgrade_write()
H A D	cmpxchg-llsc.h	7 unsigned long tmp; xchg_u32() local 17 : "=&z"(tmp), "=&r" (retval) xchg_u32() 28 unsigned long tmp; xchg_u8() local 38 : "=&z"(tmp), "=&r" (retval) xchg_u8() 50 unsigned long tmp; __cmpxchg_u32() local 63 : "=&z" (tmp), "=&r" (retval) __cmpxchg_u32()
H A D	bitops-llsc.h	8 unsigned long tmp; set_bit() local 19 : "=&z" (tmp) set_bit() 29 unsigned long tmp; clear_bit() local 40 : "=&z" (tmp) clear_bit() 50 unsigned long tmp; change_bit() local 61 : "=&z" (tmp) change_bit() 71 unsigned long tmp; test_and_set_bit() local 84 : "=&z" (tmp), "=&r" (retval) test_and_set_bit() 96 unsigned long tmp; test_and_clear_bit() local 110 : "=&z" (tmp), "=&r" (retval) test_and_clear_bit() 122 unsigned long tmp; test_and_change_bit() local 136 : "=&z" (tmp), "=&r" (retval) test_and_change_bit()
H A D	spinlock.h	39 unsigned long tmp; arch_spin_lock() local 51 : "=&z" (tmp), "=&r" (oldval) arch_spin_lock() 59 unsigned long tmp; arch_spin_unlock() local 64 : "=&z" (tmp) arch_spin_unlock() 72 unsigned long tmp, oldval; arch_spin_trylock() local 82 : "=&z" (tmp), "=&r" (oldval) arch_spin_trylock() 113 unsigned long tmp; arch_read_lock() local 123 : "=&z" (tmp) arch_read_lock() 131 unsigned long tmp; arch_read_unlock() local 139 : "=&z" (tmp) arch_read_unlock() 147 unsigned long tmp; arch_write_lock() local 157 : "=&z" (tmp) arch_write_lock() 175 unsigned long tmp, oldval; arch_read_trylock() local 188 : "=&z" (tmp), "=&r" (oldval) arch_read_trylock() 198 unsigned long tmp, oldval; arch_write_trylock() local 211 : "=&z" (tmp), "=&r" (oldval) arch_write_trylock()
H A D	atomic-grb.h	7 int tmp; \ 18 : "=&r" (tmp), \ 27 int tmp; \ 38 : "=&r" (tmp), \ 43 return tmp; \
H A D	bitops-grb.h	8 unsigned long tmp; set_bit() local 22 : "=&r" (tmp), set_bit() 32 unsigned long tmp; clear_bit() local 45 : "=&r" (tmp), clear_bit() 55 unsigned long tmp; change_bit() local 68 : "=&r" (tmp), change_bit() 78 unsigned long tmp; test_and_set_bit() local 96 : "=&r" (tmp), test_and_set_bit() 109 unsigned long tmp; test_and_clear_bit() local 129 : "=&r" (tmp), test_and_clear_bit() 143 unsigned long tmp; test_and_change_bit() local 161 : "=&r" (tmp), test_and_change_bit()
/linux-4.4.14/arch/sparc/include/asm/
H A D	rwsem.h	34 long tmp; __down_read_trylock() local 36 while ((tmp = sem->count) >= 0L) { __down_read_trylock() 37 if (tmp == cmpxchg(&sem->count, tmp, __down_read_trylock() 38 tmp + RWSEM_ACTIVE_READ_BIAS)) { __down_read_trylock() 50 long tmp; __down_write_nested() local 52 tmp = atomic64_add_return(RWSEM_ACTIVE_WRITE_BIAS, __down_write_nested() 54 if (unlikely(tmp != RWSEM_ACTIVE_WRITE_BIAS)) __down_write_nested() 65 long tmp; __down_write_trylock() local 67 tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE, __down_write_trylock() 69 return tmp == RWSEM_UNLOCKED_VALUE; __down_write_trylock() 77 long tmp; __up_read() local 79 tmp = atomic64_dec_return((atomic64_t *)(&sem->count)); __up_read() 80 if (unlikely(tmp < -1L && (tmp & RWSEM_ACTIVE_MASK) == 0L)) __up_read() 107 long tmp; __downgrade_write() local 109 tmp = atomic64_add_return(-RWSEM_WAITING_BIAS, (atomic64_t *)(&sem->count)); __downgrade_write() 110 if (tmp < 0L) __downgrade_write()
H A D	backoff.h	54 #define BACKOFF_SPIN(reg, tmp, label) \ 55 mov reg, tmp; \ 61 sllx tmp, 7, tmp; \ 62 wr tmp, 0, %asr27; \ 63 clr tmp; \ 65 brnz,pt tmp, 88b; \ 66 sub tmp, 1, tmp; \ 67 set BACKOFF_LIMIT, tmp; \ 68 cmp reg, tmp; \ 81 #define BACKOFF_SPIN(reg, tmp, label)
/linux-4.4.14/arch/avr32/include/asm/
H A D	asm.h	44 .macro save_min sr, tmp=lr variable 46 mfsr \tmp, \sr 48 st.w --sp, \tmp 51 .macro restore_min sr, tmp=lr variable 52 ld.w \tmp, sp++ 53 mtsr \sr, \tmp 57 .macro save_half sr, tmp=lr variable 61 mfsr \tmp, \sr variable 62 st.w --sp, \tmp 65 .macro restore_half sr, tmp=lr variable 66 ld.w \tmp, sp++ 67 mtsr \sr, \tmp 72 .macro save_full_user sr, tmp=lr variable 76 mfsr \tmp, \sr variable 77 st.w --sp, \tmp 80 .macro restore_full_user sr, tmp=lr variable 81 ld.w \tmp, sp++ 82 mtsr \sr, \tmp
/linux-4.4.14/arch/arm/include/asm/
H A D	vfpmacros.h	20 .macro VFPFLDMIA, base, tmp 28 ldr \tmp, =elf_hwcap @ may not have MVFR regs variable 29 ldr \tmp, [\tmp, #0] 30 tst \tmp, #HWCAP_VFPD32 variable 34 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 35 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field 36 cmp \tmp, #2 @ 32 x 64bit registers? 44 .macro VFPFSTMIA, base, tmp 52 ldr \tmp, =elf_hwcap @ may not have MVFR regs variable 53 ldr \tmp, [\tmp, #0] 54 tst \tmp, #HWCAP_VFPD32 variable 58 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 59 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field 60 cmp \tmp, #2 @ 32 x 64bit registers?
H A D	futex.h	24 #define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ 38 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \ 83 #define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ 92 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \ 137 int oldval = 0, ret, tmp; futex_atomic_op_inuser() local 152 __futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg); futex_atomic_op_inuser() 155 __futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg); futex_atomic_op_inuser() 158 __futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg); futex_atomic_op_inuser() 161 __futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg); futex_atomic_op_inuser() 164 __futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg); futex_atomic_op_inuser()
/linux-4.4.14/arch/arm/mach-gemini/include/mach/
H A D	entry-macro.S	15 .macro get_irqnr_preamble, base, tmp 18 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 23 mov \tmp, \irqnr 26 tst \tmp, #1 29 mov \tmp, \tmp, lsr #1
/linux-4.4.14/tools/power/cpupower/utils/
H A D	cpuidle-info.c	26 char *tmp; cpuidle_cpu_output() local 39 tmp = sysfs_get_idlestate_name(cpu, idlestate); cpuidle_cpu_output() 40 if (!tmp) cpuidle_cpu_output() 42 printf(" %s", tmp); cpuidle_cpu_output() 43 free(tmp); cpuidle_cpu_output() 55 tmp = sysfs_get_idlestate_name(cpu, idlestate); cpuidle_cpu_output() 56 if (!tmp) cpuidle_cpu_output() 58 printf("%s%s:\n", tmp, (disabled) ? " (DISABLED) " : ""); cpuidle_cpu_output() 59 free(tmp); cpuidle_cpu_output() 61 tmp = sysfs_get_idlestate_desc(cpu, idlestate); cpuidle_cpu_output() 62 if (!tmp) cpuidle_cpu_output() 64 printf(_("Flags/Description: %s\n"), tmp); cpuidle_cpu_output() 65 free(tmp); cpuidle_cpu_output() 79 char *tmp; cpuidle_general_output() local 81 tmp = sysfs_get_cpuidle_driver(); cpuidle_general_output() 82 if (!tmp) { cpuidle_general_output() 87 printf(_("CPUidle driver: %s\n"), tmp); cpuidle_general_output() 88 free(tmp); cpuidle_general_output() 90 tmp = sysfs_get_cpuidle_governor(); cpuidle_general_output() 91 if (!tmp) { cpuidle_general_output() 96 printf(_("CPUidle governor: %s\n"), tmp); cpuidle_general_output() 97 free(tmp); cpuidle_general_output()
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
H A D	gmc_v8_0.c	133 u32 tmp; gmc_v8_0_mc_wait_for_idle() local 137 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__VMC_BUSY_MASK | gmc_v8_0_mc_wait_for_idle() 143 if (!tmp) gmc_v8_0_mc_wait_for_idle() 176 u32 tmp; gmc_v8_0_mc_resume() local 179 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); gmc_v8_0_mc_resume() 180 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); gmc_v8_0_mc_resume() 181 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); gmc_v8_0_mc_resume() 183 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); gmc_v8_0_mc_resume() 184 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); gmc_v8_0_mc_resume() 185 WREG32(mmBIF_FB_EN, tmp); gmc_v8_0_mc_resume() 338 u32 tmp; gmc_v8_0_mc_program() local 365 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; gmc_v8_0_mc_program() 366 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); gmc_v8_0_mc_program() 367 WREG32(mmMC_VM_FB_LOCATION, tmp); gmc_v8_0_mc_program() 382 tmp = RREG32(mmHDP_MISC_CNTL); gmc_v8_0_mc_program() 383 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); gmc_v8_0_mc_program() 384 WREG32(mmHDP_MISC_CNTL, tmp); gmc_v8_0_mc_program() 386 tmp = RREG32(mmHDP_HOST_PATH_CNTL); gmc_v8_0_mc_program() 387 WREG32(mmHDP_HOST_PATH_CNTL, tmp); gmc_v8_0_mc_program() 401 u32 tmp; gmc_v8_0_mc_init() local 405 tmp = RREG32(mmMC_ARB_RAMCFG); gmc_v8_0_mc_init() 406 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { gmc_v8_0_mc_init() 411 tmp = RREG32(mmMC_SHARED_CHMAP); gmc_v8_0_mc_init() 412 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { gmc_v8_0_mc_init() 545 u32 tmp; gmc_v8_0_set_fault_enable_default() local 547 tmp = RREG32(mmVM_CONTEXT1_CNTL); gmc_v8_0_set_fault_enable_default() 548 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, gmc_v8_0_set_fault_enable_default() 550 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, gmc_v8_0_set_fault_enable_default() 552 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, gmc_v8_0_set_fault_enable_default() 554 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, gmc_v8_0_set_fault_enable_default() 556 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, gmc_v8_0_set_fault_enable_default() 558 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, gmc_v8_0_set_fault_enable_default() 560 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, gmc_v8_0_set_fault_enable_default() 562 WREG32(mmVM_CONTEXT1_CNTL, tmp); gmc_v8_0_set_fault_enable_default() 579 u32 tmp; gmc_v8_0_gart_enable() local 589 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); gmc_v8_0_gart_enable() 590 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); gmc_v8_0_gart_enable() 591 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); gmc_v8_0_gart_enable() 592 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); gmc_v8_0_gart_enable() 593 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); gmc_v8_0_gart_enable() 594 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); gmc_v8_0_gart_enable() 595 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); gmc_v8_0_gart_enable() 597 tmp = RREG32(mmVM_L2_CNTL); gmc_v8_0_gart_enable() 598 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); gmc_v8_0_gart_enable() 599 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); gmc_v8_0_gart_enable() 600 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); gmc_v8_0_gart_enable() 601 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); gmc_v8_0_gart_enable() 602 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); gmc_v8_0_gart_enable() 603 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); gmc_v8_0_gart_enable() 604 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); gmc_v8_0_gart_enable() 605 WREG32(mmVM_L2_CNTL, tmp); gmc_v8_0_gart_enable() 606 tmp = RREG32(mmVM_L2_CNTL2); gmc_v8_0_gart_enable() 607 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); gmc_v8_0_gart_enable() 608 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); gmc_v8_0_gart_enable() 609 WREG32(mmVM_L2_CNTL2, tmp); gmc_v8_0_gart_enable() 610 tmp = RREG32(mmVM_L2_CNTL3); gmc_v8_0_gart_enable() 611 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); gmc_v8_0_gart_enable() 612 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); gmc_v8_0_gart_enable() 613 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); gmc_v8_0_gart_enable() 614 WREG32(mmVM_L2_CNTL3, tmp); gmc_v8_0_gart_enable() 616 tmp = RREG32(mmVM_L2_CNTL4); gmc_v8_0_gart_enable() 617 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); gmc_v8_0_gart_enable() 618 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); gmc_v8_0_gart_enable() 619 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); gmc_v8_0_gart_enable() 620 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); gmc_v8_0_gart_enable() 621 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); gmc_v8_0_gart_enable() 622 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); gmc_v8_0_gart_enable() 623 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); gmc_v8_0_gart_enable() 624 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); gmc_v8_0_gart_enable() 625 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); gmc_v8_0_gart_enable() 626 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); gmc_v8_0_gart_enable() 627 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); gmc_v8_0_gart_enable() 628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); gmc_v8_0_gart_enable() 629 WREG32(mmVM_L2_CNTL4, tmp); gmc_v8_0_gart_enable() 637 tmp = RREG32(mmVM_CONTEXT0_CNTL); gmc_v8_0_gart_enable() 638 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); gmc_v8_0_gart_enable() 639 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); gmc_v8_0_gart_enable() 640 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); gmc_v8_0_gart_enable() 641 WREG32(mmVM_CONTEXT0_CNTL, tmp); gmc_v8_0_gart_enable() 667 tmp = RREG32(mmVM_CONTEXT1_CNTL); gmc_v8_0_gart_enable() 668 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); gmc_v8_0_gart_enable() 669 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); gmc_v8_0_gart_enable() 670 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); gmc_v8_0_gart_enable() 671 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); gmc_v8_0_gart_enable() 672 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); gmc_v8_0_gart_enable() 673 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); gmc_v8_0_gart_enable() 674 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); gmc_v8_0_gart_enable() 675 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); gmc_v8_0_gart_enable() 676 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); gmc_v8_0_gart_enable() 677 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, gmc_v8_0_gart_enable() 679 WREG32(mmVM_CONTEXT1_CNTL, tmp); gmc_v8_0_gart_enable() 718 u32 tmp; gmc_v8_0_gart_disable() local 724 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); gmc_v8_0_gart_disable() 725 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); gmc_v8_0_gart_disable() 726 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); gmc_v8_0_gart_disable() 727 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); gmc_v8_0_gart_disable() 728 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); gmc_v8_0_gart_disable() 730 tmp = RREG32(mmVM_L2_CNTL); gmc_v8_0_gart_disable() 731 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); gmc_v8_0_gart_disable() 732 WREG32(mmVM_L2_CNTL, tmp); gmc_v8_0_gart_disable() 777 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); gmc_v8_0_vm_init() local 778 tmp <<= 22; gmc_v8_0_vm_init() 779 adev->vm_manager.vram_base_offset = tmp; gmc_v8_0_vm_init() 880 u32 tmp; gmc_v8_0_sw_init() local 883 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); gmc_v8_0_sw_init() 885 tmp = RREG32(mmMC_SEQ_MISC0); gmc_v8_0_sw_init() 886 tmp &= MC_SEQ_MISC0__MT__MASK; gmc_v8_0_sw_init() 887 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp); gmc_v8_0_sw_init() 1048 u32 tmp = RREG32(mmSRBM_STATUS); gmc_v8_0_is_idle() local 1050 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | gmc_v8_0_is_idle() 1060 u32 tmp; gmc_v8_0_wait_for_idle() local 1065 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | gmc_v8_0_wait_for_idle() 1071 if (!tmp) gmc_v8_0_wait_for_idle() 1189 u32 tmp = RREG32(mmSRBM_STATUS); gmc_v8_0_soft_reset() local 1191 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) gmc_v8_0_soft_reset() 1195 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | gmc_v8_0_soft_reset() 1211 tmp = RREG32(mmSRBM_SOFT_RESET); gmc_v8_0_soft_reset() 1212 tmp |= srbm_soft_reset; gmc_v8_0_soft_reset() 1213 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); gmc_v8_0_soft_reset() 1214 WREG32(mmSRBM_SOFT_RESET, tmp); gmc_v8_0_soft_reset() 1215 tmp = RREG32(mmSRBM_SOFT_RESET); gmc_v8_0_soft_reset() 1219 tmp &= ~srbm_soft_reset; gmc_v8_0_soft_reset() 1220 WREG32(mmSRBM_SOFT_RESET, tmp); gmc_v8_0_soft_reset() 1221 tmp = RREG32(mmSRBM_SOFT_RESET); gmc_v8_0_soft_reset() 1240 u32 tmp; gmc_v8_0_vm_fault_interrupt_state() local 1252 tmp = RREG32(mmVM_CONTEXT0_CNTL); gmc_v8_0_vm_fault_interrupt_state() 1253 tmp &= ~bits; gmc_v8_0_vm_fault_interrupt_state() 1254 WREG32(mmVM_CONTEXT0_CNTL, tmp); gmc_v8_0_vm_fault_interrupt_state() 1256 tmp = RREG32(mmVM_CONTEXT1_CNTL); gmc_v8_0_vm_fault_interrupt_state() 1257 tmp &= ~bits; gmc_v8_0_vm_fault_interrupt_state() 1258 WREG32(mmVM_CONTEXT1_CNTL, tmp); gmc_v8_0_vm_fault_interrupt_state() 1262 tmp = RREG32(mmVM_CONTEXT0_CNTL); gmc_v8_0_vm_fault_interrupt_state() 1263 tmp |= bits; gmc_v8_0_vm_fault_interrupt_state() 1264 WREG32(mmVM_CONTEXT0_CNTL, tmp); gmc_v8_0_vm_fault_interrupt_state() 1266 tmp = RREG32(mmVM_CONTEXT1_CNTL); gmc_v8_0_vm_fault_interrupt_state() 1267 tmp |= bits; gmc_v8_0_vm_fault_interrupt_state() 1268 WREG32(mmVM_CONTEXT1_CNTL, tmp); gmc_v8_0_vm_fault_interrupt_state()
H A D	dce_v10_0.c	369 u32 tmp; dce_v10_0_hpd_set_polarity() local 396 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); dce_v10_0_hpd_set_polarity() 398 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); dce_v10_0_hpd_set_polarity() 400 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); dce_v10_0_hpd_set_polarity() 401 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); dce_v10_0_hpd_set_polarity() 416 u32 tmp; dce_v10_0_hpd_init() local 455 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); dce_v10_0_hpd_init() 456 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); dce_v10_0_hpd_init() 457 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); dce_v10_0_hpd_init() 459 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); dce_v10_0_hpd_init() 460 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, dce_v10_0_hpd_init() 463 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, dce_v10_0_hpd_init() 466 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); dce_v10_0_hpd_init() 486 u32 tmp; dce_v10_0_hpd_fini() local 515 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); dce_v10_0_hpd_fini() 516 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); dce_v10_0_hpd_fini() 517 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); dce_v10_0_hpd_fini() 533 u32 i, j, tmp; dce_v10_0_is_display_hung() local 536 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); dce_v10_0_is_display_hung() 537 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { dce_v10_0_is_display_hung() 546 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); dce_v10_0_is_display_hung() 547 if (tmp != crtc_status[i]) dce_v10_0_is_display_hung() 562 u32 crtc_enabled, tmp; dce_v10_0_stop_mc_access() local 569 tmp = RREG32(mmVGA_RENDER_CONTROL); dce_v10_0_stop_mc_access() 570 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); dce_v10_0_stop_mc_access() 571 WREG32(mmVGA_RENDER_CONTROL, tmp); dce_v10_0_stop_mc_access() 583 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); dce_v10_0_stop_mc_access() 584 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { dce_v10_0_stop_mc_access() 587 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); dce_v10_0_stop_mc_access() 588 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); dce_v10_0_stop_mc_access() 598 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); dce_v10_0_stop_mc_access() 599 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { dce_v10_0_stop_mc_access() 600 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); dce_v10_0_stop_mc_access() 601 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); dce_v10_0_stop_mc_access() 603 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); dce_v10_0_stop_mc_access() 604 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { dce_v10_0_stop_mc_access() 605 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); dce_v10_0_stop_mc_access() 606 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); dce_v10_0_stop_mc_access() 611 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); dce_v10_0_stop_mc_access() 612 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); dce_v10_0_stop_mc_access() 613 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); dce_v10_0_stop_mc_access() 627 u32 tmp, frame_count; dce_v10_0_resume_mc_access() local 642 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); dce_v10_0_resume_mc_access() 643 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { dce_v10_0_resume_mc_access() 644 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); dce_v10_0_resume_mc_access() 645 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); dce_v10_0_resume_mc_access() 647 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); dce_v10_0_resume_mc_access() 648 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { dce_v10_0_resume_mc_access() 649 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); dce_v10_0_resume_mc_access() 650 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); dce_v10_0_resume_mc_access() 652 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); dce_v10_0_resume_mc_access() 653 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { dce_v10_0_resume_mc_access() 654 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); dce_v10_0_resume_mc_access() 655 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); dce_v10_0_resume_mc_access() 658 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); dce_v10_0_resume_mc_access() 659 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) dce_v10_0_resume_mc_access() 663 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); dce_v10_0_resume_mc_access() 664 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); dce_v10_0_resume_mc_access() 666 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); dce_v10_0_resume_mc_access() 690 u32 tmp; dce_v10_0_set_vga_render_state() local 693 tmp = RREG32(mmVGA_HDP_CONTROL); dce_v10_0_set_vga_render_state() 695 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); dce_v10_0_set_vga_render_state() 697 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); dce_v10_0_set_vga_render_state() 698 WREG32(mmVGA_HDP_CONTROL, tmp); dce_v10_0_set_vga_render_state() 701 tmp = RREG32(mmVGA_RENDER_CONTROL); dce_v10_0_set_vga_render_state() 703 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); dce_v10_0_set_vga_render_state() 705 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); dce_v10_0_set_vga_render_state() 706 WREG32(mmVGA_RENDER_CONTROL, tmp); dce_v10_0_set_vga_render_state() 717 u32 tmp = 0; dce_v10_0_program_fmt() local 742 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); dce_v10_0_program_fmt() 743 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); dce_v10_0_program_fmt() 744 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); dce_v10_0_program_fmt() 745 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); dce_v10_0_program_fmt() 747 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); dce_v10_0_program_fmt() 748 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); dce_v10_0_program_fmt() 754 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); dce_v10_0_program_fmt() 755 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); dce_v10_0_program_fmt() 756 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); dce_v10_0_program_fmt() 757 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); dce_v10_0_program_fmt() 758 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); dce_v10_0_program_fmt() 760 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); dce_v10_0_program_fmt() 761 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); dce_v10_0_program_fmt() 767 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); dce_v10_0_program_fmt() 768 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); dce_v10_0_program_fmt() 769 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); dce_v10_0_program_fmt() 770 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); dce_v10_0_program_fmt() 771 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); dce_v10_0_program_fmt() 773 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); dce_v10_0_program_fmt() 774 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); dce_v10_0_program_fmt() 782 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_program_fmt() 803 u32 tmp, buffer_alloc, i, mem_cfg; dce_v10_0_line_buffer_adjust() local 833 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); dce_v10_0_line_buffer_adjust() 834 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); dce_v10_0_line_buffer_adjust() 835 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_line_buffer_adjust() 837 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); dce_v10_0_line_buffer_adjust() 838 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); dce_v10_0_line_buffer_adjust() 839 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); dce_v10_0_line_buffer_adjust() 842 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); dce_v10_0_line_buffer_adjust() 843 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) dce_v10_0_line_buffer_adjust() 875 u32 tmp = RREG32(mmMC_SHARED_CHMAP); cik_get_number_of_dram_channels() local 877 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { cik_get_number_of_dram_channels() 1107 u32 tmp, dmif_size = 12288; dce_v10_0_latency_watermark() local 1134 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); dce_v10_0_latency_watermark() 1142 lb_fill_bw = min(tmp, dfixed_trunc(b)); dce_v10_0_latency_watermark() 1253 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; dce_v10_0_program_watermarks() local 1341 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); dce_v10_0_program_watermarks() 1342 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_program_watermarks() 1343 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); dce_v10_0_program_watermarks() 1344 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); dce_v10_0_program_watermarks() 1345 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); dce_v10_0_program_watermarks() 1346 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_program_watermarks() 1348 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); dce_v10_0_program_watermarks() 1349 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_program_watermarks() 1350 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); dce_v10_0_program_watermarks() 1351 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); dce_v10_0_program_watermarks() 1352 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); dce_v10_0_program_watermarks() 1353 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_program_watermarks() 1396 u32 offset, tmp; dce_v10_0_audio_get_connected_pins() local 1400 tmp = RREG32_AUDIO_ENDPT(offset, dce_v10_0_audio_get_connected_pins() 1402 if (((tmp & dce_v10_0_audio_get_connected_pins() 1430 u32 tmp; dce_v10_0_afmt_audio_select_pin() local 1435 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); dce_v10_0_afmt_audio_select_pin() 1436 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); dce_v10_0_afmt_audio_select_pin() 1437 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); dce_v10_0_afmt_audio_select_pin() 1448 u32 tmp; dce_v10_0_audio_write_latency_fields() local 1469 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, dce_v10_0_audio_write_latency_fields() 1471 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, dce_v10_0_audio_write_latency_fields() 1474 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, dce_v10_0_audio_write_latency_fields() 1476 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, dce_v10_0_audio_write_latency_fields() 1480 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); dce_v10_0_audio_write_latency_fields() 1490 u32 tmp; dce_v10_0_audio_write_speaker_allocation() local 1516 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, dce_v10_0_audio_write_speaker_allocation() 1518 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, dce_v10_0_audio_write_speaker_allocation() 1521 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, dce_v10_0_audio_write_speaker_allocation() 1524 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, dce_v10_0_audio_write_speaker_allocation() 1527 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, dce_v10_0_audio_write_speaker_allocation() 1530 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); dce_v10_0_audio_write_speaker_allocation() 1583 u32 tmp = 0; dce_v10_0_audio_write_sad_regs() local 1593 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, dce_v10_0_audio_write_sad_regs() 1595 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, dce_v10_0_audio_write_sad_regs() 1597 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, dce_v10_0_audio_write_sad_regs() 1609 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, dce_v10_0_audio_write_sad_regs() 1611 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); dce_v10_0_audio_write_sad_regs() 1690 u32 tmp; dce_v10_0_afmt_update_ACR() local 1692 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); dce_v10_0_afmt_update_ACR() 1693 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); dce_v10_0_afmt_update_ACR() 1694 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); dce_v10_0_afmt_update_ACR() 1695 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); dce_v10_0_afmt_update_ACR() 1696 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); dce_v10_0_afmt_update_ACR() 1697 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); dce_v10_0_afmt_update_ACR() 1699 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); dce_v10_0_afmt_update_ACR() 1700 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); dce_v10_0_afmt_update_ACR() 1701 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); dce_v10_0_afmt_update_ACR() 1702 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); dce_v10_0_afmt_update_ACR() 1703 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); dce_v10_0_afmt_update_ACR() 1704 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); dce_v10_0_afmt_update_ACR() 1706 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); dce_v10_0_afmt_update_ACR() 1707 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); dce_v10_0_afmt_update_ACR() 1708 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); dce_v10_0_afmt_update_ACR() 1709 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); dce_v10_0_afmt_update_ACR() 1710 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); dce_v10_0_afmt_update_ACR() 1711 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); dce_v10_0_afmt_update_ACR() 1747 u32 tmp; dce_v10_0_audio_set_dto() local 1757 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); dce_v10_0_audio_set_dto() 1758 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, dce_v10_0_audio_set_dto() 1760 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); dce_v10_0_audio_set_dto() 1779 u32 tmp; dce_v10_0_afmt_setmode() local 1801 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); dce_v10_0_afmt_setmode() 1802 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); dce_v10_0_afmt_setmode() 1803 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ dce_v10_0_afmt_setmode() 1807 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); dce_v10_0_afmt_setmode() 1814 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); dce_v10_0_afmt_setmode() 1815 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); dce_v10_0_afmt_setmode() 1820 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); dce_v10_0_afmt_setmode() 1821 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); dce_v10_0_afmt_setmode() 1826 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); dce_v10_0_afmt_setmode() 1827 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); dce_v10_0_afmt_setmode() 1832 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); dce_v10_0_afmt_setmode() 1834 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); dce_v10_0_afmt_setmode() 1835 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ dce_v10_0_afmt_setmode() 1836 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ dce_v10_0_afmt_setmode() 1837 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ dce_v10_0_afmt_setmode() 1838 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); dce_v10_0_afmt_setmode() 1840 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); dce_v10_0_afmt_setmode() 1842 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); dce_v10_0_afmt_setmode() 1844 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); dce_v10_0_afmt_setmode() 1845 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); dce_v10_0_afmt_setmode() 1847 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); dce_v10_0_afmt_setmode() 1849 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); dce_v10_0_afmt_setmode() 1850 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); dce_v10_0_afmt_setmode() 1852 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); dce_v10_0_afmt_setmode() 1854 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); dce_v10_0_afmt_setmode() 1855 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); dce_v10_0_afmt_setmode() 1859 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); dce_v10_0_afmt_setmode() 1861 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); dce_v10_0_afmt_setmode() 1863 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); dce_v10_0_afmt_setmode() 1864 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); dce_v10_0_afmt_setmode() 1866 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); dce_v10_0_afmt_setmode() 1868 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); dce_v10_0_afmt_setmode() 1869 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); dce_v10_0_afmt_setmode() 1871 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); dce_v10_0_afmt_setmode() 1874 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); dce_v10_0_afmt_setmode() 1877 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); dce_v10_0_afmt_setmode() 1879 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); dce_v10_0_afmt_setmode() 1880 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); dce_v10_0_afmt_setmode() 1884 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); dce_v10_0_afmt_setmode() 1885 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); dce_v10_0_afmt_setmode() 1886 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); dce_v10_0_afmt_setmode() 1888 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); dce_v10_0_afmt_setmode() 1889 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); dce_v10_0_afmt_setmode() 1890 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); dce_v10_0_afmt_setmode() 1892 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); dce_v10_0_afmt_setmode() 1893 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); dce_v10_0_afmt_setmode() 1894 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); dce_v10_0_afmt_setmode() 1895 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); dce_v10_0_afmt_setmode() 1896 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); dce_v10_0_afmt_setmode() 1897 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); dce_v10_0_afmt_setmode() 1898 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); dce_v10_0_afmt_setmode() 1899 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); dce_v10_0_afmt_setmode() 1924 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); dce_v10_0_afmt_setmode() 1926 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); dce_v10_0_afmt_setmode() 1928 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); dce_v10_0_afmt_setmode() 1929 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); dce_v10_0_afmt_setmode() 1931 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); dce_v10_0_afmt_setmode() 1932 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); dce_v10_0_afmt_setmode() 1933 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); dce_v10_0_afmt_setmode() 1935 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); dce_v10_0_afmt_setmode() 1937 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); dce_v10_0_afmt_setmode() 1938 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); dce_v10_0_afmt_setmode() 2054 u32 tmp, viewport_w, viewport_h; dce_v10_0_crtc_do_set_base() local 2220 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); dce_v10_0_crtc_do_set_base() 2222 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); dce_v10_0_crtc_do_set_base() 2224 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); dce_v10_0_crtc_do_set_base() 2225 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_crtc_do_set_base() 2256 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); dce_v10_0_crtc_do_set_base() 2257 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, dce_v10_0_crtc_do_set_base() 2259 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_crtc_do_set_base() 2286 u32 tmp; dce_v10_0_set_interleave() local 2288 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); dce_v10_0_set_interleave() 2290 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); dce_v10_0_set_interleave() 2292 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); dce_v10_0_set_interleave() 2293 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_set_interleave() 2302 u32 tmp; dce_v10_0_crtc_load_lut() local 2306 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); dce_v10_0_crtc_load_lut() 2307 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); dce_v10_0_crtc_load_lut() 2308 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0); dce_v10_0_crtc_load_lut() 2309 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_crtc_load_lut() 2311 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); dce_v10_0_crtc_load_lut() 2312 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); dce_v10_0_crtc_load_lut() 2313 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_crtc_load_lut() 2315 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); dce_v10_0_crtc_load_lut() 2316 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1); dce_v10_0_crtc_load_lut() 2317 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_crtc_load_lut() 2319 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); dce_v10_0_crtc_load_lut() 2320 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); dce_v10_0_crtc_load_lut() 2321 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0); dce_v10_0_crtc_load_lut() 2322 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_crtc_load_lut() 2345 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); dce_v10_0_crtc_load_lut() 2346 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); dce_v10_0_crtc_load_lut() 2347 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0); dce_v10_0_crtc_load_lut() 2348 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); dce_v10_0_crtc_load_lut() 2349 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_crtc_load_lut() 2351 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); dce_v10_0_crtc_load_lut() 2352 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); dce_v10_0_crtc_load_lut() 2353 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0); dce_v10_0_crtc_load_lut() 2354 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_crtc_load_lut() 2356 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); dce_v10_0_crtc_load_lut() 2357 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); dce_v10_0_crtc_load_lut() 2358 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0); dce_v10_0_crtc_load_lut() 2359 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_crtc_load_lut() 2361 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); dce_v10_0_crtc_load_lut() 2362 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); dce_v10_0_crtc_load_lut() 2363 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0); dce_v10_0_crtc_load_lut() 2364 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_crtc_load_lut() 2371 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); dce_v10_0_crtc_load_lut() 2372 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); dce_v10_0_crtc_load_lut() 2373 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_crtc_load_lut() 2486 u32 tmp; dce_v10_0_hide_cursor() local 2488 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); dce_v10_0_hide_cursor() 2489 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); dce_v10_0_hide_cursor() 2490 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_hide_cursor() 2497 u32 tmp; dce_v10_0_show_cursor() local 2504 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); dce_v10_0_show_cursor() 2505 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); dce_v10_0_show_cursor() 2506 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); dce_v10_0_show_cursor() 2507 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v10_0_show_cursor() 3134 u32 srbm_soft_reset = 0, tmp; dce_v10_0_soft_reset() local 3143 tmp = RREG32(mmSRBM_SOFT_RESET); dce_v10_0_soft_reset() 3144 tmp |= srbm_soft_reset; dce_v10_0_soft_reset() 3145 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); dce_v10_0_soft_reset() 3146 WREG32(mmSRBM_SOFT_RESET, tmp); dce_v10_0_soft_reset() 3147 tmp = RREG32(mmSRBM_SOFT_RESET); dce_v10_0_soft_reset() 3151 tmp &= ~srbm_soft_reset; dce_v10_0_soft_reset() 3152 WREG32(mmSRBM_SOFT_RESET, tmp); dce_v10_0_soft_reset() 3153 tmp = RREG32(mmSRBM_SOFT_RESET); dce_v10_0_soft_reset() 3225 u32 tmp; dce_v10_0_set_hpd_irq_state() local 3234 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); dce_v10_0_set_hpd_irq_state() 3235 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); dce_v10_0_set_hpd_irq_state() 3236 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); dce_v10_0_set_hpd_irq_state() 3239 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); dce_v10_0_set_hpd_irq_state() 3240 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); dce_v10_0_set_hpd_irq_state() 3241 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); dce_v10_0_set_hpd_irq_state() 3377 u32 tmp; dce_v10_0_hpd_int_ack() local 3384 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); dce_v10_0_hpd_int_ack() 3385 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); dce_v10_0_hpd_int_ack() 3386 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); dce_v10_0_hpd_int_ack() 3392 u32 tmp; dce_v10_0_crtc_vblank_int_ack() local 3399 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); dce_v10_0_crtc_vblank_int_ack() 3400 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); dce_v10_0_crtc_vblank_int_ack() 3401 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); dce_v10_0_crtc_vblank_int_ack() 3407 u32 tmp; dce_v10_0_crtc_vline_int_ack() local 3414 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); dce_v10_0_crtc_vline_int_ack() 3415 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); dce_v10_0_crtc_vline_int_ack() 3416 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); dce_v10_0_crtc_vline_int_ack()
H A D	dce_v11_0.c	359 u32 tmp; dce_v11_0_hpd_set_polarity() local 386 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); dce_v11_0_hpd_set_polarity() 388 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); dce_v11_0_hpd_set_polarity() 390 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); dce_v11_0_hpd_set_polarity() 391 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); dce_v11_0_hpd_set_polarity() 406 u32 tmp; dce_v11_0_hpd_init() local 445 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); dce_v11_0_hpd_init() 446 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); dce_v11_0_hpd_init() 447 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); dce_v11_0_hpd_init() 449 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); dce_v11_0_hpd_init() 450 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, dce_v11_0_hpd_init() 453 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, dce_v11_0_hpd_init() 456 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); dce_v11_0_hpd_init() 475 u32 tmp; dce_v11_0_hpd_fini() local 504 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); dce_v11_0_hpd_fini() 505 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); dce_v11_0_hpd_fini() 506 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); dce_v11_0_hpd_fini() 521 u32 i, j, tmp; dce_v11_0_is_display_hung() local 524 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); dce_v11_0_is_display_hung() 525 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { dce_v11_0_is_display_hung() 534 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); dce_v11_0_is_display_hung() 535 if (tmp != crtc_status[i]) dce_v11_0_is_display_hung() 550 u32 crtc_enabled, tmp; dce_v11_0_stop_mc_access() local 557 tmp = RREG32(mmVGA_RENDER_CONTROL); dce_v11_0_stop_mc_access() 558 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); dce_v11_0_stop_mc_access() 559 WREG32(mmVGA_RENDER_CONTROL, tmp); dce_v11_0_stop_mc_access() 571 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); dce_v11_0_stop_mc_access() 572 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { dce_v11_0_stop_mc_access() 575 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); dce_v11_0_stop_mc_access() 576 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); dce_v11_0_stop_mc_access() 586 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); dce_v11_0_stop_mc_access() 587 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { dce_v11_0_stop_mc_access() 588 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); dce_v11_0_stop_mc_access() 589 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); dce_v11_0_stop_mc_access() 591 tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); dce_v11_0_stop_mc_access() 592 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { dce_v11_0_stop_mc_access() 593 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); dce_v11_0_stop_mc_access() 594 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); dce_v11_0_stop_mc_access() 599 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); dce_v11_0_stop_mc_access() 600 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); dce_v11_0_stop_mc_access() 601 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); dce_v11_0_stop_mc_access() 615 u32 tmp, frame_count; dce_v11_0_resume_mc_access() local 630 tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]); dce_v11_0_resume_mc_access() 631 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { dce_v11_0_resume_mc_access() 632 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); dce_v11_0_resume_mc_access() 633 WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); dce_v11_0_resume_mc_access() 635 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); dce_v11_0_resume_mc_access() 636 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { dce_v11_0_resume_mc_access() 637 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); dce_v11_0_resume_mc_access() 638 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); dce_v11_0_resume_mc_access() 640 tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); dce_v11_0_resume_mc_access() 641 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { dce_v11_0_resume_mc_access() 642 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); dce_v11_0_resume_mc_access() 643 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); dce_v11_0_resume_mc_access() 646 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); dce_v11_0_resume_mc_access() 647 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) dce_v11_0_resume_mc_access() 651 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); dce_v11_0_resume_mc_access() 652 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); dce_v11_0_resume_mc_access() 654 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); dce_v11_0_resume_mc_access() 678 u32 tmp; dce_v11_0_set_vga_render_state() local 681 tmp = RREG32(mmVGA_HDP_CONTROL); dce_v11_0_set_vga_render_state() 683 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); dce_v11_0_set_vga_render_state() 685 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); dce_v11_0_set_vga_render_state() 686 WREG32(mmVGA_HDP_CONTROL, tmp); dce_v11_0_set_vga_render_state() 689 tmp = RREG32(mmVGA_RENDER_CONTROL); dce_v11_0_set_vga_render_state() 691 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); dce_v11_0_set_vga_render_state() 693 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); dce_v11_0_set_vga_render_state() 694 WREG32(mmVGA_RENDER_CONTROL, tmp); dce_v11_0_set_vga_render_state() 705 u32 tmp = 0; dce_v11_0_program_fmt() local 730 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); dce_v11_0_program_fmt() 731 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); dce_v11_0_program_fmt() 732 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); dce_v11_0_program_fmt() 733 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); dce_v11_0_program_fmt() 735 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); dce_v11_0_program_fmt() 736 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); dce_v11_0_program_fmt() 742 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); dce_v11_0_program_fmt() 743 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); dce_v11_0_program_fmt() 744 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); dce_v11_0_program_fmt() 745 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); dce_v11_0_program_fmt() 746 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); dce_v11_0_program_fmt() 748 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); dce_v11_0_program_fmt() 749 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); dce_v11_0_program_fmt() 755 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); dce_v11_0_program_fmt() 756 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); dce_v11_0_program_fmt() 757 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); dce_v11_0_program_fmt() 758 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); dce_v11_0_program_fmt() 759 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); dce_v11_0_program_fmt() 761 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); dce_v11_0_program_fmt() 762 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); dce_v11_0_program_fmt() 770 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_program_fmt() 791 u32 tmp, buffer_alloc, i, mem_cfg; dce_v11_0_line_buffer_adjust() local 821 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); dce_v11_0_line_buffer_adjust() 822 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); dce_v11_0_line_buffer_adjust() 823 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_line_buffer_adjust() 825 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); dce_v11_0_line_buffer_adjust() 826 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); dce_v11_0_line_buffer_adjust() 827 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); dce_v11_0_line_buffer_adjust() 830 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); dce_v11_0_line_buffer_adjust() 831 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) dce_v11_0_line_buffer_adjust() 863 u32 tmp = RREG32(mmMC_SHARED_CHMAP); cik_get_number_of_dram_channels() local 865 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { cik_get_number_of_dram_channels() 1095 u32 tmp, dmif_size = 12288; dce_v11_0_latency_watermark() local 1122 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); dce_v11_0_latency_watermark() 1130 lb_fill_bw = min(tmp, dfixed_trunc(b)); dce_v11_0_latency_watermark() 1241 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; dce_v11_0_program_watermarks() local 1329 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); dce_v11_0_program_watermarks() 1330 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_program_watermarks() 1331 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); dce_v11_0_program_watermarks() 1332 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); dce_v11_0_program_watermarks() 1333 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); dce_v11_0_program_watermarks() 1334 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_program_watermarks() 1336 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); dce_v11_0_program_watermarks() 1337 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_program_watermarks() 1338 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); dce_v11_0_program_watermarks() 1339 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); dce_v11_0_program_watermarks() 1340 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); dce_v11_0_program_watermarks() 1341 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_program_watermarks() 1384 u32 offset, tmp; dce_v11_0_audio_get_connected_pins() local 1388 tmp = RREG32_AUDIO_ENDPT(offset, dce_v11_0_audio_get_connected_pins() 1390 if (((tmp & dce_v11_0_audio_get_connected_pins() 1418 u32 tmp; dce_v11_0_afmt_audio_select_pin() local 1423 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); dce_v11_0_afmt_audio_select_pin() 1424 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); dce_v11_0_afmt_audio_select_pin() 1425 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); dce_v11_0_afmt_audio_select_pin() 1436 u32 tmp; dce_v11_0_audio_write_latency_fields() local 1457 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, dce_v11_0_audio_write_latency_fields() 1459 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, dce_v11_0_audio_write_latency_fields() 1462 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, dce_v11_0_audio_write_latency_fields() 1464 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, dce_v11_0_audio_write_latency_fields() 1468 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); dce_v11_0_audio_write_latency_fields() 1478 u32 tmp; dce_v11_0_audio_write_speaker_allocation() local 1504 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, dce_v11_0_audio_write_speaker_allocation() 1506 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, dce_v11_0_audio_write_speaker_allocation() 1509 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, dce_v11_0_audio_write_speaker_allocation() 1512 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, dce_v11_0_audio_write_speaker_allocation() 1515 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, dce_v11_0_audio_write_speaker_allocation() 1518 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); dce_v11_0_audio_write_speaker_allocation() 1571 u32 tmp = 0; dce_v11_0_audio_write_sad_regs() local 1581 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, dce_v11_0_audio_write_sad_regs() 1583 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, dce_v11_0_audio_write_sad_regs() 1585 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, dce_v11_0_audio_write_sad_regs() 1597 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, dce_v11_0_audio_write_sad_regs() 1599 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); dce_v11_0_audio_write_sad_regs() 1678 u32 tmp; dce_v11_0_afmt_update_ACR() local 1680 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); dce_v11_0_afmt_update_ACR() 1681 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); dce_v11_0_afmt_update_ACR() 1682 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); dce_v11_0_afmt_update_ACR() 1683 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); dce_v11_0_afmt_update_ACR() 1684 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); dce_v11_0_afmt_update_ACR() 1685 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); dce_v11_0_afmt_update_ACR() 1687 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); dce_v11_0_afmt_update_ACR() 1688 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); dce_v11_0_afmt_update_ACR() 1689 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); dce_v11_0_afmt_update_ACR() 1690 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); dce_v11_0_afmt_update_ACR() 1691 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); dce_v11_0_afmt_update_ACR() 1692 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); dce_v11_0_afmt_update_ACR() 1694 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); dce_v11_0_afmt_update_ACR() 1695 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); dce_v11_0_afmt_update_ACR() 1696 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); dce_v11_0_afmt_update_ACR() 1697 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); dce_v11_0_afmt_update_ACR() 1698 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); dce_v11_0_afmt_update_ACR() 1699 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); dce_v11_0_afmt_update_ACR() 1735 u32 tmp; dce_v11_0_audio_set_dto() local 1745 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); dce_v11_0_audio_set_dto() 1746 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, dce_v11_0_audio_set_dto() 1748 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); dce_v11_0_audio_set_dto() 1767 u32 tmp; dce_v11_0_afmt_setmode() local 1789 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); dce_v11_0_afmt_setmode() 1790 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); dce_v11_0_afmt_setmode() 1791 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ dce_v11_0_afmt_setmode() 1795 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); dce_v11_0_afmt_setmode() 1802 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); dce_v11_0_afmt_setmode() 1803 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); dce_v11_0_afmt_setmode() 1808 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); dce_v11_0_afmt_setmode() 1809 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); dce_v11_0_afmt_setmode() 1814 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); dce_v11_0_afmt_setmode() 1815 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); dce_v11_0_afmt_setmode() 1820 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); dce_v11_0_afmt_setmode() 1822 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); dce_v11_0_afmt_setmode() 1823 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ dce_v11_0_afmt_setmode() 1824 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ dce_v11_0_afmt_setmode() 1825 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ dce_v11_0_afmt_setmode() 1826 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); dce_v11_0_afmt_setmode() 1828 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); dce_v11_0_afmt_setmode() 1830 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); dce_v11_0_afmt_setmode() 1832 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); dce_v11_0_afmt_setmode() 1833 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); dce_v11_0_afmt_setmode() 1835 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); dce_v11_0_afmt_setmode() 1837 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); dce_v11_0_afmt_setmode() 1838 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); dce_v11_0_afmt_setmode() 1840 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); dce_v11_0_afmt_setmode() 1842 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); dce_v11_0_afmt_setmode() 1843 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); dce_v11_0_afmt_setmode() 1847 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); dce_v11_0_afmt_setmode() 1849 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); dce_v11_0_afmt_setmode() 1851 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); dce_v11_0_afmt_setmode() 1852 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); dce_v11_0_afmt_setmode() 1854 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); dce_v11_0_afmt_setmode() 1856 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); dce_v11_0_afmt_setmode() 1857 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); dce_v11_0_afmt_setmode() 1859 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); dce_v11_0_afmt_setmode() 1862 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); dce_v11_0_afmt_setmode() 1865 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); dce_v11_0_afmt_setmode() 1867 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); dce_v11_0_afmt_setmode() 1868 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); dce_v11_0_afmt_setmode() 1872 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); dce_v11_0_afmt_setmode() 1873 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); dce_v11_0_afmt_setmode() 1874 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); dce_v11_0_afmt_setmode() 1876 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); dce_v11_0_afmt_setmode() 1877 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); dce_v11_0_afmt_setmode() 1878 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); dce_v11_0_afmt_setmode() 1880 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); dce_v11_0_afmt_setmode() 1881 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); dce_v11_0_afmt_setmode() 1882 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); dce_v11_0_afmt_setmode() 1883 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); dce_v11_0_afmt_setmode() 1884 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); dce_v11_0_afmt_setmode() 1885 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); dce_v11_0_afmt_setmode() 1886 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); dce_v11_0_afmt_setmode() 1887 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); dce_v11_0_afmt_setmode() 1912 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); dce_v11_0_afmt_setmode() 1914 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); dce_v11_0_afmt_setmode() 1916 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); dce_v11_0_afmt_setmode() 1917 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); dce_v11_0_afmt_setmode() 1919 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); dce_v11_0_afmt_setmode() 1920 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); dce_v11_0_afmt_setmode() 1921 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); dce_v11_0_afmt_setmode() 1923 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); dce_v11_0_afmt_setmode() 1925 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); dce_v11_0_afmt_setmode() 1926 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); dce_v11_0_afmt_setmode() 2042 u32 tmp, viewport_w, viewport_h; dce_v11_0_crtc_do_set_base() local 2208 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); dce_v11_0_crtc_do_set_base() 2210 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); dce_v11_0_crtc_do_set_base() 2212 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); dce_v11_0_crtc_do_set_base() 2213 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_crtc_do_set_base() 2244 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); dce_v11_0_crtc_do_set_base() 2245 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, dce_v11_0_crtc_do_set_base() 2247 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_crtc_do_set_base() 2274 u32 tmp; dce_v11_0_set_interleave() local 2276 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); dce_v11_0_set_interleave() 2278 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); dce_v11_0_set_interleave() 2280 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); dce_v11_0_set_interleave() 2281 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_set_interleave() 2290 u32 tmp; dce_v11_0_crtc_load_lut() local 2294 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); dce_v11_0_crtc_load_lut() 2295 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); dce_v11_0_crtc_load_lut() 2296 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_crtc_load_lut() 2298 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); dce_v11_0_crtc_load_lut() 2299 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); dce_v11_0_crtc_load_lut() 2300 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_crtc_load_lut() 2302 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); dce_v11_0_crtc_load_lut() 2303 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); dce_v11_0_crtc_load_lut() 2304 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_crtc_load_lut() 2327 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); dce_v11_0_crtc_load_lut() 2328 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); dce_v11_0_crtc_load_lut() 2329 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); dce_v11_0_crtc_load_lut() 2330 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0); dce_v11_0_crtc_load_lut() 2331 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_crtc_load_lut() 2333 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); dce_v11_0_crtc_load_lut() 2334 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); dce_v11_0_crtc_load_lut() 2335 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_crtc_load_lut() 2337 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); dce_v11_0_crtc_load_lut() 2338 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); dce_v11_0_crtc_load_lut() 2339 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_crtc_load_lut() 2341 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); dce_v11_0_crtc_load_lut() 2342 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); dce_v11_0_crtc_load_lut() 2343 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_crtc_load_lut() 2350 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); dce_v11_0_crtc_load_lut() 2351 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); dce_v11_0_crtc_load_lut() 2352 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_crtc_load_lut() 2475 u32 tmp; dce_v11_0_hide_cursor() local 2477 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); dce_v11_0_hide_cursor() 2478 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); dce_v11_0_hide_cursor() 2479 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_hide_cursor() 2486 u32 tmp; dce_v11_0_show_cursor() local 2493 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); dce_v11_0_show_cursor() 2494 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); dce_v11_0_show_cursor() 2495 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); dce_v11_0_show_cursor() 2496 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); dce_v11_0_show_cursor() 3127 u32 srbm_soft_reset = 0, tmp; dce_v11_0_soft_reset() local 3136 tmp = RREG32(mmSRBM_SOFT_RESET); dce_v11_0_soft_reset() 3137 tmp |= srbm_soft_reset; dce_v11_0_soft_reset() 3138 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); dce_v11_0_soft_reset() 3139 WREG32(mmSRBM_SOFT_RESET, tmp); dce_v11_0_soft_reset() 3140 tmp = RREG32(mmSRBM_SOFT_RESET); dce_v11_0_soft_reset() 3144 tmp &= ~srbm_soft_reset; dce_v11_0_soft_reset() 3145 WREG32(mmSRBM_SOFT_RESET, tmp); dce_v11_0_soft_reset() 3146 tmp = RREG32(mmSRBM_SOFT_RESET); dce_v11_0_soft_reset() 3218 u32 tmp; dce_v11_0_set_hpd_irq_state() local 3227 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); dce_v11_0_set_hpd_irq_state() 3228 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); dce_v11_0_set_hpd_irq_state() 3229 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); dce_v11_0_set_hpd_irq_state() 3232 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); dce_v11_0_set_hpd_irq_state() 3233 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); dce_v11_0_set_hpd_irq_state() 3234 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); dce_v11_0_set_hpd_irq_state() 3370 u32 tmp; dce_v11_0_hpd_int_ack() local 3377 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); dce_v11_0_hpd_int_ack() 3378 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); dce_v11_0_hpd_int_ack() 3379 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); dce_v11_0_hpd_int_ack() 3385 u32 tmp; dce_v11_0_crtc_vblank_int_ack() local 3392 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); dce_v11_0_crtc_vblank_int_ack() 3393 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); dce_v11_0_crtc_vblank_int_ack() 3394 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); dce_v11_0_crtc_vblank_int_ack() 3400 u32 tmp; dce_v11_0_crtc_vline_int_ack() local 3407 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); dce_v11_0_crtc_vline_int_ack() 3408 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); dce_v11_0_crtc_vline_int_ack() 3409 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); dce_v11_0_crtc_vline_int_ack()
H A D	gmc_v7_0.c	88 u32 tmp; gmc_v7_0_mc_wait_for_idle() local 92 tmp = RREG32(mmSRBM_STATUS) & 0x1F00; gmc_v7_0_mc_wait_for_idle() 93 if (!tmp) gmc_v7_0_mc_wait_for_idle() 126 u32 tmp; gmc_v7_0_mc_resume() local 129 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); gmc_v7_0_mc_resume() 130 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); gmc_v7_0_mc_resume() 131 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); gmc_v7_0_mc_resume() 133 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); gmc_v7_0_mc_resume() 134 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); gmc_v7_0_mc_resume() 135 WREG32(mmBIF_FB_EN, tmp); gmc_v7_0_mc_resume() 297 u32 tmp; gmc_v7_0_mc_program() local 324 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; gmc_v7_0_mc_program() 325 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); gmc_v7_0_mc_program() 326 WREG32(mmMC_VM_FB_LOCATION, tmp); gmc_v7_0_mc_program() 341 tmp = RREG32(mmHDP_MISC_CNTL); gmc_v7_0_mc_program() 342 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); gmc_v7_0_mc_program() 343 WREG32(mmHDP_MISC_CNTL, tmp); gmc_v7_0_mc_program() 345 tmp = RREG32(mmHDP_HOST_PATH_CNTL); gmc_v7_0_mc_program() 346 WREG32(mmHDP_HOST_PATH_CNTL, tmp); gmc_v7_0_mc_program() 360 u32 tmp; gmc_v7_0_mc_init() local 364 tmp = RREG32(mmMC_ARB_RAMCFG); gmc_v7_0_mc_init() 365 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { gmc_v7_0_mc_init() 370 tmp = RREG32(mmMC_SHARED_CHMAP); gmc_v7_0_mc_init() 371 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { gmc_v7_0_mc_init() 484 u32 tmp; gmc_v7_0_set_fault_enable_default() local 486 tmp = RREG32(mmVM_CONTEXT1_CNTL); gmc_v7_0_set_fault_enable_default() 487 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, gmc_v7_0_set_fault_enable_default() 489 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, gmc_v7_0_set_fault_enable_default() 491 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, gmc_v7_0_set_fault_enable_default() 493 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, gmc_v7_0_set_fault_enable_default() 495 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, gmc_v7_0_set_fault_enable_default() 497 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, gmc_v7_0_set_fault_enable_default() 499 WREG32(mmVM_CONTEXT1_CNTL, tmp); gmc_v7_0_set_fault_enable_default() 516 u32 tmp; gmc_v7_0_gart_enable() local 526 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); gmc_v7_0_gart_enable() 527 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); gmc_v7_0_gart_enable() 528 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); gmc_v7_0_gart_enable() 529 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); gmc_v7_0_gart_enable() 530 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); gmc_v7_0_gart_enable() 531 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); gmc_v7_0_gart_enable() 532 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); gmc_v7_0_gart_enable() 534 tmp = RREG32(mmVM_L2_CNTL); gmc_v7_0_gart_enable() 535 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); gmc_v7_0_gart_enable() 536 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); gmc_v7_0_gart_enable() 537 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); gmc_v7_0_gart_enable() 538 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); gmc_v7_0_gart_enable() 539 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); gmc_v7_0_gart_enable() 540 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); gmc_v7_0_gart_enable() 541 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); gmc_v7_0_gart_enable() 542 WREG32(mmVM_L2_CNTL, tmp); gmc_v7_0_gart_enable() 543 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); gmc_v7_0_gart_enable() 544 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); gmc_v7_0_gart_enable() 545 WREG32(mmVM_L2_CNTL2, tmp); gmc_v7_0_gart_enable() 546 tmp = RREG32(mmVM_L2_CNTL3); gmc_v7_0_gart_enable() 547 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); gmc_v7_0_gart_enable() 548 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); gmc_v7_0_gart_enable() 549 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); gmc_v7_0_gart_enable() 550 WREG32(mmVM_L2_CNTL3, tmp); gmc_v7_0_gart_enable() 558 tmp = RREG32(mmVM_CONTEXT0_CNTL); gmc_v7_0_gart_enable() 559 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); gmc_v7_0_gart_enable() 560 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); gmc_v7_0_gart_enable() 561 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); gmc_v7_0_gart_enable() 562 WREG32(mmVM_CONTEXT0_CNTL, tmp); gmc_v7_0_gart_enable() 588 tmp = RREG32(mmVM_CONTEXT1_CNTL); gmc_v7_0_gart_enable() 589 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); gmc_v7_0_gart_enable() 590 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); gmc_v7_0_gart_enable() 591 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, gmc_v7_0_gart_enable() 593 WREG32(mmVM_CONTEXT1_CNTL, tmp); gmc_v7_0_gart_enable() 600 tmp = RREG32(mmCHUB_CONTROL); gmc_v7_0_gart_enable() 601 tmp &= ~BYPASS_VM; gmc_v7_0_gart_enable() 602 WREG32(mmCHUB_CONTROL, tmp); gmc_v7_0_gart_enable() 638 u32 tmp; gmc_v7_0_gart_disable() local 644 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); gmc_v7_0_gart_disable() 645 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); gmc_v7_0_gart_disable() 646 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); gmc_v7_0_gart_disable() 647 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); gmc_v7_0_gart_disable() 648 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); gmc_v7_0_gart_disable() 650 tmp = RREG32(mmVM_L2_CNTL); gmc_v7_0_gart_disable() 651 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); gmc_v7_0_gart_disable() 652 WREG32(mmVM_L2_CNTL, tmp); gmc_v7_0_gart_disable() 697 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); gmc_v7_0_vm_init() local 698 tmp <<= 22; gmc_v7_0_vm_init() 699 adev->vm_manager.vram_base_offset = tmp; gmc_v7_0_vm_init() 924 u32 tmp = RREG32(mmMC_SEQ_MISC0); gmc_v7_0_sw_init() local 925 tmp &= MC_SEQ_MISC0__MT__MASK; gmc_v7_0_sw_init() 926 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp); gmc_v7_0_sw_init() 1087 u32 tmp = RREG32(mmSRBM_STATUS); gmc_v7_0_is_idle() local 1089 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | gmc_v7_0_is_idle() 1099 u32 tmp; gmc_v7_0_wait_for_idle() local 1104 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | gmc_v7_0_wait_for_idle() 1109 if (!tmp) gmc_v7_0_wait_for_idle() 1230 u32 tmp = RREG32(mmSRBM_STATUS); gmc_v7_0_soft_reset() local 1232 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) gmc_v7_0_soft_reset() 1236 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | gmc_v7_0_soft_reset() 1252 tmp = RREG32(mmSRBM_SOFT_RESET); gmc_v7_0_soft_reset() 1253 tmp |= srbm_soft_reset; gmc_v7_0_soft_reset() 1254 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); gmc_v7_0_soft_reset() 1255 WREG32(mmSRBM_SOFT_RESET, tmp); gmc_v7_0_soft_reset() 1256 tmp = RREG32(mmSRBM_SOFT_RESET); gmc_v7_0_soft_reset() 1260 tmp &= ~srbm_soft_reset; gmc_v7_0_soft_reset() 1261 WREG32(mmSRBM_SOFT_RESET, tmp); gmc_v7_0_soft_reset() 1262 tmp = RREG32(mmSRBM_SOFT_RESET); gmc_v7_0_soft_reset() 1281 u32 tmp; gmc_v7_0_vm_fault_interrupt_state() local 1292 tmp = RREG32(mmVM_CONTEXT0_CNTL); gmc_v7_0_vm_fault_interrupt_state() 1293 tmp &= ~bits; gmc_v7_0_vm_fault_interrupt_state() 1294 WREG32(mmVM_CONTEXT0_CNTL, tmp); gmc_v7_0_vm_fault_interrupt_state() 1296 tmp = RREG32(mmVM_CONTEXT1_CNTL); gmc_v7_0_vm_fault_interrupt_state() 1297 tmp &= ~bits; gmc_v7_0_vm_fault_interrupt_state() 1298 WREG32(mmVM_CONTEXT1_CNTL, tmp); gmc_v7_0_vm_fault_interrupt_state() 1302 tmp = RREG32(mmVM_CONTEXT0_CNTL); gmc_v7_0_vm_fault_interrupt_state() 1303 tmp |= bits; gmc_v7_0_vm_fault_interrupt_state() 1304 WREG32(mmVM_CONTEXT0_CNTL, tmp); gmc_v7_0_vm_fault_interrupt_state() 1306 tmp = RREG32(mmVM_CONTEXT1_CNTL); gmc_v7_0_vm_fault_interrupt_state() 1307 tmp |= bits; gmc_v7_0_vm_fault_interrupt_state() 1308 WREG32(mmVM_CONTEXT1_CNTL, tmp); gmc_v7_0_vm_fault_interrupt_state()
H A D	vce_v2_0.c	305 u32 tmp; vce_v2_0_set_sw_cg() local 308 tmp = RREG32(mmVCE_CLOCK_GATING_B); vce_v2_0_set_sw_cg() 309 tmp |= 0xe70000; vce_v2_0_set_sw_cg() 310 WREG32(mmVCE_CLOCK_GATING_B, tmp); vce_v2_0_set_sw_cg() 312 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); vce_v2_0_set_sw_cg() 313 tmp |= 0xff000000; vce_v2_0_set_sw_cg() 314 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); vce_v2_0_set_sw_cg() 316 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING); vce_v2_0_set_sw_cg() 317 tmp &= ~0x3fc; vce_v2_0_set_sw_cg() 318 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp); vce_v2_0_set_sw_cg() 322 tmp = RREG32(mmVCE_CLOCK_GATING_B); vce_v2_0_set_sw_cg() 323 tmp |= 0xe7; vce_v2_0_set_sw_cg() 324 tmp &= ~0xe70000; vce_v2_0_set_sw_cg() 325 WREG32(mmVCE_CLOCK_GATING_B, tmp); vce_v2_0_set_sw_cg() 327 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); vce_v2_0_set_sw_cg() 328 tmp |= 0x1fe000; vce_v2_0_set_sw_cg() 329 tmp &= ~0xff000000; vce_v2_0_set_sw_cg() 330 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); vce_v2_0_set_sw_cg() 332 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING); vce_v2_0_set_sw_cg() 333 tmp |= 0x3fc; vce_v2_0_set_sw_cg() 334 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp); vce_v2_0_set_sw_cg() 340 u32 orig, tmp; vce_v2_0_set_dyn_cg() local 342 tmp = RREG32(mmVCE_CLOCK_GATING_B); vce_v2_0_set_dyn_cg() 343 tmp &= ~0x00060006; vce_v2_0_set_dyn_cg() 345 tmp |= 0xe10000; vce_v2_0_set_dyn_cg() 347 tmp |= 0xe1; vce_v2_0_set_dyn_cg() 348 tmp &= ~0xe10000; vce_v2_0_set_dyn_cg() 350 WREG32(mmVCE_CLOCK_GATING_B, tmp); vce_v2_0_set_dyn_cg() 352 orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING); vce_v2_0_set_dyn_cg() 353 tmp &= ~0x1fe000; vce_v2_0_set_dyn_cg() 354 tmp &= ~0xff000000; vce_v2_0_set_dyn_cg() 355 if (tmp != orig) vce_v2_0_set_dyn_cg() 356 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); vce_v2_0_set_dyn_cg() 358 orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING); vce_v2_0_set_dyn_cg() 359 tmp &= ~0x3fc; vce_v2_0_set_dyn_cg() 360 if (tmp != orig) vce_v2_0_set_dyn_cg() 361 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp); vce_v2_0_set_dyn_cg() 393 u32 tmp; vce_v2_0_init_cg() local 395 tmp = RREG32(mmVCE_CLOCK_GATING_A); vce_v2_0_init_cg() 396 tmp &= ~0xfff; vce_v2_0_init_cg() 397 tmp |= ((0 << 0) | (4 << 4)); vce_v2_0_init_cg() 398 tmp |= 0x40000; vce_v2_0_init_cg() 399 WREG32(mmVCE_CLOCK_GATING_A, tmp); vce_v2_0_init_cg() 401 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); vce_v2_0_init_cg() 402 tmp &= ~0xfff; vce_v2_0_init_cg() 403 tmp |= ((0 << 0) | (4 << 4)); vce_v2_0_init_cg() 404 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); vce_v2_0_init_cg() 406 tmp = RREG32(mmVCE_CLOCK_GATING_B); vce_v2_0_init_cg() 407 tmp |= 0x10; vce_v2_0_init_cg() 408 tmp &= ~0x100000; vce_v2_0_init_cg() 409 WREG32(mmVCE_CLOCK_GATING_B, tmp); vce_v2_0_init_cg()
H A D	vi.c	291 u32 tmp; vi_get_xclk() local 296 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); vi_get_xclk() 297 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK)) vi_get_xclk() 300 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL); vi_get_xclk() 301 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE)) vi_get_xclk() 594 u32 tmp; vi_gpu_check_soft_reset() local 597 tmp = RREG32(mmGRBM_STATUS); vi_gpu_check_soft_reset() 598 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | vi_gpu_check_soft_reset() 606 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) vi_gpu_check_soft_reset() 610 tmp = RREG32(mmGRBM_STATUS2); vi_gpu_check_soft_reset() 611 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK) vi_gpu_check_soft_reset() 614 if (tmp & (GRBM_STATUS2__CPF_BUSY_MASK | vi_gpu_check_soft_reset() 620 tmp = RREG32(mmSRBM_STATUS2); vi_gpu_check_soft_reset() 621 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) vi_gpu_check_soft_reset() 624 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) vi_gpu_check_soft_reset() 628 tmp = RREG32(mmSRBM_STATUS); vi_gpu_check_soft_reset() 630 if (tmp & SRBM_STATUS__IH_BUSY_MASK) vi_gpu_check_soft_reset() 633 if (tmp & SRBM_STATUS__SEM_BUSY_MASK) vi_gpu_check_soft_reset() 636 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK) vi_gpu_check_soft_reset() 640 if (tmp & (SRBM_STATUS__UVD_RQ_PENDING_MASK | vi_gpu_check_soft_reset() 645 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) vi_gpu_check_soft_reset() 648 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | vi_gpu_check_soft_reset() 653 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET); vi_gpu_check_soft_reset() 654 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) vi_gpu_check_soft_reset() 659 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); vi_gpu_check_soft_reset() 660 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) vi_gpu_check_soft_reset() 666 tmp = RREG32(mmVCE_STATUS); vi_gpu_check_soft_reset() 667 if (tmp & VCE_STATUS__VCPU_REPORT_RB0_BUSY_MASK) vi_gpu_check_soft_reset() 669 if (tmp & VCE_STATUS__VCPU_REPORT_RB1_BUSY_MASK) vi_gpu_check_soft_reset() 701 u32 tmp; vi_gpu_soft_reset() local 721 tmp = RREG32(mmCP_ME_CNTL); vi_gpu_soft_reset() 722 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); vi_gpu_soft_reset() 723 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); vi_gpu_soft_reset() 724 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); vi_gpu_soft_reset() 725 WREG32(mmCP_ME_CNTL, tmp); vi_gpu_soft_reset() 728 tmp = RREG32(mmCP_MEC_CNTL); vi_gpu_soft_reset() 729 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1); vi_gpu_soft_reset() 730 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1); vi_gpu_soft_reset() 731 WREG32(mmCP_MEC_CNTL, tmp); vi_gpu_soft_reset() 735 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); vi_gpu_soft_reset() 736 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1); vi_gpu_soft_reset() 737 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); vi_gpu_soft_reset() 741 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); vi_gpu_soft_reset() 742 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1); vi_gpu_soft_reset() 743 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); vi_gpu_soft_reset() 816 tmp = RREG32(mmGRBM_SOFT_RESET); vi_gpu_soft_reset() 817 tmp |= grbm_soft_reset; vi_gpu_soft_reset() 818 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); vi_gpu_soft_reset() 819 WREG32(mmGRBM_SOFT_RESET, tmp); vi_gpu_soft_reset() 820 tmp = RREG32(mmGRBM_SOFT_RESET); vi_gpu_soft_reset() 824 tmp &= ~grbm_soft_reset; vi_gpu_soft_reset() 825 WREG32(mmGRBM_SOFT_RESET, tmp); vi_gpu_soft_reset() 826 tmp = RREG32(mmGRBM_SOFT_RESET); vi_gpu_soft_reset() 830 tmp = RREG32(mmSRBM_SOFT_RESET); vi_gpu_soft_reset() 831 tmp |= srbm_soft_reset; vi_gpu_soft_reset() 832 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); vi_gpu_soft_reset() 833 WREG32(mmSRBM_SOFT_RESET, tmp); vi_gpu_soft_reset() 834 tmp = RREG32(mmSRBM_SOFT_RESET); vi_gpu_soft_reset() 838 tmp &= ~srbm_soft_reset; vi_gpu_soft_reset() 839 WREG32(mmSRBM_SOFT_RESET, tmp); vi_gpu_soft_reset() 840 tmp = RREG32(mmSRBM_SOFT_RESET); vi_gpu_soft_reset() 855 u32 tmp, i; vi_gpu_pci_config_reset() local 864 tmp = RREG32(mmCP_ME_CNTL); vi_gpu_pci_config_reset() 865 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); vi_gpu_pci_config_reset() 866 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); vi_gpu_pci_config_reset() 867 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); vi_gpu_pci_config_reset() 868 WREG32(mmCP_ME_CNTL, tmp); vi_gpu_pci_config_reset() 871 tmp = RREG32(mmCP_MEC_CNTL); vi_gpu_pci_config_reset() 872 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1); vi_gpu_pci_config_reset() 873 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1); vi_gpu_pci_config_reset() 874 WREG32(mmCP_MEC_CNTL, tmp); vi_gpu_pci_config_reset() 885 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); vi_gpu_pci_config_reset() 886 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1); vi_gpu_pci_config_reset() 887 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); vi_gpu_pci_config_reset() 890 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); vi_gpu_pci_config_reset() 891 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1); vi_gpu_pci_config_reset() 892 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); vi_gpu_pci_config_reset() 926 u32 tmp = RREG32(mmBIOS_SCRATCH_3); vi_set_bios_scratch_engine_hung() local 929 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; vi_set_bios_scratch_engine_hung() 931 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; vi_set_bios_scratch_engine_hung() 933 WREG32(mmBIOS_SCRATCH_3, tmp); vi_set_bios_scratch_engine_hung() 976 uint32_t tmp; vi_set_uvd_clock() local 984 tmp = RREG32_SMC(cntl_reg); vi_set_uvd_clock() 985 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK | vi_set_uvd_clock() 987 tmp |= dividers.post_divider; vi_set_uvd_clock() 988 WREG32_SMC(cntl_reg, tmp); vi_set_uvd_clock() 1057 u32 tmp; vi_enable_doorbell_aperture() local 1063 tmp = RREG32(mmBIF_DOORBELL_APER_EN); vi_enable_doorbell_aperture() 1065 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1); vi_enable_doorbell_aperture() 1067 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0); vi_enable_doorbell_aperture() 1069 WREG32(mmBIF_DOORBELL_APER_EN, tmp); vi_enable_doorbell_aperture()
H A D	ci_smc.c	119 u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); amdgpu_ci_start_smc() local 121 tmp &= ~SMC_SYSCON_RESET_CNTL__rst_reg_MASK; amdgpu_ci_start_smc() 122 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp); amdgpu_ci_start_smc() 127 u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); amdgpu_ci_reset_smc() local 129 tmp |= SMC_SYSCON_RESET_CNTL__rst_reg_MASK; amdgpu_ci_reset_smc() 130 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp); amdgpu_ci_reset_smc() 142 u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); amdgpu_ci_stop_smc_clock() local 144 tmp |= SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK; amdgpu_ci_stop_smc_clock() 146 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp); amdgpu_ci_stop_smc_clock() 151 u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); amdgpu_ci_start_smc_clock() local 153 tmp &= ~SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK; amdgpu_ci_start_smc_clock() 155 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp); amdgpu_ci_start_smc_clock() 171 u32 tmp; amdgpu_ci_send_msg_to_smc() local 180 tmp = RREG32(mmSMC_RESP_0); amdgpu_ci_send_msg_to_smc() 181 if (tmp != 0) amdgpu_ci_send_msg_to_smc() 185 tmp = RREG32(mmSMC_RESP_0); amdgpu_ci_send_msg_to_smc() 187 return (PPSMC_Result)tmp; amdgpu_ci_send_msg_to_smc() 192 u32 tmp; amdgpu_ci_wait_for_smc_inactive() local 199 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); amdgpu_ci_wait_for_smc_inactive() 200 if ((tmp & SMC_SYSCON_CLOCK_CNTL_0__cken_MASK) == 0) amdgpu_ci_wait_for_smc_inactive()
/linux-4.4.14/arch/blackfin/include/asm/
H A D	timex.h	18 unsigned long tmp, tmp2; get_cycles() local 19 __asm__ __volatile__("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2)); get_cycles() 20 return tmp | ((cycles_t)tmp2 << 32); get_cycles()
H A D	cmpxchg.h	27 unsigned long tmp; __xchg() local 31 tmp = __raw_xchg_1_asm(ptr, x); __xchg() 34 tmp = __raw_xchg_2_asm(ptr, x); __xchg() 37 tmp = __raw_xchg_4_asm(ptr, x); __xchg() 41 return tmp; __xchg() 52 unsigned long tmp; __cmpxchg() local 56 tmp = __raw_cmpxchg_1_asm(ptr, new, old); __cmpxchg() 59 tmp = __raw_cmpxchg_2_asm(ptr, new, old); __cmpxchg() 62 tmp = __raw_cmpxchg_4_asm(ptr, new, old); __cmpxchg() 66 return tmp; __cmpxchg() 85 unsigned long tmp = 0; __xchg() local 95 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); __xchg() 101 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); __xchg() 107 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); __xchg() 111 return tmp; __xchg()
/linux-4.4.14/drivers/pnp/isapnp/
H A D	core.c	369 unsigned char tag, tmp[2]; isapnp_read_tag() local 376 isapnp_peek(tmp, 2); isapnp_read_tag() 377 *size = (tmp[1] << 8) | tmp[0]; isapnp_read_tag() 401 unsigned char tmp[6]; isapnp_parse_device() local 406 isapnp_peek(tmp, size); isapnp_parse_device() 407 eisa_id = tmp[0] | tmp[1] << 8 | tmp[2] << 16 | tmp[3] << 24; isapnp_parse_device() 430 unsigned char tmp[3]; isapnp_parse_irq_resource() local 435 isapnp_peek(tmp, size); isapnp_parse_irq_resource() 436 bits = (tmp[1] << 8) | tmp[0]; isapnp_parse_irq_resource() 442 flags = tmp[2]; isapnp_parse_irq_resource() 454 unsigned char tmp[2]; isapnp_parse_dma_resource() local 456 isapnp_peek(tmp, size); isapnp_parse_dma_resource() 457 pnp_register_dma_resource(dev, option_flags, tmp[0], tmp[1]); isapnp_parse_dma_resource() 467 unsigned char tmp[7]; isapnp_parse_port_resource() local 471 isapnp_peek(tmp, size); isapnp_parse_port_resource() 472 min = (tmp[2] << 8) | tmp[1]; isapnp_parse_port_resource() 473 max = (tmp[4] << 8) | tmp[3]; isapnp_parse_port_resource() 474 align = tmp[5]; isapnp_parse_port_resource() 475 len = tmp[6]; isapnp_parse_port_resource() 476 flags = tmp[0] ? IORESOURCE_IO_16BIT_ADDR : 0; isapnp_parse_port_resource() 488 unsigned char tmp[3]; isapnp_parse_fixed_port_resource() local 491 isapnp_peek(tmp, size); isapnp_parse_fixed_port_resource() 492 base = (tmp[1] << 8) | tmp[0]; isapnp_parse_fixed_port_resource() 493 len = tmp[2]; isapnp_parse_fixed_port_resource() 505 unsigned char tmp[9]; isapnp_parse_mem_resource() local 509 isapnp_peek(tmp, size); isapnp_parse_mem_resource() 510 min = ((tmp[2] << 8) | tmp[1]) << 8; isapnp_parse_mem_resource() 511 max = ((tmp[4] << 8) | tmp[3]) << 8; isapnp_parse_mem_resource() 512 align = (tmp[6] << 8) | tmp[5]; isapnp_parse_mem_resource() 513 len = ((tmp[8] << 8) | tmp[7]) << 8; isapnp_parse_mem_resource() 514 flags = tmp[0]; isapnp_parse_mem_resource() 526 unsigned char tmp[17]; isapnp_parse_mem32_resource() local 530 isapnp_peek(tmp, size); isapnp_parse_mem32_resource() 531 min = (tmp[4] << 24) | (tmp[3] << 16) | (tmp[2] << 8) | tmp[1]; isapnp_parse_mem32_resource() 532 max = (tmp[8] << 24) | (tmp[7] << 16) | (tmp[6] << 8) | tmp[5]; isapnp_parse_mem32_resource() 533 align = (tmp[12] << 24) | (tmp[11] << 16) | (tmp[10] << 8) | tmp[9]; isapnp_parse_mem32_resource() 534 len = (tmp[16] << 24) | (tmp[15] << 16) | (tmp[14] << 8) | tmp[13]; isapnp_parse_mem32_resource() 535 flags = tmp[0]; isapnp_parse_mem32_resource() 547 unsigned char tmp[9]; isapnp_parse_fixed_mem32_resource() local 551 isapnp_peek(tmp, size); isapnp_parse_fixed_mem32_resource() 552 base = (tmp[4] << 24) | (tmp[3] << 16) | (tmp[2] << 8) | tmp[1]; isapnp_parse_fixed_mem32_resource() 553 len = (tmp[8] << 24) | (tmp[7] << 16) | (tmp[6] << 8) | tmp[5]; isapnp_parse_fixed_mem32_resource() 554 flags = tmp[0]; isapnp_parse_fixed_mem32_resource() 584 unsigned char type, tmp[17]; isapnp_create_device() local 618 isapnp_peek(tmp, 4); isapnp_create_device() 619 eisa_id = tmp[0] | tmp[1] << 8 | isapnp_create_device() 620 tmp[2] << 16 | tmp[3] << 24; isapnp_create_device() 644 isapnp_peek(tmp, size); isapnp_create_device() 645 priority = tmp[0]; isapnp_create_device() 718 unsigned char type, tmp[17]; isapnp_parse_resource_map() local 728 isapnp_peek(tmp, 2); isapnp_parse_resource_map() 729 card->pnpver = tmp[0]; isapnp_parse_resource_map() 730 card->productver = tmp[1]; isapnp_parse_resource_map() 928 int tmp; isapnp_set_resources() local 933 for (tmp = 0; tmp < ISAPNP_MAX_PORT; tmp++) { isapnp_set_resources() 934 res = pnp_get_resource(dev, IORESOURCE_IO, tmp); isapnp_set_resources() 937 tmp, (unsigned long long) res->start); isapnp_set_resources() 938 isapnp_write_word(ISAPNP_CFG_PORT + (tmp << 1), isapnp_set_resources() 942 for (tmp = 0; tmp < ISAPNP_MAX_IRQ; tmp++) { isapnp_set_resources() 943 res = pnp_get_resource(dev, IORESOURCE_IRQ, tmp); isapnp_set_resources() 948 pnp_dbg(&dev->dev, " set irq %d to %d\n", tmp, irq); isapnp_set_resources() 949 isapnp_write_byte(ISAPNP_CFG_IRQ + (tmp << 1), irq); isapnp_set_resources() 952 for (tmp = 0; tmp < ISAPNP_MAX_DMA; tmp++) { isapnp_set_resources() 953 res = pnp_get_resource(dev, IORESOURCE_DMA, tmp); isapnp_set_resources() 956 tmp, (unsigned long long) res->start); isapnp_set_resources() 957 isapnp_write_byte(ISAPNP_CFG_DMA + tmp, res->start); isapnp_set_resources() 960 for (tmp = 0; tmp < ISAPNP_MAX_MEM; tmp++) { isapnp_set_resources() 961 res = pnp_get_resource(dev, IORESOURCE_MEM, tmp); isapnp_set_resources() 964 tmp, (unsigned long long) res->start); isapnp_set_resources() 965 isapnp_write_word(ISAPNP_CFG_MEM + (tmp << 3), isapnp_set_resources()
/linux-4.4.14/net/6lowpan/
H A D	nhc_udp.c	44 u8 tmp = 0, val = 0; udp_uncompress() local 49 fail = lowpan_fetch_skb(skb, &tmp, sizeof(tmp)); udp_uncompress() 52 switch (tmp & LOWPAN_NHC_UDP_CS_P_11) { udp_uncompress() 80 if (tmp & LOWPAN_NHC_UDP_CS_C) { udp_uncompress() 124 u8 tmp; udp_compress() local 132 tmp = LOWPAN_NHC_UDP_CS_P_11; udp_compress() 133 lowpan_push_hc_data(hc_ptr, &tmp, sizeof(tmp)); udp_compress() 135 tmp = ntohs(uh->dest) - LOWPAN_NHC_UDP_4BIT_PORT + udp_compress() 137 lowpan_push_hc_data(hc_ptr, &tmp, sizeof(tmp)); udp_compress() 142 tmp = LOWPAN_NHC_UDP_CS_P_01; udp_compress() 143 lowpan_push_hc_data(hc_ptr, &tmp, sizeof(tmp)); udp_compress() 147 tmp = ntohs(uh->dest) - LOWPAN_NHC_UDP_8BIT_PORT; udp_compress() 148 lowpan_push_hc_data(hc_ptr, &tmp, sizeof(tmp)); udp_compress() 153 tmp = LOWPAN_NHC_UDP_CS_P_10; udp_compress() 154 lowpan_push_hc_data(hc_ptr, &tmp, sizeof(tmp)); udp_compress() 156 tmp = ntohs(uh->source) - LOWPAN_NHC_UDP_8BIT_PORT; udp_compress() 157 lowpan_push_hc_data(hc_ptr, &tmp, sizeof(tmp)); udp_compress() 163 tmp = LOWPAN_NHC_UDP_CS_P_00; udp_compress() 164 lowpan_push_hc_data(hc_ptr, &tmp, sizeof(tmp)); udp_compress()
/linux-4.4.14/fs/
H A D	filesystems.c	103 struct file_system_type ** tmp; unregister_filesystem() local 106 tmp = &file_systems; unregister_filesystem() 107 while (*tmp) { unregister_filesystem() 108 if (fs == *tmp) { unregister_filesystem() 109 *tmp = fs->next; unregister_filesystem() 115 tmp = &(*tmp)->next; unregister_filesystem() 127 struct file_system_type * tmp; fs_index() local 138 for (tmp=file_systems, index=0 ; tmp ; tmp=tmp->next, index++) { fs_index() 139 if (strcmp(tmp->name, name->name) == 0) { fs_index() 151 struct file_system_type * tmp; fs_name() local 155 for (tmp = file_systems; tmp; tmp = tmp->next, index--) fs_name() 156 if (index <= 0 && try_module_get(tmp->owner)) fs_name() 159 if (!tmp) fs_name() 163 len = strlen(tmp->name) + 1; fs_name() 164 res = copy_to_user(buf, tmp->name, len) ? -EFAULT : 0; fs_name() 165 put_filesystem(tmp); fs_name() 171 struct file_system_type * tmp; fs_maxindex() local 175 for (tmp = file_systems, index = 0 ; tmp ; tmp = tmp->next, index++) fs_maxindex() 208 struct file_system_type * tmp; get_filesystem_list() local 211 tmp = file_systems; get_filesystem_list() 212 while (tmp && len < PAGE_SIZE - 80) { get_filesystem_list() 214 (tmp->fs_flags & FS_REQUIRES_DEV) ? "" : "nodev", get_filesystem_list() 215 tmp->name); get_filesystem_list() 216 tmp = tmp->next; get_filesystem_list() 225 struct file_system_type * tmp; filesystems_proc_show() local 228 tmp = file_systems; filesystems_proc_show() 229 while (tmp) { filesystems_proc_show() 231 (tmp->fs_flags & FS_REQUIRES_DEV) ? "" : "nodev", filesystems_proc_show() 232 tmp->name); filesystems_proc_show() 233 tmp = tmp->next; filesystems_proc_show()
H A D	stat.c	143 struct __old_kernel_stat tmp; cp_old_stat() local 154 memset(&tmp, 0, sizeof(struct __old_kernel_stat)); cp_old_stat() 155 tmp.st_dev = old_encode_dev(stat->dev); cp_old_stat() 156 tmp.st_ino = stat->ino; cp_old_stat() 157 if (sizeof(tmp.st_ino) < sizeof(stat->ino) && tmp.st_ino != stat->ino) cp_old_stat() 159 tmp.st_mode = stat->mode; cp_old_stat() 160 tmp.st_nlink = stat->nlink; cp_old_stat() 161 if (tmp.st_nlink != stat->nlink) cp_old_stat() 163 SET_UID(tmp.st_uid, from_kuid_munged(current_user_ns(), stat->uid)); cp_old_stat() 164 SET_GID(tmp.st_gid, from_kgid_munged(current_user_ns(), stat->gid)); cp_old_stat() 165 tmp.st_rdev = old_encode_dev(stat->rdev); cp_old_stat() 170 tmp.st_size = stat->size; cp_old_stat() 171 tmp.st_atime = stat->atime.tv_sec; cp_old_stat() 172 tmp.st_mtime = stat->mtime.tv_sec; cp_old_stat() 173 tmp.st_ctime = stat->ctime.tv_sec; cp_old_stat() 174 return copy_to_user(statbuf,&tmp,sizeof(tmp)) ? -EFAULT : 0; cp_old_stat() 231 struct stat tmp; cp_new_stat() local 240 INIT_STRUCT_STAT_PADDING(tmp); cp_new_stat() 241 tmp.st_dev = encode_dev(stat->dev); cp_new_stat() 242 tmp.st_ino = stat->ino; cp_new_stat() 243 if (sizeof(tmp.st_ino) < sizeof(stat->ino) && tmp.st_ino != stat->ino) cp_new_stat() 245 tmp.st_mode = stat->mode; cp_new_stat() 246 tmp.st_nlink = stat->nlink; cp_new_stat() 247 if (tmp.st_nlink != stat->nlink) cp_new_stat() 249 SET_UID(tmp.st_uid, from_kuid_munged(current_user_ns(), stat->uid)); cp_new_stat() 250 SET_GID(tmp.st_gid, from_kgid_munged(current_user_ns(), stat->gid)); cp_new_stat() 251 tmp.st_rdev = encode_dev(stat->rdev); cp_new_stat() 252 tmp.st_size = stat->size; cp_new_stat() 253 tmp.st_atime = stat->atime.tv_sec; cp_new_stat() 254 tmp.st_mtime = stat->mtime.tv_sec; cp_new_stat() 255 tmp.st_ctime = stat->ctime.tv_sec; cp_new_stat() 257 tmp.st_atime_nsec = stat->atime.tv_nsec; cp_new_stat() 258 tmp.st_mtime_nsec = stat->mtime.tv_nsec; cp_new_stat() 259 tmp.st_ctime_nsec = stat->ctime.tv_nsec; cp_new_stat() 261 tmp.st_blocks = stat->blocks; cp_new_stat() 262 tmp.st_blksize = stat->blksize; cp_new_stat() 263 return copy_to_user(statbuf,&tmp,sizeof(tmp)) ? -EFAULT : 0; cp_new_stat() 365 struct stat64 tmp; cp_new_stat64() local 367 INIT_STRUCT_STAT64_PADDING(tmp); cp_new_stat64() 370 tmp.st_dev = new_encode_dev(stat->dev); cp_new_stat64() 371 tmp.st_rdev = new_encode_dev(stat->rdev); cp_new_stat64() 373 tmp.st_dev = huge_encode_dev(stat->dev); cp_new_stat64() 374 tmp.st_rdev = huge_encode_dev(stat->rdev); cp_new_stat64() 376 tmp.st_ino = stat->ino; cp_new_stat64() 377 if (sizeof(tmp.st_ino) < sizeof(stat->ino) && tmp.st_ino != stat->ino) cp_new_stat64() 380 tmp.__st_ino = stat->ino; cp_new_stat64() 382 tmp.st_mode = stat->mode; cp_new_stat64() 383 tmp.st_nlink = stat->nlink; cp_new_stat64() 384 tmp.st_uid = from_kuid_munged(current_user_ns(), stat->uid); cp_new_stat64() 385 tmp.st_gid = from_kgid_munged(current_user_ns(), stat->gid); cp_new_stat64() 386 tmp.st_atime = stat->atime.tv_sec; cp_new_stat64() 387 tmp.st_atime_nsec = stat->atime.tv_nsec; cp_new_stat64() 388 tmp.st_mtime = stat->mtime.tv_sec; cp_new_stat64() 389 tmp.st_mtime_nsec = stat->mtime.tv_nsec; cp_new_stat64() 390 tmp.st_ctime = stat->ctime.tv_sec; cp_new_stat64() 391 tmp.st_ctime_nsec = stat->ctime.tv_nsec; cp_new_stat64() 392 tmp.st_size = stat->size; cp_new_stat64() 393 tmp.st_blocks = stat->blocks; cp_new_stat64() 394 tmp.st_blksize = stat->blksize; cp_new_stat64() 395 return copy_to_user(statbuf,&tmp,sizeof(tmp)) ? -EFAULT : 0; cp_new_stat64()
/linux-4.4.14/drivers/gpu/drm/i915/
H A D	intel_audio.c	140 uint32_t tmp = val; audio_config_setup_n_reg() local 144 tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK); audio_config_setup_n_reg() 145 tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) | audio_config_setup_n_reg() 148 return tmp; audio_config_setup_n_reg() 170 uint32_t tmp; intel_eld_uptodate() local 173 tmp = I915_READ(reg_eldv); intel_eld_uptodate() 174 tmp &= bits_eldv; intel_eld_uptodate() 176 if (!tmp) intel_eld_uptodate() 179 tmp = I915_READ(reg_elda); intel_eld_uptodate() 180 tmp &= ~bits_elda; intel_eld_uptodate() 181 I915_WRITE(reg_elda, tmp); intel_eld_uptodate() 193 uint32_t eldv, tmp; g4x_audio_codec_disable() local 197 tmp = I915_READ(G4X_AUD_VID_DID); g4x_audio_codec_disable() 198 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) g4x_audio_codec_disable() 204 tmp = I915_READ(G4X_AUD_CNTL_ST); g4x_audio_codec_disable() 205 tmp &= ~eldv; g4x_audio_codec_disable() 206 I915_WRITE(G4X_AUD_CNTL_ST, tmp); g4x_audio_codec_disable() 216 uint32_t tmp; g4x_audio_codec_enable() local 221 tmp = I915_READ(G4X_AUD_VID_DID); g4x_audio_codec_enable() 222 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) g4x_audio_codec_enable() 233 tmp = I915_READ(G4X_AUD_CNTL_ST); g4x_audio_codec_enable() 234 tmp &= ~(eldv | G4X_ELD_ADDR_MASK); g4x_audio_codec_enable() 235 len = (tmp >> 9) & 0x1f; /* ELD buffer size */ g4x_audio_codec_enable() 236 I915_WRITE(G4X_AUD_CNTL_ST, tmp); g4x_audio_codec_enable() 243 tmp = I915_READ(G4X_AUD_CNTL_ST); g4x_audio_codec_enable() 244 tmp |= eldv; g4x_audio_codec_enable() 245 I915_WRITE(G4X_AUD_CNTL_ST, tmp); g4x_audio_codec_enable() 253 uint32_t tmp; hsw_audio_codec_disable() local 260 tmp = I915_READ(HSW_AUD_CFG(pipe)); hsw_audio_codec_disable() 261 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; hsw_audio_codec_disable() 262 tmp |= AUD_CONFIG_N_PROG_ENABLE; hsw_audio_codec_disable() 263 tmp &= ~AUD_CONFIG_UPPER_N_MASK; hsw_audio_codec_disable() 264 tmp &= ~AUD_CONFIG_LOWER_N_MASK; hsw_audio_codec_disable() 266 tmp |= AUD_CONFIG_N_VALUE_INDEX; hsw_audio_codec_disable() 267 I915_WRITE(HSW_AUD_CFG(pipe), tmp); hsw_audio_codec_disable() local 270 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); hsw_audio_codec_disable() 271 tmp &= ~AUDIO_ELD_VALID(pipe); hsw_audio_codec_disable() 272 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe); hsw_audio_codec_disable() 273 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); hsw_audio_codec_disable() 290 uint32_t tmp; hsw_audio_codec_enable() local 300 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); hsw_audio_codec_enable() 301 tmp |= AUDIO_OUTPUT_ENABLE(pipe); hsw_audio_codec_enable() 302 tmp &= ~AUDIO_ELD_VALID(pipe); hsw_audio_codec_enable() 303 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); hsw_audio_codec_enable() 313 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe)); hsw_audio_codec_enable() 314 tmp &= ~IBX_ELD_ADDRESS_MASK; hsw_audio_codec_enable() 315 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); hsw_audio_codec_enable() local 323 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); hsw_audio_codec_enable() 324 tmp |= AUDIO_ELD_VALID(pipe); hsw_audio_codec_enable() 325 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); hsw_audio_codec_enable() 328 tmp = I915_READ(HSW_AUD_CFG(pipe)); hsw_audio_codec_enable() 329 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; hsw_audio_codec_enable() 330 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; hsw_audio_codec_enable() 332 tmp |= AUD_CONFIG_N_VALUE_INDEX; hsw_audio_codec_enable() 334 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); hsw_audio_codec_enable() 336 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; hsw_audio_codec_enable() 348 tmp = audio_config_setup_n_reg(n, tmp); hsw_audio_codec_enable() 353 I915_WRITE(HSW_AUD_CFG(pipe), tmp); hsw_audio_codec_enable() local 366 uint32_t tmp, eldv; ilk_audio_codec_disable() local 388 tmp = I915_READ(aud_config); ilk_audio_codec_disable() 389 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; ilk_audio_codec_disable() 390 tmp |= AUD_CONFIG_N_PROG_ENABLE; ilk_audio_codec_disable() 391 tmp &= ~AUD_CONFIG_UPPER_N_MASK; ilk_audio_codec_disable() 392 tmp &= ~AUD_CONFIG_LOWER_N_MASK; ilk_audio_codec_disable() 394 tmp |= AUD_CONFIG_N_VALUE_INDEX; ilk_audio_codec_disable() 395 I915_WRITE(aud_config, tmp); ilk_audio_codec_disable() 400 tmp = I915_READ(aud_cntrl_st2); ilk_audio_codec_disable() 401 tmp &= ~eldv; ilk_audio_codec_disable() 402 I915_WRITE(aud_cntrl_st2, tmp); ilk_audio_codec_disable() 417 uint32_t tmp; ilk_audio_codec_enable() local 457 tmp = I915_READ(aud_cntrl_st2); ilk_audio_codec_enable() 458 tmp &= ~eldv; ilk_audio_codec_enable() 459 I915_WRITE(aud_cntrl_st2, tmp); ilk_audio_codec_enable() 462 tmp = I915_READ(aud_cntl_st); ilk_audio_codec_enable() 463 tmp &= ~IBX_ELD_ADDRESS_MASK; ilk_audio_codec_enable() 464 I915_WRITE(aud_cntl_st, tmp); ilk_audio_codec_enable() 472 tmp = I915_READ(aud_cntrl_st2); ilk_audio_codec_enable() 473 tmp |= eldv; ilk_audio_codec_enable() 474 I915_WRITE(aud_cntrl_st2, tmp); ilk_audio_codec_enable() 477 tmp = I915_READ(aud_config); ilk_audio_codec_enable() 478 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; ilk_audio_codec_enable() 479 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; ilk_audio_codec_enable() 480 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; ilk_audio_codec_enable() 482 tmp |= AUD_CONFIG_N_VALUE_INDEX; ilk_audio_codec_enable() 484 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); ilk_audio_codec_enable() 485 I915_WRITE(aud_config, tmp); ilk_audio_codec_enable() 592 u32 tmp; i915_audio_component_codec_wake_override() local 601 tmp = I915_READ(HSW_AUD_CHICKENBIT); i915_audio_component_codec_wake_override() 602 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; i915_audio_component_codec_wake_override() 603 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); i915_audio_component_codec_wake_override() 607 tmp = I915_READ(HSW_AUD_CHICKENBIT); i915_audio_component_codec_wake_override() 608 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; i915_audio_component_codec_wake_override() 609 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); i915_audio_component_codec_wake_override() 642 u32 tmp; i915_audio_component_sync_audio_rate() local 682 tmp = I915_READ(HSW_AUD_CFG(pipe)); 683 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 684 I915_WRITE(HSW_AUD_CFG(pipe), tmp); local 693 tmp = I915_READ(HSW_AUD_CFG(pipe)); 694 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 695 I915_WRITE(HSW_AUD_CFG(pipe), tmp); local 701 tmp = I915_READ(HSW_AUD_CFG(pipe)); 702 tmp = audio_config_setup_n_reg(n, tmp); 703 I915_WRITE(HSW_AUD_CFG(pipe), tmp); local
/linux-4.4.14/drivers/clk/imx/
H A D	clk-pfd.c	61 u64 tmp = parent_rate; clk_pfd_recalc_rate() local 64 tmp *= 18; clk_pfd_recalc_rate() 65 do_div(tmp, frac); clk_pfd_recalc_rate() 67 return tmp; clk_pfd_recalc_rate() 73 u64 tmp = *prate; clk_pfd_round_rate() local 76 tmp = tmp * 18 + rate / 2; clk_pfd_round_rate() 77 do_div(tmp, rate); clk_pfd_round_rate() 78 frac = tmp; clk_pfd_round_rate() 83 tmp = *prate; clk_pfd_round_rate() 84 tmp *= 18; clk_pfd_round_rate() 85 do_div(tmp, frac); clk_pfd_round_rate() 87 return tmp; clk_pfd_round_rate() 94 u64 tmp = parent_rate; clk_pfd_set_rate() local 97 tmp = tmp * 18 + rate / 2; clk_pfd_set_rate() 98 do_div(tmp, rate); clk_pfd_set_rate() 99 frac = tmp; clk_pfd_set_rate()
/linux-4.4.14/drivers/clk/mxs/
H A D	clk-ref.c	57 u64 tmp = parent_rate; clk_ref_recalc_rate() local 60 tmp *= 18; clk_ref_recalc_rate() 61 do_div(tmp, frac); clk_ref_recalc_rate() 63 return tmp; clk_ref_recalc_rate() 70 u64 tmp = parent_rate; clk_ref_round_rate() local 73 tmp = tmp * 18 + rate / 2; clk_ref_round_rate() 74 do_div(tmp, rate); clk_ref_round_rate() 75 frac = tmp; clk_ref_round_rate() 82 tmp = parent_rate; clk_ref_round_rate() 83 tmp *= 18; clk_ref_round_rate() 84 do_div(tmp, frac); clk_ref_round_rate() 86 return tmp; clk_ref_round_rate() 94 u64 tmp = parent_rate; clk_ref_set_rate() local 98 tmp = tmp * 18 + rate / 2; clk_ref_set_rate() 99 do_div(tmp, rate); clk_ref_set_rate() 100 frac = tmp; clk_ref_set_rate()
H A D	clk-frac.c	59 u64 tmp, tmp_rate, result; clk_frac_round_rate() local 64 tmp = rate; clk_frac_round_rate() 65 tmp <<= frac->width; clk_frac_round_rate() 66 do_div(tmp, parent_rate); clk_frac_round_rate() 67 div = tmp; clk_frac_round_rate() 85 u64 tmp; clk_frac_set_rate() local 90 tmp = rate; clk_frac_set_rate() 91 tmp <<= frac->width; clk_frac_set_rate() 92 do_div(tmp, parent_rate); clk_frac_set_rate() 93 div = tmp; clk_frac_set_rate()
/linux-4.4.14/arch/arm/mach-s5pv210/
H A D	pm.c	45 unsigned long tmp; s5pv210_cpu_suspend() local 50 tmp = 0; s5pv210_cpu_suspend() 57 "wfi" : : "r" (tmp)); s5pv210_cpu_suspend() 65 unsigned int tmp; s5pv210_pm_prepare() local 74 tmp = __raw_readl(S5P_SLEEP_CFG); s5pv210_pm_prepare() 75 tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN); s5pv210_pm_prepare() 76 __raw_writel(tmp, S5P_SLEEP_CFG); s5pv210_pm_prepare() 79 tmp = __raw_readl(S5P_PWR_CFG); s5pv210_pm_prepare() 80 tmp &= S5P_CFG_WFI_CLEAN; s5pv210_pm_prepare() 81 tmp |= S5P_CFG_WFI_SLEEP; s5pv210_pm_prepare() 82 __raw_writel(tmp, S5P_PWR_CFG); s5pv210_pm_prepare() 85 tmp = __raw_readl(S5P_OTHERS); s5pv210_pm_prepare() 86 tmp |= S5P_OTHER_SYSC_INTOFF; s5pv210_pm_prepare() 87 __raw_writel(tmp, S5P_OTHERS); s5pv210_pm_prepare() 158 u32 tmp; s5pv210_pm_resume() local 160 tmp = __raw_readl(S5P_OTHERS); s5pv210_pm_resume() 161 tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF |\ s5pv210_pm_resume() 163 __raw_writel(tmp , S5P_OTHERS); s5pv210_pm_resume()
/linux-4.4.14/drivers/devfreq/exynos/
H A D	exynos4_bus.c	294 unsigned int tmp; exynos4210_set_busclk() local 304 tmp = data->dmc_divtable[index]; exynos4210_set_busclk() 306 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0); exynos4210_set_busclk() 309 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0); exynos4210_set_busclk() 310 } while (tmp & 0x11111111); exynos4210_set_busclk() 313 tmp = data->top_divtable[index]; exynos4210_set_busclk() 315 __raw_writel(tmp, EXYNOS4_CLKDIV_TOP); exynos4210_set_busclk() 318 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP); exynos4210_set_busclk() 319 } while (tmp & 0x11111); exynos4210_set_busclk() 322 tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS); exynos4210_set_busclk() 324 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); exynos4210_set_busclk() 326 tmp |= ((exynos4210_clkdiv_lr_bus[index][0] << exynos4210_set_busclk() 331 __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS); exynos4210_set_busclk() 334 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS); exynos4210_set_busclk() 335 } while (tmp & 0x11); exynos4210_set_busclk() 338 tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS); exynos4210_set_busclk() 340 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); exynos4210_set_busclk() 342 tmp |= ((exynos4210_clkdiv_lr_bus[index][0] << exynos4210_set_busclk() 347 __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS); exynos4210_set_busclk() 350 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS); exynos4210_set_busclk() 351 } while (tmp & 0x11); exynos4210_set_busclk() 360 unsigned int tmp; exynos4x12_set_busclk() local 370 tmp = data->dmc_divtable[index]; exynos4x12_set_busclk() 372 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0); exynos4x12_set_busclk() 375 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0); exynos4x12_set_busclk() 376 } while (tmp & 0x11111111); exynos4x12_set_busclk() 379 tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1); exynos4x12_set_busclk() 381 tmp &= ~(EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK | exynos4x12_set_busclk() 385 tmp |= ((exynos4x12_clkdiv_dmc1[index][0] << exynos4x12_set_busclk() 392 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC1); exynos4x12_set_busclk() 395 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC1); exynos4x12_set_busclk() 396 } while (tmp & 0x111111); exynos4x12_set_busclk() 399 tmp = __raw_readl(EXYNOS4_CLKDIV_TOP); exynos4x12_set_busclk() 401 tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK | exynos4x12_set_busclk() 407 tmp |= ((exynos4x12_clkdiv_top[index][0] << exynos4x12_set_busclk() 418 __raw_writel(tmp, EXYNOS4_CLKDIV_TOP); exynos4x12_set_busclk() 421 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP); exynos4x12_set_busclk() 422 } while (tmp & 0x11111); exynos4x12_set_busclk() 425 tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS); exynos4x12_set_busclk() 427 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); exynos4x12_set_busclk() 429 tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] << exynos4x12_set_busclk() 434 __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS); exynos4x12_set_busclk() 437 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS); exynos4x12_set_busclk() 438 } while (tmp & 0x11); exynos4x12_set_busclk() 441 tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS); exynos4x12_set_busclk() 443 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); exynos4x12_set_busclk() 445 tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] << exynos4x12_set_busclk() 450 __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS); exynos4x12_set_busclk() 453 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS); exynos4x12_set_busclk() 454 } while (tmp & 0x11); exynos4x12_set_busclk() 457 tmp = __raw_readl(EXYNOS4_CLKDIV_MFC); exynos4x12_set_busclk() 459 tmp &= ~(EXYNOS4_CLKDIV_MFC_MASK); exynos4x12_set_busclk() 461 tmp |= ((exynos4x12_clkdiv_sclkip[index][0] << exynos4x12_set_busclk() 464 __raw_writel(tmp, EXYNOS4_CLKDIV_MFC); exynos4x12_set_busclk() 467 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_MFC); exynos4x12_set_busclk() 468 } while (tmp & 0x1); exynos4x12_set_busclk() 471 tmp = __raw_readl(EXYNOS4_CLKDIV_CAM1); exynos4x12_set_busclk() 473 tmp &= ~(EXYNOS4_CLKDIV_CAM1_JPEG_MASK); exynos4x12_set_busclk() 475 tmp |= ((exynos4x12_clkdiv_sclkip[index][1] << exynos4x12_set_busclk() 478 __raw_writel(tmp, EXYNOS4_CLKDIV_CAM1); exynos4x12_set_busclk() 481 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1); exynos4x12_set_busclk() 482 } while (tmp & 0x1); exynos4x12_set_busclk() 485 tmp = __raw_readl(EXYNOS4_CLKDIV_CAM); exynos4x12_set_busclk() 487 tmp &= ~(EXYNOS4_CLKDIV_CAM_FIMC0_MASK | EXYNOS4_CLKDIV_CAM_FIMC1_MASK | exynos4x12_set_busclk() 490 tmp |= ((exynos4x12_clkdiv_sclkip[index][2] << exynos4x12_set_busclk() 499 __raw_writel(tmp, EXYNOS4_CLKDIV_CAM); exynos4x12_set_busclk() 502 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1); exynos4x12_set_busclk() 503 } while (tmp & 0x1111); exynos4x12_set_busclk() 525 int err = 0, tmp; exynos4_bus_setvolt() local 541 tmp = exynos4x12_get_intspec(oppi->rate); exynos4_bus_setvolt() 542 if (tmp < 0) { exynos4_bus_setvolt() 543 err = tmp; exynos4_bus_setvolt() 550 exynos4x12_intclk_table[tmp].volt, exynos4_bus_setvolt() 664 u32 tmp; exynos4210_init_tables() local 668 tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0); exynos4210_init_tables() 670 tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK | exynos4210_init_tables() 679 tmp |= ((exynos4210_clkdiv_dmc0[i][0] << exynos4210_init_tables() 696 data->dmc_divtable[i] = tmp; exynos4210_init_tables() 699 tmp = __raw_readl(EXYNOS4_CLKDIV_TOP); exynos4210_init_tables() 701 tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK200_MASK | exynos4210_init_tables() 707 tmp |= ((exynos4210_clkdiv_top[i][0] << exynos4210_init_tables() 718 data->top_divtable[i] = tmp; exynos4210_init_tables() 722 * TODO: init tmp based on busfreq_data exynos4210_init_tables() 725 tmp = 0; /* Max voltages for the reliability of the unknown */ exynos4210_init_tables() 727 pr_debug("ASV Group of Exynos4 is %d\n", tmp); exynos4210_init_tables() 729 switch (tmp) { exynos4210_init_tables() 772 unsigned int tmp; exynos4x12_init_tables() local 776 tmp = __raw_readl(EXYNOS4_DMC_PAUSE_CTRL); exynos4x12_init_tables() 777 tmp |= EXYNOS4_DMC_PAUSE_ENABLE; exynos4x12_init_tables() 778 __raw_writel(tmp, EXYNOS4_DMC_PAUSE_CTRL); exynos4x12_init_tables() 780 tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0); exynos4x12_init_tables() 783 tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK | exynos4x12_init_tables() 790 tmp |= ((exynos4x12_clkdiv_dmc0[i][0] << exynos4x12_init_tables() 803 data->dmc_divtable[i] = tmp; exynos4x12_init_tables() 806 tmp = 0; /* Max voltages for the reliability of the unknown */ exynos4x12_init_tables() 808 if (tmp > 8) exynos4x12_init_tables() 809 tmp = 0; exynos4x12_init_tables() 810 pr_debug("ASV Group of Exynos4x12 is %d\n", tmp); exynos4x12_init_tables() 814 exynos4x12_mif_step_50[tmp][i]; exynos4x12_init_tables() 816 exynos4x12_int_volt[tmp][i]; exynos4x12_init_tables()
/linux-4.4.14/drivers/gpu/drm/
H A D	drm_rect.c	76 int64_t tmp = src->x1 + (int64_t) diff * hscale; drm_rect_clip_scaled() local 77 src->x1 = clamp_t(int64_t, tmp, INT_MIN, INT_MAX); drm_rect_clip_scaled() 81 int64_t tmp = src->y1 + (int64_t) diff * vscale; drm_rect_clip_scaled() local 82 src->y1 = clamp_t(int64_t, tmp, INT_MIN, INT_MAX); drm_rect_clip_scaled() 86 int64_t tmp = src->x2 - (int64_t) diff * hscale; drm_rect_clip_scaled() local 87 src->x2 = clamp_t(int64_t, tmp, INT_MIN, INT_MAX); drm_rect_clip_scaled() 91 int64_t tmp = src->y2 - (int64_t) diff * vscale; drm_rect_clip_scaled() local 92 src->y2 = clamp_t(int64_t, tmp, INT_MIN, INT_MAX); drm_rect_clip_scaled() 317 struct drm_rect tmp; drm_rect_rotate() local 320 tmp = *r; drm_rect_rotate() 323 r->x1 = width - tmp.x2; drm_rect_rotate() 324 r->x2 = width - tmp.x1; drm_rect_rotate() 328 r->y1 = height - tmp.y2; drm_rect_rotate() 329 r->y2 = height - tmp.y1; drm_rect_rotate() 337 tmp = *r; drm_rect_rotate() 338 r->x1 = tmp.y1; drm_rect_rotate() 339 r->x2 = tmp.y2; drm_rect_rotate() 340 r->y1 = width - tmp.x2; drm_rect_rotate() 341 r->y2 = width - tmp.x1; drm_rect_rotate() 344 tmp = *r; drm_rect_rotate() 345 r->x1 = width - tmp.x2; drm_rect_rotate() 346 r->x2 = width - tmp.x1; drm_rect_rotate() 347 r->y1 = height - tmp.y2; drm_rect_rotate() 348 r->y2 = height - tmp.y1; drm_rect_rotate() 351 tmp = *r; drm_rect_rotate() 352 r->x1 = height - tmp.y2; drm_rect_rotate() 353 r->x2 = height - tmp.y1; drm_rect_rotate() 354 r->y1 = tmp.x1; drm_rect_rotate() 355 r->y2 = tmp.x2; drm_rect_rotate() 391 struct drm_rect tmp; drm_rect_rotate_inv() local 397 tmp = *r; drm_rect_rotate_inv() 398 r->x1 = width - tmp.y2; drm_rect_rotate_inv() 399 r->x2 = width - tmp.y1; drm_rect_rotate_inv() 400 r->y1 = tmp.x1; drm_rect_rotate_inv() 401 r->y2 = tmp.x2; drm_rect_rotate_inv() 404 tmp = *r; drm_rect_rotate_inv() 405 r->x1 = width - tmp.x2; drm_rect_rotate_inv() 406 r->x2 = width - tmp.x1; drm_rect_rotate_inv() 407 r->y1 = height - tmp.y2; drm_rect_rotate_inv() 408 r->y2 = height - tmp.y1; drm_rect_rotate_inv() 411 tmp = *r; drm_rect_rotate_inv() 412 r->x1 = tmp.y1; drm_rect_rotate_inv() 413 r->x2 = tmp.y2; drm_rect_rotate_inv() 414 r->y1 = height - tmp.x2; drm_rect_rotate_inv() 415 r->y2 = height - tmp.x1; drm_rect_rotate_inv() 422 tmp = *r; drm_rect_rotate_inv() 425 r->x1 = width - tmp.x2; drm_rect_rotate_inv() 426 r->x2 = width - tmp.x1; drm_rect_rotate_inv() 430 r->y1 = height - tmp.y2; drm_rect_rotate_inv() 431 r->y2 = height - tmp.y1; drm_rect_rotate_inv()
/linux-4.4.14/drivers/media/common/b2c2/
H A D	flexcop-eeprom.c	63 u8 tmp[8]; 66 tmp[0] = mac[0]; 67 tmp[1] = mac[1]; 68 tmp[2] = mac[2]; 69 tmp[3] = mac[5]; 70 tmp[4] = mac[6]; 71 tmp[5] = mac[7]; 73 tmp[0] = mac[0]; 74 tmp[1] = mac[1]; 75 tmp[2] = mac[2]; 76 tmp[3] = mac[3]; 77 tmp[4] = mac[4]; 78 tmp[5] = mac[5]; 81 tmp[6] = 0; 82 tmp[7] = calc_lrc(tmp, 7); 84 if (eeprom_write(adapter, 0x3f8, tmp, 8) == 8)
/linux-4.4.14/drivers/rtc/
H A D	rtc-m41t93.c	51 int tmp; m41t93_set_time() local 66 tmp = spi_w8r8(spi, M41T93_REG_FLAGS); m41t93_set_time() 67 if (tmp < 0) m41t93_set_time() 68 return tmp; m41t93_set_time() 70 if (tmp & M41T93_FLAG_OF) { m41t93_set_time() 72 m41t93_set_reg(spi, M41T93_REG_FLAGS, tmp & ~M41T93_FLAG_OF); m41t93_set_time() 74 tmp = spi_w8r8(spi, M41T93_REG_FLAGS); m41t93_set_time() 75 if (tmp < 0) { m41t93_set_time() 76 return tmp; m41t93_set_time() 77 } else if (tmp & M41T93_FLAG_OF) { m41t93_set_time() 110 int tmp; m41t93_get_time() local 119 tmp = spi_w8r8(spi, M41T93_REG_ALM_HOUR_HT); m41t93_get_time() 120 if (tmp < 0) m41t93_get_time() 121 return tmp; m41t93_get_time() 123 if (tmp & M41T93_FLAG_HT) { m41t93_get_time() 126 tmp & ~M41T93_FLAG_HT); m41t93_get_time() 129 tmp = spi_w8r8(spi, M41T93_REG_FLAGS); m41t93_get_time() 130 if (tmp < 0) m41t93_get_time() 131 return tmp; m41t93_get_time() 133 if (tmp & M41T93_FLAG_OF) { m41t93_get_time() 138 if (tmp & M41T93_FLAG_BL) m41t93_get_time() 142 tmp = spi_write_then_read(spi, &start_addr, 1, buf, sizeof(buf)); m41t93_get_time() 143 if (tmp < 0) m41t93_get_time() 144 return tmp; m41t93_get_time()
H A D	rtc-fm3130.c	98 int tmp; fm3130_get_time() local 110 tmp = i2c_transfer(to_i2c_adapter(fm3130->client->dev.parent), fm3130_get_time() 112 if (tmp != 2) { fm3130_get_time() 113 dev_err(dev, "%s error %d\n", "read", tmp); fm3130_get_time() 123 tmp = fm3130->regs[FM3130_RTC_HOURS] & 0x3f; fm3130_get_time() 124 t->tm_hour = bcd2bin(tmp); fm3130_get_time() 127 tmp = fm3130->regs[FM3130_RTC_MONTHS] & 0x1f; fm3130_get_time() 128 t->tm_mon = bcd2bin(tmp) - 1; fm3130_get_time() 147 int tmp, i; fm3130_set_time() local 165 tmp = t->tm_year - 100; fm3130_set_time() 166 buf[FM3130_RTC_YEARS] = bin2bcd(tmp); fm3130_set_time() 190 int tmp; fm3130_read_alarm() local 204 tmp = i2c_transfer(to_i2c_adapter(fm3130->client->dev.parent), fm3130_read_alarm() 206 if (tmp != 2) { fm3130_read_alarm() 207 dev_err(dev, "%s error %d\n", "read", tmp); fm3130_read_alarm() 354 int tmp; fm3130_probe() local 396 tmp = i2c_transfer(adapter, fm3130->msg, 4); fm3130_probe() 397 if (tmp != 4) { fm3130_probe() 398 dev_dbg(&client->dev, "read error %d\n", tmp); fm3130_probe() 451 tmp = bcd2bin(fm3130->regs[FM3130_RTC_SECONDS] & 0x7f); fm3130_probe() 452 if (tmp > 59) fm3130_probe() 455 tmp = bcd2bin(fm3130->regs[FM3130_RTC_MINUTES] & 0x7f); fm3130_probe() 456 if (tmp > 59) fm3130_probe() 459 tmp = bcd2bin(fm3130->regs[FM3130_RTC_HOURS] & 0x3f); fm3130_probe() 460 if (tmp > 23) fm3130_probe() 463 tmp = bcd2bin(fm3130->regs[FM3130_RTC_DATE] & 0x3f); fm3130_probe() 464 if (tmp == 0 || tmp > 31) fm3130_probe() 467 tmp = bcd2bin(fm3130->regs[FM3130_RTC_MONTHS] & 0x1f); fm3130_probe() 468 if (tmp == 0 || tmp > 12) fm3130_probe() 476 tmp = bcd2bin(fm3130->regs[FM3130_RTC_SECONDS] & 0x7f); fm3130_probe() 477 if (tmp > 59) fm3130_probe() 480 tmp = bcd2bin(fm3130->regs[FM3130_RTC_MINUTES] & 0x7f); fm3130_probe() 481 if (tmp > 59) fm3130_probe() 484 tmp = bcd2bin(fm3130->regs[FM3130_RTC_HOURS] & 0x3f); fm3130_probe() 485 if (tmp > 23) fm3130_probe() 488 tmp = bcd2bin(fm3130->regs[FM3130_RTC_DAY] & 0x7); fm3130_probe() 489 if (tmp == 0 || tmp > 7) fm3130_probe() 492 tmp = bcd2bin(fm3130->regs[FM3130_RTC_DATE] & 0x3f); fm3130_probe() 493 if (tmp == 0 || tmp > 31) fm3130_probe() 496 tmp = bcd2bin(fm3130->regs[FM3130_RTC_MONTHS] & 0x1f); fm3130_probe() 497 if (tmp == 0 || tmp > 12) fm3130_probe()
H A D	rtc-sh.c	107 unsigned int tmp, pending; __sh_rtc_interrupt() local 109 tmp = readb(rtc->regbase + RCR1); __sh_rtc_interrupt() 110 pending = tmp & RCR1_CF; __sh_rtc_interrupt() 111 tmp &= ~RCR1_CF; __sh_rtc_interrupt() 112 writeb(tmp, rtc->regbase + RCR1); __sh_rtc_interrupt() 123 unsigned int tmp, pending; __sh_rtc_alarm() local 125 tmp = readb(rtc->regbase + RCR1); __sh_rtc_alarm() 126 pending = tmp & RCR1_AF; __sh_rtc_alarm() 127 tmp &= ~(RCR1_AF | RCR1_AIE); __sh_rtc_alarm() 128 writeb(tmp, rtc->regbase + RCR1); __sh_rtc_alarm() 140 unsigned int tmp, pending; __sh_rtc_periodic() local 142 tmp = readb(rtc->regbase + RCR2); __sh_rtc_periodic() 143 pending = tmp & RCR2_PEF; __sh_rtc_periodic() 144 tmp &= ~RCR2_PEF; __sh_rtc_periodic() 145 writeb(tmp, rtc->regbase + RCR2); __sh_rtc_periodic() 222 unsigned int tmp; sh_rtc_irq_set_state() local 226 tmp = readb(rtc->regbase + RCR2); sh_rtc_irq_set_state() 230 tmp &= ~RCR2_PEF; /* Clear PES bit */ sh_rtc_irq_set_state() 231 tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */ sh_rtc_irq_set_state() 234 tmp &= ~(RCR2_PESMASK | RCR2_PEF); sh_rtc_irq_set_state() 237 writeb(tmp, rtc->regbase + RCR2); sh_rtc_irq_set_state() 247 int tmp, ret = 0; sh_rtc_irq_set_freq() local 250 tmp = rtc->periodic_freq & PF_MASK; sh_rtc_irq_set_freq() 288 rtc->periodic_freq |= tmp; sh_rtc_irq_set_freq() 297 unsigned int tmp; sh_rtc_setaie() local 301 tmp = readb(rtc->regbase + RCR1); sh_rtc_setaie() 304 tmp |= RCR1_AIE; sh_rtc_setaie() 306 tmp &= ~RCR1_AIE; sh_rtc_setaie() 308 writeb(tmp, rtc->regbase + RCR1); sh_rtc_setaie() 316 unsigned int tmp; sh_rtc_proc() local 318 tmp = readb(rtc->regbase + RCR1); sh_rtc_proc() 319 seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no"); sh_rtc_proc() 321 tmp = readb(rtc->regbase + RCR2); sh_rtc_proc() 323 (tmp & RCR2_PESMASK) ? "yes" : "no"); sh_rtc_proc() 331 unsigned int tmp; sh_rtc_setcie() local 335 tmp = readb(rtc->regbase + RCR1); sh_rtc_setcie() 338 tmp &= ~RCR1_CIE; sh_rtc_setcie() 340 tmp |= RCR1_CIE; sh_rtc_setcie() 342 writeb(tmp, rtc->regbase + RCR1); sh_rtc_setcie() 360 unsigned int tmp; sh_rtc_read_time() local 364 tmp = readb(rtc->regbase + RCR1); sh_rtc_read_time() 365 tmp &= ~RCR1_CF; /* Clear CF-bit */ sh_rtc_read_time() 366 tmp |= RCR1_CIE; sh_rtc_read_time() 367 writeb(tmp, rtc->regbase + RCR1); sh_rtc_read_time() 417 unsigned int tmp; sh_rtc_set_time() local 423 tmp = readb(rtc->regbase + RCR2); sh_rtc_set_time() 424 tmp |= RCR2_RESET; sh_rtc_set_time() 425 tmp &= ~RCR2_START; sh_rtc_set_time() 426 writeb(tmp, rtc->regbase + RCR2); sh_rtc_set_time() 445 tmp = readb(rtc->regbase + RCR2); sh_rtc_set_time() 446 tmp &= ~RCR2_RESET; sh_rtc_set_time() 447 tmp |= RCR2_RTCEN | RCR2_START; sh_rtc_set_time() 448 writeb(tmp, rtc->regbase + RCR2); sh_rtc_set_time()
H A D	rtc-v3020.c	172 unsigned char tmp; v3020_set_reg() local 174 tmp = address; v3020_set_reg() 176 chip->ops->write_bit(chip, (tmp & 1)); v3020_set_reg() 177 tmp >>= 1; v3020_set_reg() 215 int tmp; v3020_read_time() local 221 tmp = v3020_get_reg(chip, V3020_SECONDS); v3020_read_time() 222 dt->tm_sec = bcd2bin(tmp); v3020_read_time() 223 tmp = v3020_get_reg(chip, V3020_MINUTES); v3020_read_time() 224 dt->tm_min = bcd2bin(tmp); v3020_read_time() 225 tmp = v3020_get_reg(chip, V3020_HOURS); v3020_read_time() 226 dt->tm_hour = bcd2bin(tmp); v3020_read_time() 227 tmp = v3020_get_reg(chip, V3020_MONTH_DAY); v3020_read_time() 228 dt->tm_mday = bcd2bin(tmp); v3020_read_time() 229 tmp = v3020_get_reg(chip, V3020_MONTH); v3020_read_time() 230 dt->tm_mon = bcd2bin(tmp) - 1; v3020_read_time() 231 tmp = v3020_get_reg(chip, V3020_WEEK_DAY); v3020_read_time() 232 dt->tm_wday = bcd2bin(tmp); v3020_read_time() 233 tmp = v3020_get_reg(chip, V3020_YEAR); v3020_read_time() 234 dt->tm_year = bcd2bin(tmp)+100; v3020_read_time()
/linux-4.4.14/drivers/spi/
H A D	spi-bcm53xx.c	44 u32 tmp; bcm53xxspi_wait() local 49 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2); bcm53xxspi_wait() 50 if (!(tmp & B53SPI_MSPI_SPCR2_SPE)) bcm53xxspi_wait() 55 if (tmp & B53SPI_MSPI_SPCR2_SPE) bcm53xxspi_wait() 61 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_MSPI_STATUS); bcm53xxspi_wait() 62 if (tmp & B53SPI_MSPI_MSPI_STATUS_SPIF) { bcm53xxspi_wait() 82 u32 tmp; bcm53xxspi_buf_write() local 92 tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL | bcm53xxspi_buf_write() 95 tmp &= ~B53SPI_CDRAM_CONT; bcm53xxspi_buf_write() 96 tmp &= ~0x1; bcm53xxspi_buf_write() 98 bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp); bcm53xxspi_buf_write() 109 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2); bcm53xxspi_buf_write() 110 tmp |= B53SPI_MSPI_SPCR2_SPE; bcm53xxspi_buf_write() 112 tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD; bcm53xxspi_buf_write() 113 bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp); bcm53xxspi_buf_write() 127 u32 tmp; bcm53xxspi_buf_read() local 131 tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL | bcm53xxspi_buf_read() 134 tmp &= ~B53SPI_CDRAM_CONT; bcm53xxspi_buf_read() 135 tmp &= ~0x1; bcm53xxspi_buf_read() 137 bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp); bcm53xxspi_buf_read() 149 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2); bcm53xxspi_buf_read() 150 tmp |= B53SPI_MSPI_SPCR2_SPE; bcm53xxspi_buf_read() 152 tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD; bcm53xxspi_buf_read() 153 bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp); bcm53xxspi_buf_read()
/linux-4.4.14/kernel/
H A D	delayacct.c	88 s64 tmp; __delayacct_add_tsk() local 91 tmp = (s64)d->cpu_run_real_total; __delayacct_add_tsk() 92 tmp += cputime_to_nsecs(utime + stime); __delayacct_add_tsk() 93 d->cpu_run_real_total = (tmp < (s64)d->cpu_run_real_total) ? 0 : tmp; __delayacct_add_tsk() 96 tmp = (s64)d->cpu_scaled_run_real_total; __delayacct_add_tsk() 97 tmp += cputime_to_nsecs(utimescaled + stimescaled); __delayacct_add_tsk() 99 (tmp < (s64)d->cpu_scaled_run_real_total) ? 0 : tmp; __delayacct_add_tsk() 111 tmp = (s64)d->cpu_delay_total + t2; __delayacct_add_tsk() 112 d->cpu_delay_total = (tmp < (s64)d->cpu_delay_total) ? 0 : tmp; __delayacct_add_tsk() 114 tmp = (s64)d->cpu_run_virtual_total + t3; __delayacct_add_tsk() 116 (tmp < (s64)d->cpu_run_virtual_total) ? 0 : tmp; __delayacct_add_tsk() 121 tmp = d->blkio_delay_total + tsk->delays->blkio_delay; __delayacct_add_tsk() 122 d->blkio_delay_total = (tmp < d->blkio_delay_total) ? 0 : tmp; __delayacct_add_tsk() 123 tmp = d->swapin_delay_total + tsk->delays->swapin_delay; __delayacct_add_tsk() 124 d->swapin_delay_total = (tmp < d->swapin_delay_total) ? 0 : tmp; __delayacct_add_tsk() 125 tmp = d->freepages_delay_total + tsk->delays->freepages_delay; __delayacct_add_tsk() 126 d->freepages_delay_total = (tmp < d->freepages_delay_total) ? 0 : tmp; __delayacct_add_tsk()
/linux-4.4.14/arch/h8300/include/asm/
H A D	cmpxchg.h	16 unsigned long tmp, flags; __xchg() local 25 : "=&r" (tmp) : "r" (x), "m" (*__xg(ptr))); __xchg() 31 : "=&r" (tmp) : "r" (x), "m" (*__xg(ptr))); __xchg() 37 : "=&r" (tmp) : "r" (x), "m" (*__xg(ptr))); __xchg() 40 tmp = 0; __xchg() 43 return tmp; __xchg()
/linux-4.4.14/arch/arm64/include/asm/
H A D	assembler.h	63 .macro disable_step_tsk, flgs, tmp 65 mrs \tmp, mdscr_el1 variable 66 bic \tmp, \tmp, #1 variable 67 msr mdscr_el1, \tmp 72 .macro enable_step_tsk, flgs, tmp 75 mrs \tmp, mdscr_el1 variable 76 orr \tmp, \tmp, #1 variable 77 msr mdscr_el1, \tmp 155 * @tmp: optional scratch register to be used if <dst> == sp, which 158 .macro adr_l, dst, sym, tmp= variable 159 .ifb \tmp 163 adrp \tmp, \sym 164 add \dst, \tmp, :lo12:\sym variable 171 * @tmp: optional 64-bit scratch register to be used if <dst> is a 175 .macro ldr_l, dst, sym, tmp= variable 176 .ifb \tmp 180 adrp \tmp, \sym 181 ldr \dst, [\tmp, :lo12:\sym] 188 * @tmp: mandatory 64-bit scratch register to calculate the address 191 .macro str_l, src, sym, tmp 192 adrp \tmp, \sym variable 193 str \src, [\tmp, :lo12:\sym]
H A D	futex.h	29 #define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg) \ 51 : "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp) \ 62 int oldval = 0, ret, tmp; futex_atomic_op_inuser() local 75 ret, oldval, uaddr, tmp, oparg); futex_atomic_op_inuser() 79 ret, oldval, uaddr, tmp, oparg); futex_atomic_op_inuser() 83 ret, oldval, uaddr, tmp, oparg); futex_atomic_op_inuser() 87 ret, oldval, uaddr, tmp, ~oparg); futex_atomic_op_inuser() 91 ret, oldval, uaddr, tmp, oparg); futex_atomic_op_inuser() 118 u32 val, tmp; futex_atomic_cmpxchg_inatomic() local 140 : "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp) futex_atomic_cmpxchg_inatomic()
H A D	atomic_ll_sc.h	44 unsigned long tmp; \ 53 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \ 62 unsigned long tmp; \ 72 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \ 108 unsigned long tmp; \ 116 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \ 126 unsigned long tmp; \ 135 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \ 170 unsigned long tmp; atomic64_dec_if_positive() local 181 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) atomic64_dec_if_positive() 195 unsigned long tmp, oldval; \ 200 " eor %" #w "[tmp], %" #w "[oldval], %" #w "[old]\n" \ 201 " cbnz %" #w "[tmp], 2f\n" \ 202 " st" #rel "xr" #sz "\t%w[tmp], %" #w "[new], %[v]\n" \ 203 " cbnz %w[tmp], 1b\n" \ 207 : [tmp] "=&r" (tmp), [oldval] "=&r" (oldval), \ 243 unsigned long tmp, ret; \ 256 : "=&r" (tmp), "=&r" (ret), "+Q" (*(unsigned long *)ptr) \
/linux-4.4.14/drivers/net/wireless/ti/wl18xx/
H A D	io.c	29 u32 tmp; wl18xx_top_reg_write() local 36 ret = wlcore_read32(wl, addr, &tmp); wl18xx_top_reg_write() 40 tmp = (tmp & 0xffff0000) | val; wl18xx_top_reg_write() 41 ret = wlcore_write32(wl, addr, tmp); wl18xx_top_reg_write() 43 ret = wlcore_read32(wl, addr - 2, &tmp); wl18xx_top_reg_write() 47 tmp = (tmp & 0xffff) | (val << 16); wl18xx_top_reg_write() 48 ret = wlcore_write32(wl, addr - 2, tmp); wl18xx_top_reg_write()
/linux-4.4.14/arch/mips/include/asm/octeon/
H A D	cvmx-spinlock.h	105 unsigned int tmp; cvmx_spinlock_trylock() local 108 "1: ll %[tmp], %[val] \n" cvmx_spinlock_trylock() 110 " bnez %[tmp], 2f \n" cvmx_spinlock_trylock() 111 " li %[tmp], 1 \n" cvmx_spinlock_trylock() 112 " sc %[tmp], %[val] \n" cvmx_spinlock_trylock() 113 " beqz %[tmp], 1b \n" cvmx_spinlock_trylock() 114 " li %[tmp], 0 \n" cvmx_spinlock_trylock() 117 [val] "+m"(lock->value), [tmp] "=&r"(tmp) cvmx_spinlock_trylock() 120 return tmp != 0; /* normalize to 0 or 1 */ cvmx_spinlock_trylock() 130 unsigned int tmp; cvmx_spinlock_lock() local 133 "1: ll %[tmp], %[val] \n" cvmx_spinlock_lock() 134 " bnez %[tmp], 1b \n" cvmx_spinlock_lock() 135 " li %[tmp], 1 \n" cvmx_spinlock_lock() 136 " sc %[tmp], %[val] \n" cvmx_spinlock_lock() 137 " beqz %[tmp], 1b \n" cvmx_spinlock_lock() 140 [val] "+m"(lock->value), [tmp] "=&r"(tmp) cvmx_spinlock_lock() 163 unsigned int tmp; cvmx_spinlock_bit_lock() local 168 "1: ll %[tmp], %[val] \n" cvmx_spinlock_bit_lock() 169 " bbit1 %[tmp], 31, 1b \n" cvmx_spinlock_bit_lock() 171 " ins %[tmp], $at, 31, 1 \n" cvmx_spinlock_bit_lock() 172 " sc %[tmp], %[val] \n" cvmx_spinlock_bit_lock() 173 " beqz %[tmp], 1b \n" cvmx_spinlock_bit_lock() 177 [val] "+m"(*word), [tmp] "=&r"(tmp), [sav] "=&r"(sav) cvmx_spinlock_bit_lock() 195 unsigned int tmp; cvmx_spinlock_bit_trylock() local 199 "1: ll %[tmp], %[val] \n" cvmx_spinlock_bit_trylock() 201 " bbit1 %[tmp], 31, 2f \n" cvmx_spinlock_bit_trylock() 203 " ins %[tmp], $at, 31, 1 \n" cvmx_spinlock_bit_trylock() 204 " sc %[tmp], %[val] \n" cvmx_spinlock_bit_trylock() 205 " beqz %[tmp], 1b \n" cvmx_spinlock_bit_trylock() 206 " li %[tmp], 0 \n" cvmx_spinlock_bit_trylock() 210 [val] "+m"(*word), [tmp] "=&r"(tmp) cvmx_spinlock_bit_trylock() 213 return tmp != 0; /* normalize to 0 or 1 */ cvmx_spinlock_bit_trylock()
/linux-4.4.14/arch/sh/boards/mach-sdk7786/
H A D	irq.c	32 unsigned int tmp; sdk7786_init_irq() local 42 tmp = fpga_read_reg(INTAMR); sdk7786_init_irq() 43 tmp &= ~(1 << ETH_IRQ_BIT); sdk7786_init_irq() 44 fpga_write_reg(tmp, INTAMR); sdk7786_init_irq()
H A D	nmi.c	53 unsigned int source, mask, tmp; sdk7786_nmi_init() local 76 tmp = fpga_read_reg(NMISR); sdk7786_nmi_init() 77 tmp &= ~NMISR_MASK; sdk7786_nmi_init() 78 tmp |= source; sdk7786_nmi_init() 79 fpga_write_reg(tmp, NMISR); sdk7786_nmi_init()
/linux-4.4.14/lib/
H A D	kstrtox.c	148 unsigned long long tmp; kstrtoll() local 152 rv = _kstrtoull(s + 1, base, &tmp); kstrtoll() 155 if ((long long)-tmp > 0) kstrtoll() 157 *res = -tmp; kstrtoll() 159 rv = kstrtoull(s, base, &tmp); kstrtoll() 162 if ((long long)tmp < 0) kstrtoll() 164 *res = tmp; kstrtoll() 173 unsigned long long tmp; _kstrtoul() local 176 rv = kstrtoull(s, base, &tmp); _kstrtoul() 179 if (tmp != (unsigned long long)(unsigned long)tmp) _kstrtoul() 181 *res = tmp; _kstrtoul() 189 long long tmp; _kstrtol() local 192 rv = kstrtoll(s, base, &tmp); _kstrtol() 195 if (tmp != (long long)(long)tmp) _kstrtol() 197 *res = tmp; _kstrtol() 220 unsigned long long tmp; kstrtouint() local 223 rv = kstrtoull(s, base, &tmp); kstrtouint() 226 if (tmp != (unsigned long long)(unsigned int)tmp) kstrtouint() 228 *res = tmp; kstrtouint() 251 long long tmp; kstrtoint() local 254 rv = kstrtoll(s, base, &tmp); kstrtoint() 257 if (tmp != (long long)(int)tmp) kstrtoint() 259 *res = tmp; kstrtoint() 266 unsigned long long tmp; kstrtou16() local 269 rv = kstrtoull(s, base, &tmp); kstrtou16() 272 if (tmp != (unsigned long long)(u16)tmp) kstrtou16() 274 *res = tmp; kstrtou16() 281 long long tmp; kstrtos16() local 284 rv = kstrtoll(s, base, &tmp); kstrtos16() 287 if (tmp != (long long)(s16)tmp) kstrtos16() 289 *res = tmp; kstrtos16() 296 unsigned long long tmp; kstrtou8() local 299 rv = kstrtoull(s, base, &tmp); kstrtou8() 302 if (tmp != (unsigned long long)(u8)tmp) kstrtou8() 304 *res = tmp; kstrtou8() 311 long long tmp; kstrtos8() local 314 rv = kstrtoll(s, base, &tmp); kstrtos8() 317 if (tmp != (long long)(s8)tmp) kstrtos8() 319 *res = tmp; kstrtos8()
H A D	find_bit.c	34 unsigned long tmp; _find_next_bit() local 39 tmp = addr[start / BITS_PER_LONG] ^ invert; _find_next_bit() 42 tmp &= BITMAP_FIRST_WORD_MASK(start); _find_next_bit() 45 while (!tmp) { _find_next_bit() 50 tmp = addr[start / BITS_PER_LONG] ^ invert; _find_next_bit() 53 return min(start + __ffs(tmp), nbits); _find_next_bit() 152 unsigned long tmp; _find_next_bit_le() local 157 tmp = addr[start / BITS_PER_LONG] ^ invert; _find_next_bit_le() 160 tmp &= ext2_swab(BITMAP_FIRST_WORD_MASK(start)); _find_next_bit_le() 163 while (!tmp) { _find_next_bit_le() 168 tmp = addr[start / BITS_PER_LONG] ^ invert; _find_next_bit_le() 171 return min(start + __ffs(ext2_swab(tmp)), nbits); _find_next_bit_le()
/linux-4.4.14/drivers/ata/
H A D	ahci_ceva.c	108 u32 tmp; ahci_ceva_setup() local 116 tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL; ahci_ceva_setup() 117 writel(tmp, mmio + AHCI_VEND_PAXIC); ahci_ceva_setup() 120 tmp = readl(mmio + HOST_CTL); ahci_ceva_setup() 121 tmp |= HOST_AHCI_EN; ahci_ceva_setup() 122 writel(tmp, mmio + HOST_CTL); ahci_ceva_setup() 126 tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i); ahci_ceva_setup() 127 writel(tmp, mmio + AHCI_VEND_PCFG); ahci_ceva_setup() 130 tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN; ahci_ceva_setup() 131 writel(tmp, mmio + AHCI_VEND_PPCFG); ahci_ceva_setup() 134 tmp = PP2C_CIBGMN | PP2C_CIBGMX | PP2C_CIBGN | PP2C_CINMP; ahci_ceva_setup() 135 writel(tmp, mmio + AHCI_VEND_PP2C); ahci_ceva_setup() 138 tmp = PP3C_CWBGMN | PP3C_CWBGMX | PP3C_CWBGN | PP3C_CWNMP; ahci_ceva_setup() 139 writel(tmp, mmio + AHCI_VEND_PP3C); ahci_ceva_setup() 142 tmp = PP4C_BMX | PP4C_BNM | PP4C_SFD | PP4C_PTST; ahci_ceva_setup() 143 writel(tmp, mmio + AHCI_VEND_PP4C); ahci_ceva_setup() 146 tmp = PP5C_RIT | PP5C_RCT; ahci_ceva_setup() 147 writel(tmp, mmio + AHCI_VEND_PP5C); ahci_ceva_setup() 150 tmp = PTC_RX_WM_VAL | PTC_RSVD; ahci_ceva_setup() 151 writel(tmp, mmio + AHCI_VEND_PTC); ahci_ceva_setup() 154 tmp = PORT_SCTL_SPD_GEN2 | PORT_SCTL_IPM; ahci_ceva_setup() 156 tmp = PORT_SCTL_SPD_GEN1 | PORT_SCTL_IPM; ahci_ceva_setup() 157 writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); ahci_ceva_setup()
H A D	sata_promise.c	366 unsigned int tmp; pdc_sata_port_start() local 368 tmp = readl(sata_mmio + PDC_PHYMODE4); pdc_sata_port_start() 369 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ pdc_sata_port_start() 370 writel(tmp, sata_mmio + PDC_PHYMODE4); pdc_sata_port_start() 379 u32 tmp; pdc_fpdma_clear_interrupt_flag() local 381 tmp = readl(sata_mmio + PDC_FPDMA_CTLSTAT); pdc_fpdma_clear_interrupt_flag() 382 tmp |= PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG; pdc_fpdma_clear_interrupt_flag() 383 tmp |= PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG; pdc_fpdma_clear_interrupt_flag() 387 writeb(tmp >> 8, sata_mmio + PDC_FPDMA_CTLSTAT + 1); pdc_fpdma_clear_interrupt_flag() 394 u8 tmp; pdc_fpdma_reset() local 396 tmp = (u8)readl(sata_mmio + PDC_FPDMA_CTLSTAT); pdc_fpdma_reset() 397 tmp &= 0x7F; pdc_fpdma_reset() 398 tmp |= PDC_FPDMA_CTLSTAT_RESET; pdc_fpdma_reset() 399 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT); pdc_fpdma_reset() 402 tmp &= ~PDC_FPDMA_CTLSTAT_RESET; pdc_fpdma_reset() 403 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT); pdc_fpdma_reset() 413 u32 tmp; pdc_not_at_command_packet_phase() local 418 tmp = readl(sata_mmio + PDC_INTERNAL_DEBUG_2); pdc_not_at_command_packet_phase() 419 if ((tmp & 0xF) != 1) pdc_not_at_command_packet_phase() 437 u32 tmp; pdc_reset_port() local 442 tmp = readl(ata_ctlstat_mmio); pdc_reset_port() 443 tmp |= PDC_RESET; pdc_reset_port() 444 writel(tmp, ata_ctlstat_mmio); pdc_reset_port() 447 tmp = readl(ata_ctlstat_mmio); pdc_reset_port() 448 if (tmp & PDC_RESET) pdc_reset_port() 453 tmp |= PDC_RESET; pdc_reset_port() 454 writel(tmp, ata_ctlstat_mmio); pdc_reset_port() 457 tmp &= ~PDC_RESET; pdc_reset_port() 458 writel(tmp, ata_ctlstat_mmio); pdc_reset_port() 469 u8 tmp; pdc_pata_cable_detect() local 472 tmp = readb(ata_mmio + PDC_CTLSTAT + 3); pdc_pata_cable_detect() 473 if (tmp & 0x01) pdc_pata_cable_detect() 719 u32 tmp; pdc_freeze() local 721 tmp = readl(ata_mmio + PDC_CTLSTAT); pdc_freeze() 722 tmp |= PDC_IRQ_DISABLE; pdc_freeze() 723 tmp &= ~PDC_DMA_ENABLE; pdc_freeze() 724 writel(tmp, ata_mmio + PDC_CTLSTAT); pdc_freeze() 754 u32 tmp; pdc_thaw() local 760 tmp = readl(ata_mmio + PDC_CTLSTAT); pdc_thaw() 761 tmp &= ~PDC_IRQ_DISABLE; pdc_thaw() 762 writel(tmp, ata_mmio + PDC_CTLSTAT); pdc_thaw() 808 u8 tmp; pdc_hard_reset_port() local 812 tmp = readb(pcictl_b1_mmio); pdc_hard_reset_port() 813 tmp &= ~(0x10 << ata_no); pdc_hard_reset_port() 814 writeb(tmp, pcictl_b1_mmio); pdc_hard_reset_port() 817 tmp |= (0x10 << ata_no); pdc_hard_reset_port() 818 writeb(tmp, pcictl_b1_mmio); pdc_hard_reset_port() 938 unsigned int i, tmp; pdc_interrupt() local 990 tmp = hotplug_status & (0x11 << ata_no); pdc_interrupt() 991 if (tmp) { pdc_interrupt() 995 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp); pdc_interrupt() 1002 tmp = mask & (1 << (i + 1)); pdc_interrupt() 1003 if (tmp) { pdc_interrupt() 1133 u32 tmp; pdc_host_init() local 1147 tmp = readl(host_mmio + PDC_FLASH_CTL); pdc_host_init() 1148 tmp |= 0x02000; /* bit 13 (enable bmr burst) */ pdc_host_init() 1150 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ pdc_host_init() 1151 writel(tmp, host_mmio + PDC_FLASH_CTL); pdc_host_init() 1154 tmp = readl(host_mmio + hotplug_offset); pdc_host_init() 1155 writel(tmp | 0xff, host_mmio + hotplug_offset); pdc_host_init() 1157 tmp = readl(host_mmio + hotplug_offset); pdc_host_init() 1159 writel(tmp & ~0xff0000, host_mmio + hotplug_offset); pdc_host_init() 1161 writel(tmp | 0xff0000, host_mmio + hotplug_offset); pdc_host_init() 1168 tmp = readl(host_mmio + PDC_TBG_MODE); pdc_host_init() 1169 tmp &= ~0x30000; /* clear bit 17, 16*/ pdc_host_init() 1170 tmp |= 0x10000; /* set bit 17:16 = 0:1 */ pdc_host_init() 1171 writel(tmp, host_mmio + PDC_TBG_MODE); pdc_host_init() 1177 tmp = readl(host_mmio + PDC_SLEW_CTL); pdc_host_init() 1178 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ pdc_host_init() 1179 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ pdc_host_init() 1180 writel(tmp, host_mmio + PDC_SLEW_CTL); pdc_host_init() 1216 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1); pdc_ata_init_one() local 1217 if (!(tmp & 0x80)) pdc_ata_init_one()
/linux-4.4.14/sound/pci/ice1712/
H A D	ak4xxx.c	58 unsigned int tmp; snd_ice1712_akm4xxx_write() local 67 tmp = snd_ice1712_gpio_read(ice); snd_ice1712_akm4xxx_write() 68 tmp |= priv->add_flags; snd_ice1712_akm4xxx_write() 69 tmp &= ~priv->mask_flags; snd_ice1712_akm4xxx_write() 72 tmp |= priv->cs_mask; /* start without chip select */ snd_ice1712_akm4xxx_write() 74 tmp &= ~priv->cs_mask; /* chip select low */ snd_ice1712_akm4xxx_write() 75 snd_ice1712_gpio_write(ice, tmp); snd_ice1712_akm4xxx_write() 80 tmp &= ~priv->cs_mask; snd_ice1712_akm4xxx_write() 81 tmp |= priv->cs_addr; snd_ice1712_akm4xxx_write() 82 snd_ice1712_gpio_write(ice, tmp); snd_ice1712_akm4xxx_write() 91 tmp &= ~priv->clk_mask; snd_ice1712_akm4xxx_write() 92 snd_ice1712_gpio_write(ice, tmp); snd_ice1712_akm4xxx_write() 96 tmp |= priv->data_mask; snd_ice1712_akm4xxx_write() 98 tmp &= ~priv->data_mask; snd_ice1712_akm4xxx_write() 99 snd_ice1712_gpio_write(ice, tmp); snd_ice1712_akm4xxx_write() 102 tmp |= priv->clk_mask; snd_ice1712_akm4xxx_write() 103 snd_ice1712_gpio_write(ice, tmp); snd_ice1712_akm4xxx_write() 110 tmp &= ~priv->cs_mask; snd_ice1712_akm4xxx_write() 111 snd_ice1712_gpio_write(ice, tmp); snd_ice1712_akm4xxx_write() 114 tmp |= priv->cs_mask; /* chip select high to trigger */ snd_ice1712_akm4xxx_write() 116 tmp &= ~priv->cs_mask; snd_ice1712_akm4xxx_write() 117 tmp |= priv->cs_none; /* deselect address */ snd_ice1712_akm4xxx_write() 119 snd_ice1712_gpio_write(ice, tmp); snd_ice1712_akm4xxx_write()
H A D	delta.c	47 static void ap_cs8427_write_byte(struct snd_ice1712 *ice, unsigned char data, unsigned char tmp) ap_cs8427_write_byte() argument 52 tmp &= ~(ICE1712_DELTA_AP_DOUT|ICE1712_DELTA_AP_CCLK); ap_cs8427_write_byte() 54 tmp |= ICE1712_DELTA_AP_DOUT; ap_cs8427_write_byte() 55 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp); ap_cs8427_write_byte() 57 tmp |= ICE1712_DELTA_AP_CCLK; ap_cs8427_write_byte() 58 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp); ap_cs8427_write_byte() 64 static unsigned char ap_cs8427_read_byte(struct snd_ice1712 *ice, unsigned char tmp) ap_cs8427_read_byte() argument 70 tmp &= ~ICE1712_DELTA_AP_CCLK; ap_cs8427_read_byte() 71 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp); ap_cs8427_read_byte() 75 tmp |= ICE1712_DELTA_AP_CCLK; ap_cs8427_read_byte() 76 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp); ap_cs8427_read_byte() 85 unsigned char tmp; ap_cs8427_codec_select() local 86 tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA); ap_cs8427_codec_select() 90 tmp &= ~ICE1712_DELTA_1010LT_CS; ap_cs8427_codec_select() 91 tmp |= ICE1712_DELTA_1010LT_CCLK | ICE1712_DELTA_1010LT_CS_CS8427; ap_cs8427_codec_select() 95 tmp |= ICE1712_DELTA_AP_CCLK | ICE1712_DELTA_AP_CS_CODEC; ap_cs8427_codec_select() 96 tmp &= ~ICE1712_DELTA_AP_CS_DIGITAL; ap_cs8427_codec_select() 99 tmp |= ICE1712_DELTA_66E_CCLK | ICE1712_DELTA_66E_CS_CHIP_A | ap_cs8427_codec_select() 101 tmp &= ~ICE1712_DELTA_66E_CS_CS8427; ap_cs8427_codec_select() 104 tmp |= ICE1712_VX442_CCLK | ICE1712_VX442_CODEC_CHIP_A | ICE1712_VX442_CODEC_CHIP_B; ap_cs8427_codec_select() 105 tmp &= ~ICE1712_VX442_CS_DIGITAL; ap_cs8427_codec_select() 108 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp); ap_cs8427_codec_select() 110 return tmp; ap_cs8427_codec_select() 114 static void ap_cs8427_codec_deassert(struct snd_ice1712 *ice, unsigned char tmp) ap_cs8427_codec_deassert() argument 119 tmp &= ~ICE1712_DELTA_1010LT_CS; ap_cs8427_codec_deassert() 120 tmp |= ICE1712_DELTA_1010LT_CS_NONE; ap_cs8427_codec_deassert() 124 tmp |= ICE1712_DELTA_AP_CS_DIGITAL; ap_cs8427_codec_deassert() 127 tmp |= ICE1712_DELTA_66E_CS_CS8427; ap_cs8427_codec_deassert() 130 tmp |= ICE1712_VX442_CS_DIGITAL; ap_cs8427_codec_deassert() 133 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp); ap_cs8427_codec_deassert() 141 unsigned char tmp; ap_cs8427_sendbytes() local 144 tmp = ap_cs8427_codec_select(ice); ap_cs8427_sendbytes() 145 ap_cs8427_write_byte(ice, (device->addr << 1) | 0, tmp); /* address + write mode */ ap_cs8427_sendbytes() 147 ap_cs8427_write_byte(ice, *bytes++, tmp); ap_cs8427_sendbytes() 148 ap_cs8427_codec_deassert(ice, tmp); ap_cs8427_sendbytes() 158 unsigned char tmp; ap_cs8427_readbytes() local 161 tmp = ap_cs8427_codec_select(ice); ap_cs8427_readbytes() 162 ap_cs8427_write_byte(ice, (device->addr << 1) | 1, tmp); /* address + read mode */ ap_cs8427_readbytes() 164 *bytes++ = ap_cs8427_read_byte(ice, tmp); ap_cs8427_readbytes() 165 ap_cs8427_codec_deassert(ice, tmp); ap_cs8427_readbytes() 188 unsigned char tmp, mask1, mask2; snd_ice1712_delta_cs8403_spdif_write() local 194 tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA); snd_ice1712_delta_cs8403_spdif_write() 196 tmp &= ~(mask1 | mask2); snd_ice1712_delta_cs8403_spdif_write() 198 tmp |= mask2; snd_ice1712_delta_cs8403_spdif_write() 199 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp); snd_ice1712_delta_cs8403_spdif_write() 201 tmp |= mask1; snd_ice1712_delta_cs8403_spdif_write() 202 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp); snd_ice1712_delta_cs8403_spdif_write() 205 tmp &= ~mask1; snd_ice1712_delta_cs8403_spdif_write() 206 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp); snd_ice1712_delta_cs8403_spdif_write() 318 unsigned char tmp, tmp2; delta_1010_set_rate_val() local 324 tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA); delta_1010_set_rate_val() 325 tmp2 = tmp & ~ICE1712_DELTA_DFS; delta_1010_set_rate_val() 328 if (tmp != tmp2) delta_1010_set_rate_val() 338 unsigned char tmp, tmp2; delta_ak4524_set_rate_val() local 346 tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA); delta_ak4524_set_rate_val() 348 tmp2 = tmp & ~ICE1712_DELTA_DFS; delta_ak4524_set_rate_val() 351 if (tmp == tmp2) delta_ak4524_set_rate_val() 357 tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA) & ~ICE1712_DELTA_DFS; delta_ak4524_set_rate_val() 359 tmp |= ICE1712_DELTA_DFS; delta_ak4524_set_rate_val() 360 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp); delta_ak4524_set_rate_val() 397 unsigned int tmp; delta_setup_spdif() local 401 tmp = ice->spdif.cs8403_stream_bits; delta_setup_spdif() 402 if (tmp & 0x01) /* consumer */ delta_setup_spdif() 403 tmp &= (tmp & 0x01) ? ~0x06 : ~0x18; delta_setup_spdif() 405 case 32000: tmp |= (tmp & 0x01) ? 0x04 : 0x00; break; delta_setup_spdif() 406 case 44100: tmp |= (tmp & 0x01) ? 0x00 : 0x10; break; delta_setup_spdif() 407 case 48000: tmp |= (tmp & 0x01) ? 0x02 : 0x08; break; delta_setup_spdif() 408 default: tmp |= (tmp & 0x01) ? 0x00 : 0x18; break; delta_setup_spdif() 410 change = ice->spdif.cs8403_stream_bits != tmp; delta_setup_spdif() 411 ice->spdif.cs8403_stream_bits = tmp; delta_setup_spdif() 415 snd_ice1712_delta_cs8403_spdif_write(ice, tmp); delta_setup_spdif() 632 unsigned char tmp; snd_ice1712_delta_init() local 680 tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA); snd_ice1712_delta_init() 681 tmp |= ICE1712_DELTA_AP_CCLK; snd_ice1712_delta_init() 682 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp); snd_ice1712_delta_init()
/linux-4.4.14/drivers/media/dvb-frontends/
H A D	stv0297.c	137 u64 tmp; stv0297_get_symbolrate() local 139 tmp = (u64)(stv0297_readreg(state, 0x55) stv0297_get_symbolrate() 144 tmp *= STV0297_CLOCK_KHZ; stv0297_get_symbolrate() 145 tmp >>= 32; stv0297_get_symbolrate() 147 return (u32) tmp; stv0297_get_symbolrate() 152 long tmp; stv0297_set_symbolrate() local 154 tmp = 131072L * srate; /* 131072 = 2^17 */ stv0297_set_symbolrate() 155 tmp = tmp / (STV0297_CLOCK_KHZ / 4); /* 1/4 = 2^-2 */ stv0297_set_symbolrate() 156 tmp = tmp * 8192L; /* 8192 = 2^13 */ stv0297_set_symbolrate() 158 stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF)); stv0297_set_symbolrate() 159 stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8)); stv0297_set_symbolrate() 160 stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16)); stv0297_set_symbolrate() 161 stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24)); stv0297_set_symbolrate() 166 long tmp; stv0297_set_sweeprate() local 168 tmp = (long) fshift *262144L; /* 262144 = 2*18 */ stv0297_set_sweeprate() 169 tmp /= symrate; stv0297_set_sweeprate() 170 tmp *= 1024; /* 1024 = 2*10 */ stv0297_set_sweeprate() 173 if (tmp >= 0) { stv0297_set_sweeprate() 174 tmp += 500000; stv0297_set_sweeprate() 176 tmp -= 500000; stv0297_set_sweeprate() 178 tmp /= 1000000; stv0297_set_sweeprate() 180 stv0297_writereg(state, 0x60, tmp & 0xFF); stv0297_set_sweeprate() 181 stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0); stv0297_set_sweeprate() 186 long tmp; stv0297_set_carrieroffset() local 189 tmp = offset * 26844L; /* (2**28)/10000 */ stv0297_set_carrieroffset() 190 if (tmp < 0) stv0297_set_carrieroffset() 191 tmp += 0x10000000; stv0297_set_carrieroffset() 192 tmp &= 0x0FFFFFFF; stv0297_set_carrieroffset() 194 stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF)); stv0297_set_carrieroffset() 195 stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8)); stv0297_set_carrieroffset() 196 stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16)); stv0297_set_carrieroffset() 197 stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f); stv0297_set_carrieroffset() 203 s64 tmp; 207 tmp = stv0297_readreg(state, 0x66); 208 tmp |= (stv0297_readreg(state, 0x67) << 8); 209 tmp |= (stv0297_readreg(state, 0x68) << 16); 210 tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24; 212 tmp *= stv0297_get_symbolrate(state); 213 tmp >>= 28; 215 return (s32) tmp; 221 s32 tmp; stv0297_set_initialdemodfreq() local 226 tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16); stv0297_set_initialdemodfreq() 227 tmp = (freq * 1000) / tmp; stv0297_set_initialdemodfreq() 228 if (tmp > 0xffff) stv0297_set_initialdemodfreq() 229 tmp = 0xffff; stv0297_set_initialdemodfreq() 232 stv0297_writereg(state, 0x21, tmp >> 8); stv0297_set_initialdemodfreq() 233 stv0297_writereg(state, 0x20, tmp); stv0297_set_initialdemodfreq() 365 u16 tmp; stv0297_read_signal_strength() local 368 tmp = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0]; stv0297_read_signal_strength() 370 if (tmp < 0x200) stv0297_read_signal_strength() 371 tmp = 0; stv0297_read_signal_strength() 373 tmp = tmp - 0x200; stv0297_read_signal_strength() 375 if (tmp > 0x1ff) stv0297_read_signal_strength() 376 tmp = 0; stv0297_read_signal_strength() 378 tmp = 0x1ff - tmp; stv0297_read_signal_strength() 380 *strength = (tmp << 7) | (tmp >> 2); stv0297_read_signal_strength()
H A D	ec100.c	94 u8 tmp, tmp2; ec100_set_frontend() local 123 tmp = 0xb7; ec100_set_frontend() 127 tmp = 0x00; ec100_set_frontend() 132 tmp = 0x49; ec100_set_frontend() 136 ret = ec100_write_reg(state, 0x1b, tmp); ec100_set_frontend() 181 u8 tmp; ec100_read_status() local 184 ret = ec100_read_reg(state, 0x42, &tmp); ec100_read_status() 188 if (tmp & 0x80) { ec100_read_status() 193 ret = ec100_read_reg(state, 0x01, &tmp); ec100_read_status() 197 if (tmp & 0x10) { ec100_read_status() 200 if (!(tmp & 0x01)) { ec100_read_status() 217 u8 tmp, tmp2; ec100_read_ber() local 222 ret = ec100_read_reg(state, 0x65, &tmp); ec100_read_ber() 229 ber2 = (tmp2 << 8) | tmp; ec100_read_ber() 249 u8 tmp; ec100_read_signal_strength() local 251 ret = ec100_read_reg(state, 0x24, &tmp); ec100_read_signal_strength() 257 *strength = ((tmp << 8) | tmp); ec100_read_signal_strength() 290 u8 tmp; ec100_attach() local 302 ret = ec100_read_reg(state, 0x33, &tmp); ec100_attach() 303 if (ret || tmp != 0x0b) ec100_attach()
H A D	hd29l2.c	108 u8 tmp; hd29l2_wr_reg_mask() local 112 ret = hd29l2_rd_regs(priv, reg, &tmp, 1); hd29l2_wr_reg_mask() 117 tmp &= ~mask; hd29l2_wr_reg_mask() 118 val |= tmp; hd29l2_wr_reg_mask() 128 u8 tmp; hd29l2_rd_reg_mask() local 130 ret = hd29l2_rd_regs(priv, reg, &tmp, 1); hd29l2_rd_reg_mask() 134 tmp &= mask; hd29l2_rd_reg_mask() 141 *val = tmp >> i; hd29l2_rd_reg_mask() 149 u8 tmp; hd29l2_soft_reset() local 151 ret = hd29l2_rd_reg(priv, 0x26, &tmp); hd29l2_soft_reset() 161 ret = hd29l2_wr_reg(priv, 0x26, tmp); hd29l2_soft_reset() 175 u8 tmp; hd29l2_i2c_gate_ctrl() local 196 ret = hd29l2_rd_reg(priv, 0x9e, &tmp); hd29l2_i2c_gate_ctrl() 200 if (tmp == enable) hd29l2_i2c_gate_ctrl() 254 u16 tmp; hd29l2_read_snr() local 266 tmp = (buf[0] << 8) | buf[1]; hd29l2_read_snr() 270 if (tmp) hd29l2_read_snr() 271 *snr = (LOG10_20736_24 - intlog10(tmp)) / ((1 << 24) / 100); hd29l2_read_snr() 286 u16 tmp; hd29l2_read_signal_strength() local 294 tmp = buf[0] << 8 | buf[1]; hd29l2_read_signal_strength() 295 tmp = ~tmp & 0x0fff; hd29l2_read_signal_strength() 298 *strength = tmp * 0xffff / 0x0fff; hd29l2_read_signal_strength() 345 u8 tmp, buf[3]; hd29l2_search() local 381 tmp = 0xfc; /* tuner type normal */ hd29l2_search() 385 tmp = 0xfe; /* tuner type Zero-IF */ hd29l2_search() 398 ret = hd29l2_wr_reg(priv, 0xab, tmp); hd29l2_search() 437 ret = hd29l2_rd_reg(priv, 0x0d, &tmp); hd29l2_search() 441 if ((((tmp & 0xf0) >= 0x10) && hd29l2_search() 442 ((tmp & 0x0f) == 0x08)) || (tmp >= 0x2c)) hd29l2_search() 467 tmp = (code_rate << 3) | modulation; hd29l2_search() 468 ret = hd29l2_wr_reg_mask(priv, 0x7d, tmp, 0x5f); hd29l2_search() 472 tmp = (carrier << 2) | guard_interval; hd29l2_search() 473 ret = hd29l2_wr_reg_mask(priv, 0x81, tmp, 0x0f); hd29l2_search() 477 tmp = interleave; hd29l2_search() 478 ret = hd29l2_wr_reg_mask(priv, 0x82, tmp, 0x03); hd29l2_search() 539 ret = hd29l2_rd_reg_mask(priv, 0x05, &tmp, 0x01); hd29l2_search() 543 if (tmp) hd29l2_search() 731 u8 tmp; hd29l2_init() local 763 ret = hd29l2_rd_reg(priv, 0x36, &tmp); hd29l2_init() 767 tmp &= 0x1b; hd29l2_init() 768 tmp |= priv->cfg.ts_mode; hd29l2_init() 769 ret = hd29l2_wr_reg(priv, 0x36, tmp); hd29l2_init() 773 ret = hd29l2_rd_reg(priv, 0x31, &tmp); hd29l2_init() 774 tmp &= 0xef; hd29l2_init() 778 tmp |= 0x10; hd29l2_init() 780 ret = hd29l2_wr_reg(priv, 0x31, tmp); hd29l2_init() 803 u8 tmp; hd29l2_attach() local 816 ret = hd29l2_rd_reg(priv, 0x00, &tmp); hd29l2_attach()
/linux-4.4.14/drivers/char/
H A D	tlclk.c	330 unsigned long tmp; store_received_ref_clk3a() local 334 sscanf(buf, "%lX", &tmp); store_received_ref_clk3a() 335 dev_dbg(d, ": tmp = 0x%lX\n", tmp); store_received_ref_clk3a() 337 val = (unsigned char)tmp; store_received_ref_clk3a() 352 unsigned long tmp; store_received_ref_clk3b() local 356 sscanf(buf, "%lX", &tmp); store_received_ref_clk3b() 357 dev_dbg(d, ": tmp = 0x%lX\n", tmp); store_received_ref_clk3b() 359 val = (unsigned char)tmp; store_received_ref_clk3b() 374 unsigned long tmp; store_enable_clk3b_output() local 378 sscanf(buf, "%lX", &tmp); store_enable_clk3b_output() 379 dev_dbg(d, ": tmp = 0x%lX\n", tmp); store_enable_clk3b_output() 381 val = (unsigned char)tmp; store_enable_clk3b_output() 396 unsigned long tmp; store_enable_clk3a_output() local 399 sscanf(buf, "%lX", &tmp); store_enable_clk3a_output() 400 dev_dbg(d, "tmp = 0x%lX\n", tmp); store_enable_clk3a_output() 402 val = (unsigned char)tmp; store_enable_clk3a_output() 417 unsigned long tmp; store_enable_clkb1_output() local 420 sscanf(buf, "%lX", &tmp); store_enable_clkb1_output() 421 dev_dbg(d, "tmp = 0x%lX\n", tmp); store_enable_clkb1_output() 423 val = (unsigned char)tmp; store_enable_clkb1_output() 439 unsigned long tmp; store_enable_clka1_output() local 442 sscanf(buf, "%lX", &tmp); store_enable_clka1_output() 443 dev_dbg(d, "tmp = 0x%lX\n", tmp); store_enable_clka1_output() 445 val = (unsigned char)tmp; store_enable_clka1_output() 460 unsigned long tmp; store_enable_clkb0_output() local 463 sscanf(buf, "%lX", &tmp); store_enable_clkb0_output() 464 dev_dbg(d, "tmp = 0x%lX\n", tmp); store_enable_clkb0_output() 466 val = (unsigned char)tmp; store_enable_clkb0_output() 481 unsigned long tmp; store_enable_clka0_output() local 484 sscanf(buf, "%lX", &tmp); store_enable_clka0_output() 485 dev_dbg(d, "tmp = 0x%lX\n", tmp); store_enable_clka0_output() 487 val = (unsigned char)tmp; store_enable_clka0_output() 502 unsigned long tmp; store_select_amcb2_transmit_clock() local 505 sscanf(buf, "%lX", &tmp); store_select_amcb2_transmit_clock() 506 dev_dbg(d, "tmp = 0x%lX\n", tmp); store_select_amcb2_transmit_clock() 508 val = (unsigned char)tmp; store_select_amcb2_transmit_clock() 543 unsigned long tmp; store_select_amcb1_transmit_clock() local 547 sscanf(buf, "%lX", &tmp); store_select_amcb1_transmit_clock() 548 dev_dbg(d, "tmp = 0x%lX\n", tmp); store_select_amcb1_transmit_clock() 550 val = (unsigned char)tmp; store_select_amcb1_transmit_clock() 584 unsigned long tmp; store_select_redundant_clock() local 588 sscanf(buf, "%lX", &tmp); store_select_redundant_clock() 589 dev_dbg(d, "tmp = 0x%lX\n", tmp); store_select_redundant_clock() 591 val = (unsigned char)tmp; store_select_redundant_clock() 605 unsigned long tmp; store_select_ref_frequency() local 609 sscanf(buf, "%lX", &tmp); store_select_ref_frequency() 610 dev_dbg(d, "tmp = 0x%lX\n", tmp); store_select_ref_frequency() 612 val = (unsigned char)tmp; store_select_ref_frequency() 626 unsigned long tmp; store_filter_select() local 630 sscanf(buf, "%lX", &tmp); store_filter_select() 631 dev_dbg(d, "tmp = 0x%lX\n", tmp); store_filter_select() 633 val = (unsigned char)tmp; store_filter_select() 646 unsigned long tmp; store_hardware_switching_mode() local 650 sscanf(buf, "%lX", &tmp); store_hardware_switching_mode() 651 dev_dbg(d, "tmp = 0x%lX\n", tmp); store_hardware_switching_mode() 653 val = (unsigned char)tmp; store_hardware_switching_mode() 667 unsigned long tmp; store_hardware_switching() local 671 sscanf(buf, "%lX", &tmp); store_hardware_switching() 672 dev_dbg(d, "tmp = 0x%lX\n", tmp); store_hardware_switching() 674 val = (unsigned char)tmp; store_hardware_switching() 688 unsigned long tmp; store_refalign() local 691 sscanf(buf, "%lX", &tmp); store_refalign() 692 dev_dbg(d, "tmp = 0x%lX\n", tmp); store_refalign() 707 unsigned long tmp; store_mode_select() local 711 sscanf(buf, "%lX", &tmp); store_mode_select() 712 dev_dbg(d, "tmp = 0x%lX\n", tmp); store_mode_select() 714 val = (unsigned char)tmp; store_mode_select() 727 unsigned long tmp; store_reset() local 731 sscanf(buf, "%lX", &tmp); store_reset() 732 dev_dbg(d, "tmp = 0x%lX\n", tmp); store_reset() 734 val = (unsigned char)tmp; store_reset()
H A D	ttyprintk.c	45 static char tmp[TPK_STR_SIZE + 4]; tpk_printk() local 49 /* flush tmp[] */ tpk_printk() 52 tmp[tpk_curr + 0] = '\n'; tpk_printk() 53 tmp[tpk_curr + 1] = '\0'; tpk_printk() 54 printk(KERN_INFO "%s%s", tpk_tag, tmp); tpk_printk() 61 tmp[tpk_curr] = buf[i]; tpk_printk() 66 tmp[tpk_curr + 0] = '\n'; tpk_printk() 67 tmp[tpk_curr + 1] = '\0'; tpk_printk() 68 printk(KERN_INFO "%s%s", tpk_tag, tmp); tpk_printk() 74 tmp[tpk_curr + 1] = '\0'; tpk_printk() 75 printk(KERN_INFO "%s%s", tpk_tag, tmp); tpk_printk() 82 /* end of tmp buffer reached: cut the message in two */ tpk_printk() 83 tmp[tpk_curr + 1] = '\\'; tpk_printk() 84 tmp[tpk_curr + 2] = '\n'; tpk_printk() 85 tmp[tpk_curr + 3] = '\0'; tpk_printk() 86 printk(KERN_INFO "%s%s", tpk_tag, tmp); tpk_printk()
/linux-4.4.14/drivers/isdn/hardware/eicon/
H A D	istream.c	79 char tmp[4]; diva_istream_write() local 88 (dword *)&tmp[0], diva_istream_write() 90 if (tmp[0] & DIVA_DFIFO_READY) { /* No free blocks more */ diva_istream_write() 109 tmp[1] = (char)to_write; diva_istream_write() 110 tmp[0] = (tmp[0] & DIVA_DFIFO_WRAP) | diva_istream_write() 113 if (tmp[0] & DIVA_DFIFO_LAST) { diva_istream_write() 114 tmp[2] = usr1; diva_istream_write() 115 tmp[3] = usr2; diva_istream_write() 123 (dword *)&tmp[0], diva_istream_write() 125 if (tmp[0] & DIVA_DFIFO_WRAP) { diva_istream_write() 157 char tmp[4]; diva_istream_read() local 167 (dword *)&tmp[0], diva_istream_read() 169 if (tmp[1] > max_length) { diva_istream_read() 174 if (!(tmp[0] & DIVA_DFIFO_READY)) { diva_istream_read() 179 to_read = min(max_length, (int)tmp[1]); diva_istream_read() 193 if (tmp[0] & DIVA_DFIFO_LAST) { diva_istream_read() 196 tmp[0] &= DIVA_DFIFO_WRAP; diva_istream_read() 203 (dword *)&tmp[0], diva_istream_read() 205 if (tmp[0] & DIVA_DFIFO_WRAP) { diva_istream_read() 212 *usr1 = tmp[2]; diva_istream_read() 214 *usr2 = tmp[3]; diva_istream_read()
/linux-4.4.14/drivers/gpu/drm/mgag200/
H A D	mgag200_mode.c	229 u8 tmp; mga_g200wb_set_plls() local 305 tmp = RREG8(MGAREG_CRTC_DATA); mga_g200wb_set_plls() 306 if (tmp < 0xff) mga_g200wb_set_plls() 307 WREG8(MGAREG_CRTC_DATA, tmp+1); mga_g200wb_set_plls() 312 tmp = RREG8(DAC_DATA); mga_g200wb_set_plls() 313 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; mga_g200wb_set_plls() 314 WREG8(DAC_DATA, tmp); mga_g200wb_set_plls() 317 tmp = RREG8(DAC_DATA); mga_g200wb_set_plls() 318 tmp |= MGA1064_REMHEADCTL_CLKDIS; mga_g200wb_set_plls() 319 WREG8(DAC_DATA, tmp); mga_g200wb_set_plls() 322 tmp = RREG8(MGAREG_MEM_MISC_READ); mga_g200wb_set_plls() 323 tmp |= 0x3 << 2; mga_g200wb_set_plls() 324 WREG8(MGAREG_MEM_MISC_WRITE, tmp); mga_g200wb_set_plls() 327 tmp = RREG8(DAC_DATA); mga_g200wb_set_plls() 328 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80; mga_g200wb_set_plls() 329 WREG8(DAC_DATA, tmp); mga_g200wb_set_plls() 335 tmp = RREG8(DAC_DATA); mga_g200wb_set_plls() 336 tmp &= ~0x04; mga_g200wb_set_plls() 337 WREG8(DAC_DATA, tmp); mga_g200wb_set_plls() 350 tmp = RREG8(DAC_DATA); mga_g200wb_set_plls() 351 tmp |= 0x04; mga_g200wb_set_plls() 352 WREG_DAC(MGA1064_VREF_CTL, tmp); mga_g200wb_set_plls() 358 tmp = RREG8(DAC_DATA); mga_g200wb_set_plls() 359 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; mga_g200wb_set_plls() 360 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; mga_g200wb_set_plls() 361 WREG8(DAC_DATA, tmp); mga_g200wb_set_plls() 364 tmp = RREG8(DAC_DATA); mga_g200wb_set_plls() 365 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK; mga_g200wb_set_plls() 366 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL; mga_g200wb_set_plls() 367 WREG8(DAC_DATA, tmp); mga_g200wb_set_plls() 371 tmp = RREG8(MGAREG_SEQ_DATA); mga_g200wb_set_plls() 372 tmp &= ~0x8; mga_g200wb_set_plls() 373 WREG8(MGAREG_SEQ_DATA, tmp); mga_g200wb_set_plls() 376 tmp = RREG8(DAC_DATA); mga_g200wb_set_plls() 377 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; mga_g200wb_set_plls() 378 WREG8(DAC_DATA, tmp); mga_g200wb_set_plls() 393 tmp = RREG8(DAC_DATA); mga_g200wb_set_plls() 394 tmp &= ~MGA1064_REMHEADCTL_CLKDIS; mga_g200wb_set_plls() 395 WREG_DAC(MGA1064_REMHEADCTL, tmp); mga_g200wb_set_plls() 406 u8 tmp; mga_g200ev_set_plls() local 440 tmp = RREG8(DAC_DATA); mga_g200ev_set_plls() 441 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; mga_g200ev_set_plls() 442 WREG8(DAC_DATA, tmp); mga_g200ev_set_plls() 444 tmp = RREG8(MGAREG_MEM_MISC_READ); mga_g200ev_set_plls() 445 tmp |= 0x3 << 2; mga_g200ev_set_plls() 446 WREG8(MGAREG_MEM_MISC_WRITE, tmp); mga_g200ev_set_plls() 449 tmp = RREG8(DAC_DATA); mga_g200ev_set_plls() 450 WREG8(DAC_DATA, tmp & ~0x40); mga_g200ev_set_plls() 453 tmp = RREG8(DAC_DATA); mga_g200ev_set_plls() 454 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; mga_g200ev_set_plls() 455 WREG8(DAC_DATA, tmp); mga_g200ev_set_plls() 464 tmp = RREG8(DAC_DATA); mga_g200ev_set_plls() 465 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; mga_g200ev_set_plls() 466 WREG8(DAC_DATA, tmp); mga_g200ev_set_plls() 471 tmp = RREG8(DAC_DATA); mga_g200ev_set_plls() 472 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; mga_g200ev_set_plls() 473 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; mga_g200ev_set_plls() 474 WREG8(DAC_DATA, tmp); mga_g200ev_set_plls() 477 tmp = RREG8(DAC_DATA); mga_g200ev_set_plls() 478 WREG8(DAC_DATA, tmp | 0x40); mga_g200ev_set_plls() 480 tmp = RREG8(MGAREG_MEM_MISC_READ); mga_g200ev_set_plls() 481 tmp |= (0x3 << 2); mga_g200ev_set_plls() 482 WREG8(MGAREG_MEM_MISC_WRITE, tmp); mga_g200ev_set_plls() 485 tmp = RREG8(DAC_DATA); mga_g200ev_set_plls() 486 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; mga_g200ev_set_plls() 487 WREG8(DAC_DATA, tmp); mga_g200ev_set_plls() 500 u8 tmp; mga_g200eh_set_plls() local 537 tmp = RREG8(DAC_DATA); mga_g200eh_set_plls() 538 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; mga_g200eh_set_plls() 539 WREG8(DAC_DATA, tmp); mga_g200eh_set_plls() 541 tmp = RREG8(MGAREG_MEM_MISC_READ); mga_g200eh_set_plls() 542 tmp |= 0x3 << 2; mga_g200eh_set_plls() 543 WREG8(MGAREG_MEM_MISC_WRITE, tmp); mga_g200eh_set_plls() 546 tmp = RREG8(DAC_DATA); mga_g200eh_set_plls() 547 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; mga_g200eh_set_plls() 548 WREG8(DAC_DATA, tmp); mga_g200eh_set_plls() 559 tmp = RREG8(DAC_DATA); mga_g200eh_set_plls() 560 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; mga_g200eh_set_plls() 561 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; mga_g200eh_set_plls() 562 WREG8(DAC_DATA, tmp); mga_g200eh_set_plls() 565 tmp = RREG8(DAC_DATA); mga_g200eh_set_plls() 566 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; mga_g200eh_set_plls() 567 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; mga_g200eh_set_plls() 568 WREG8(DAC_DATA, tmp); mga_g200eh_set_plls() 593 int tmp; mga_g200er_set_plls() local 636 tmp = RREG8(DAC_DATA); mga_g200er_set_plls() 637 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; mga_g200er_set_plls() 638 WREG8(DAC_DATA, tmp); mga_g200er_set_plls() 641 tmp = RREG8(DAC_DATA); mga_g200er_set_plls() 642 tmp |= MGA1064_REMHEADCTL_CLKDIS; mga_g200er_set_plls() 643 WREG8(DAC_DATA, tmp); mga_g200er_set_plls() 645 tmp = RREG8(MGAREG_MEM_MISC_READ); mga_g200er_set_plls() 646 tmp |= (0x3<<2) | 0xc0; mga_g200er_set_plls() 647 WREG8(MGAREG_MEM_MISC_WRITE, tmp); mga_g200er_set_plls() 650 tmp = RREG8(DAC_DATA); mga_g200er_set_plls() 651 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; mga_g200er_set_plls() 652 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; mga_g200er_set_plls() 653 WREG8(DAC_DATA, tmp); mga_g200er_set_plls() 693 u8 tmp; mga_g200wb_prepare() local 700 tmp = RREG8(DAC_DATA); mga_g200wb_prepare() 701 tmp |= 0x10; mga_g200wb_prepare() 702 WREG_DAC(MGA1064_GEN_IO_CTL, tmp); mga_g200wb_prepare() 706 tmp = RREG8(DAC_DATA); mga_g200wb_prepare() 707 tmp |= 0x10; mga_g200wb_prepare() 708 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); mga_g200wb_prepare() 714 tmp = RREG8(DAC_DATA); mga_g200wb_prepare() 715 tmp |= 0x80; mga_g200wb_prepare() 716 WREG_DAC(MGA1064_SPAREREG, tmp); mga_g200wb_prepare() 722 while (!(tmp & 0x1) && iter_max) { mga_g200wb_prepare() 724 tmp = RREG8(DAC_DATA); mga_g200wb_prepare() 735 while ((tmp & 0x2) && iter_max) { mga_g200wb_prepare() 737 tmp = RREG8(DAC_DATA); mga_g200wb_prepare() 746 u8 tmp; mga_g200wb_commit() local 751 tmp = RREG8(MGAREG_CRTCEXT_DATA); mga_g200wb_commit() 752 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88); mga_g200wb_commit() 756 tmp = RREG8(DAC_DATA); mga_g200wb_commit() 757 tmp |= 0x8; mga_g200wb_commit() 758 WREG8(DAC_DATA, tmp); mga_g200wb_commit() 764 tmp &= ~0x08; mga_g200wb_commit() 766 WREG8(DAC_DATA, tmp); mga_g200wb_commit() 770 tmp = RREG8(DAC_DATA); mga_g200wb_commit() 771 tmp &= ~0x80; mga_g200wb_commit() 772 WREG8(DAC_DATA, tmp); mga_g200wb_commit() 776 tmp = RREG8(DAC_DATA); mga_g200wb_commit() 777 tmp &= ~0x10; mga_g200wb_commit() 778 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); mga_g200wb_commit() 1296 u8 tmp; mga_crtc_prepare() local 1301 tmp = RREG8(MGAREG_CRTC_DATA); mga_crtc_prepare() 1302 WREG_CRT(0x11, tmp | 0x80); mga_crtc_prepare() 1311 tmp = RREG8(MGAREG_SEQ_DATA); mga_crtc_prepare() 1315 WREG_SEQ(1, tmp | 0x20); mga_crtc_prepare() 1333 u8 tmp; mga_crtc_commit() local 1345 tmp = RREG8(MGAREG_SEQ_DATA); mga_crtc_commit() 1347 tmp &= ~0x20; mga_crtc_commit() 1348 WREG_SEQ(0x1, tmp); mga_crtc_commit()
/linux-4.4.14/drivers/clk/at91/
H A D	clk-smd.c	36 u32 tmp; at91sam9x5_clk_smd_recalc_rate() local 41 tmp = pmc_read(pmc, AT91_PMC_SMD); at91sam9x5_clk_smd_recalc_rate() 42 smddiv = (tmp & AT91_PMC_SMD_DIV) >> SMD_DIV_SHIFT; at91sam9x5_clk_smd_recalc_rate() 51 unsigned long tmp; at91sam9x5_clk_smd_round_rate() local 61 tmp = *parent_rate / (div + 1); at91sam9x5_clk_smd_round_rate() 62 if (bestrate - rate > rate - tmp) at91sam9x5_clk_smd_round_rate() 63 bestrate = tmp; at91sam9x5_clk_smd_round_rate() 70 u32 tmp; at91sam9x5_clk_smd_set_parent() local 76 tmp = pmc_read(pmc, AT91_PMC_SMD) & ~AT91_PMC_SMDS; at91sam9x5_clk_smd_set_parent() 78 tmp |= AT91_PMC_SMDS; at91sam9x5_clk_smd_set_parent() 79 pmc_write(pmc, AT91_PMC_SMD, tmp); at91sam9x5_clk_smd_set_parent() 94 u32 tmp; at91sam9x5_clk_smd_set_rate() local 101 tmp = pmc_read(pmc, AT91_PMC_SMD) & ~AT91_PMC_SMD_DIV; at91sam9x5_clk_smd_set_rate() 102 tmp |= (div - 1) << SMD_DIV_SHIFT; at91sam9x5_clk_smd_set_rate() 103 pmc_write(pmc, AT91_PMC_SMD, tmp); at91sam9x5_clk_smd_set_rate()
H A D	clk-main.c	86 u32 tmp; clk_main_osc_prepare() local 88 tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK; clk_main_osc_prepare() 89 if (tmp & AT91_PMC_OSCBYPASS) clk_main_osc_prepare() 92 if (!(tmp & AT91_PMC_MOSCEN)) { clk_main_osc_prepare() 93 tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY; clk_main_osc_prepare() 94 pmc_write(pmc, AT91_CKGR_MOR, tmp); clk_main_osc_prepare() 110 u32 tmp = pmc_read(pmc, AT91_CKGR_MOR); clk_main_osc_unprepare() local 112 if (tmp & AT91_PMC_OSCBYPASS) clk_main_osc_unprepare() 115 if (!(tmp & AT91_PMC_MOSCEN)) clk_main_osc_unprepare() 118 tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN); clk_main_osc_unprepare() 119 pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY); clk_main_osc_unprepare() 126 u32 tmp = pmc_read(pmc, AT91_CKGR_MOR); clk_main_osc_is_prepared() local 128 if (tmp & AT91_PMC_OSCBYPASS) clk_main_osc_is_prepared() 232 u32 tmp; clk_main_rc_osc_prepare() local 234 tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK; clk_main_rc_osc_prepare() 236 if (!(tmp & AT91_PMC_MOSCRCEN)) { clk_main_rc_osc_prepare() 237 tmp |= AT91_PMC_MOSCRCEN | AT91_PMC_KEY; clk_main_rc_osc_prepare() 238 pmc_write(pmc, AT91_CKGR_MOR, tmp); clk_main_rc_osc_prepare() 254 u32 tmp = pmc_read(pmc, AT91_CKGR_MOR); clk_main_rc_osc_unprepare() local 256 if (!(tmp & AT91_PMC_MOSCRCEN)) clk_main_rc_osc_unprepare() 259 tmp &= ~(MOR_KEY_MASK | AT91_PMC_MOSCRCEN); clk_main_rc_osc_unprepare() 260 pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY); clk_main_rc_osc_unprepare() 371 u32 tmp; clk_main_probe_frequency() local 376 tmp = pmc_read(pmc, AT91_CKGR_MCFR); clk_main_probe_frequency() 377 if (tmp & AT91_PMC_MAINRDY) clk_main_probe_frequency() 388 u32 tmp; clk_main_recalc_rate() local 394 tmp = pmc_read(pmc, AT91_CKGR_MCFR); clk_main_recalc_rate() 395 if (!(tmp & AT91_PMC_MAINRDY)) clk_main_recalc_rate() 398 return ((tmp & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV; clk_main_recalc_rate() 524 u32 tmp; clk_sam9x5_main_set_parent() local 529 tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK; clk_sam9x5_main_set_parent() 531 if (index && !(tmp & AT91_PMC_MOSCSEL)) clk_sam9x5_main_set_parent() 532 pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_MOSCSEL); clk_sam9x5_main_set_parent() 533 else if (!index && (tmp & AT91_PMC_MOSCSEL)) clk_sam9x5_main_set_parent() 534 pmc_write(pmc, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL); clk_sam9x5_main_set_parent()
/linux-4.4.14/drivers/usb/gadget/udc/
H A D	amd5536udc.c	272 u32 tmp; udc_mask_unused_interrupts() local 275 tmp = AMD_BIT(UDC_DEVINT_SVC) | udc_mask_unused_interrupts() 283 writel(tmp, &dev->regs->irqmsk); udc_mask_unused_interrupts() 294 u32 tmp; udc_enable_ep0_interrupts() local 299 tmp = readl(&dev->regs->ep_irqmsk); udc_enable_ep0_interrupts() 301 tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0) udc_enable_ep0_interrupts() 303 writel(tmp, &dev->regs->ep_irqmsk); udc_enable_ep0_interrupts() 311 u32 tmp; udc_enable_dev_setup_interrupts() local 316 tmp = readl(&dev->regs->irqmsk); udc_enable_dev_setup_interrupts() 319 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI) udc_enable_dev_setup_interrupts() 324 writel(tmp, &dev->regs->irqmsk); udc_enable_dev_setup_interrupts() 333 u32 tmp; udc_set_txfifo_addr() local 346 tmp = readl(&dev->ep[i].regs->bufin_framenum); udc_set_txfifo_addr() 347 tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE); udc_set_txfifo_addr() 348 ep->txfifo += tmp; udc_set_txfifo_addr() 374 u32 tmp; udc_ep_enable() local 399 tmp = readl(&dev->ep[ep->num].regs->ctl); udc_ep_enable() 400 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET); udc_ep_enable() 401 writel(tmp, &dev->ep[ep->num].regs->ctl); udc_ep_enable() 405 tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt); udc_ep_enable() 406 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE); udc_ep_enable() 408 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt); udc_ep_enable() 417 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum); udc_ep_enable() 419 tmp = AMD_ADDBITS( udc_ep_enable() 420 tmp, udc_ep_enable() 424 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum); udc_ep_enable() 430 tmp = readl(&ep->regs->ctl); udc_ep_enable() 431 tmp |= AMD_BIT(UDC_EPCTL_F); udc_ep_enable() 432 writel(tmp, &ep->regs->ctl); udc_ep_enable() 440 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]); udc_ep_enable() 441 tmp = AMD_ADDBITS(tmp, maxpacket, udc_ep_enable() 443 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]); udc_ep_enable() 456 tmp = readl(&dev->csr->ne[udc_csr_epix]); udc_ep_enable() 458 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT); udc_ep_enable() 460 tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM); udc_ep_enable() 462 tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR); udc_ep_enable() 464 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE); udc_ep_enable() 466 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG); udc_ep_enable() 468 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF); udc_ep_enable() 470 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT); udc_ep_enable() 472 writel(tmp, &dev->csr->ne[udc_csr_epix]); udc_ep_enable() 475 tmp = readl(&dev->regs->ep_irqmsk); udc_ep_enable() 476 tmp &= AMD_UNMASK_BIT(ep->num); udc_ep_enable() 477 writel(tmp, &dev->regs->ep_irqmsk); udc_ep_enable() 484 tmp = readl(&ep->regs->ctl); udc_ep_enable() 485 tmp |= AMD_BIT(UDC_EPCTL_CNAK); udc_ep_enable() 486 writel(tmp, &ep->regs->ctl); udc_ep_enable() 490 tmp = desc->bEndpointAddress; udc_ep_enable() 500 u32 tmp; ep_init() local 509 tmp = readl(&ep->regs->ctl); ep_init() 510 tmp |= AMD_BIT(UDC_EPCTL_SNAK); ep_init() 511 writel(tmp, &ep->regs->ctl); ep_init() 515 tmp = readl(&regs->ep_irqmsk); ep_init() 516 tmp |= AMD_BIT(ep->num); ep_init() 517 writel(tmp, &regs->ep_irqmsk); ep_init() 521 tmp = readl(&ep->regs->ctl); ep_init() 522 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P); ep_init() 523 writel(tmp, &ep->regs->ctl); ep_init() 525 tmp = readl(&ep->regs->sts); ep_init() 526 tmp |= AMD_BIT(UDC_EPSTS_IN); ep_init() 527 writel(tmp, &ep->regs->sts); ep_init() 530 tmp = readl(&ep->regs->ctl); ep_init() 531 tmp |= AMD_BIT(UDC_EPCTL_F); ep_init() 532 writel(tmp, &ep->regs->ctl); ep_init() 750 u32 tmp; udc_rxfifo_read_bytes() local 760 tmp = readl(dev->rxfifo); udc_rxfifo_read_bytes() 762 *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK); udc_rxfifo_read_bytes() 763 tmp = tmp >> UDC_BITS_PER_BYTE; udc_rxfifo_read_bytes() 929 u32 tmp; prep_dma() local 1002 tmp = readl(&ep->regs->ctl); prep_dma() 1003 tmp |= AMD_BIT(UDC_EPCTL_CNAK); prep_dma() 1004 writel(tmp, &ep->regs->ctl); prep_dma() 1088 u32 tmp; udc_set_rde() local 1097 tmp = readl(&dev->regs->ctl); udc_set_rde() 1098 tmp |= AMD_BIT(UDC_DEVCTL_RDE); udc_set_rde() 1099 writel(tmp, &dev->regs->ctl); udc_set_rde() 1112 u32 tmp; udc_queue() local 1160 tmp = readl(&dev->regs->ctl); udc_queue() 1161 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE); udc_queue() 1162 writel(tmp, &dev->regs->ctl); udc_queue() 1168 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); udc_queue() 1169 tmp |= AMD_BIT(UDC_EPCTL_CNAK); udc_queue() 1170 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); udc_queue() 1199 tmp = readl(&dev->regs->ctl); udc_queue() 1200 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE); udc_queue() 1201 writel(tmp, &dev->regs->ctl); udc_queue() 1220 tmp = readl(&ep->regs->ctl); udc_queue() 1221 tmp |= AMD_BIT(UDC_EPCTL_CNAK); udc_queue() 1222 writel(tmp, &ep->regs->ctl); udc_queue() 1229 tmp = readl(&dev->regs->ep_irqmsk); udc_queue() 1230 tmp &= AMD_UNMASK_BIT(ep->num); udc_queue() 1231 writel(tmp, &dev->regs->ep_irqmsk); udc_queue() 1235 tmp = readl(&dev->regs->ep_irqmsk); udc_queue() 1236 tmp &= AMD_UNMASK_BIT(ep->num); udc_queue() 1237 writel(tmp, &dev->regs->ep_irqmsk); udc_queue() 1328 u32 tmp; udc_dequeue() local 1331 tmp = readl(&udc->regs->ctl); udc_dequeue() 1332 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE), udc_dequeue() 1347 writel(tmp, &udc->regs->ctl); udc_dequeue() 1363 u32 tmp; udc_set_halt() local 1388 tmp = readl(&ep->regs->ctl); udc_set_halt() 1389 tmp |= AMD_BIT(UDC_EPCTL_S); udc_set_halt() 1390 writel(tmp, &ep->regs->ctl); udc_set_halt() 1407 tmp = readl(&ep->regs->ctl); udc_set_halt() 1409 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S); udc_set_halt() 1411 tmp |= AMD_BIT(UDC_EPCTL_CNAK); udc_set_halt() 1412 writel(tmp, &ep->regs->ctl); udc_set_halt() 1448 u32 tmp; udc_remote_wakeup() local 1454 tmp = readl(&dev->regs->ctl); udc_remote_wakeup() 1455 tmp |= AMD_BIT(UDC_DEVCTL_RES); udc_remote_wakeup() 1456 writel(tmp, &dev->regs->ctl); udc_remote_wakeup() 1457 tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES); udc_remote_wakeup() 1458 writel(tmp, &dev->regs->ctl); udc_remote_wakeup() 1512 u32 tmp; udc_basic_init() local 1527 tmp = readl(&dev->regs->ctl); udc_basic_init() 1528 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE); udc_basic_init() 1529 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE); udc_basic_init() 1530 writel(tmp, &dev->regs->ctl); udc_basic_init() 1533 tmp = readl(&dev->regs->cfg); udc_basic_init() 1534 tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG); udc_basic_init() 1536 tmp |= AMD_BIT(UDC_DEVCFG_SP); udc_basic_init() 1538 tmp |= AMD_BIT(UDC_DEVCFG_RWKP); udc_basic_init() 1539 writel(tmp, &dev->regs->cfg); udc_basic_init() 1550 u32 tmp; startup_registers() local 1564 tmp = readl(&dev->regs->cfg); startup_registers() 1566 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD); startup_registers() 1568 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD); startup_registers() 1569 writel(tmp, &dev->regs->cfg); startup_registers() 1578 u32 tmp; udc_setup_endpoints() local 1584 tmp = readl(&dev->regs->sts); udc_setup_endpoints() 1585 tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED); udc_setup_endpoints() 1586 if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH) udc_setup_endpoints() 1588 else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL) udc_setup_endpoints() 1592 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) { udc_setup_endpoints() 1593 ep = &dev->ep[tmp]; udc_setup_endpoints() 1595 ep->ep.name = ep_info[tmp].name; udc_setup_endpoints() 1596 ep->ep.caps = ep_info[tmp].caps; udc_setup_endpoints() 1597 ep->num = tmp; udc_setup_endpoints() 1602 if (tmp < UDC_EPIN_NUM) { udc_setup_endpoints() 1610 ep->regs = &dev->ep_regs[tmp]; udc_setup_endpoints() 1628 if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX udc_setup_endpoints() 1629 && tmp > UDC_EPIN_NUM) { udc_setup_endpoints() 1631 reg = readl(&dev->ep[tmp].regs->ctl); udc_setup_endpoints() 1633 writel(reg, &dev->ep[tmp].regs->ctl); udc_setup_endpoints() 1634 dev->ep[tmp].naking = 1; udc_setup_endpoints() 1707 u32 tmp; udc_tasklet_disconnect() local 1718 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) udc_tasklet_disconnect() 1719 empty_req_queue(&dev->ep[tmp]); udc_tasklet_disconnect() 1738 tmp = readl(&dev->regs->cfg); udc_tasklet_disconnect() 1739 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD); udc_tasklet_disconnect() 1740 writel(tmp, &dev->regs->cfg); udc_tasklet_disconnect() 1771 u32 tmp; udc_timer_function() local 1782 tmp = readl(&udc->regs->ctl); udc_timer_function() 1783 tmp |= AMD_BIT(UDC_DEVCTL_RDE); udc_timer_function() 1784 writel(tmp, &udc->regs->ctl); udc_timer_function() 1821 u32 tmp; udc_handle_halt_state() local 1824 tmp = readl(&ep->regs->ctl); udc_handle_halt_state() 1826 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) { udc_handle_halt_state() 1836 tmp |= AMD_BIT(UDC_EPCTL_S); udc_handle_halt_state() 1837 writel(tmp, &ep->regs->ctl);*/ udc_handle_halt_state() 1840 tmp |= AMD_BIT(UDC_EPCTL_CNAK); udc_handle_halt_state() 1841 writel(tmp, &ep->regs->ctl); udc_handle_halt_state() 1885 u32 tmp; activate_control_endpoints() local 1890 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); activate_control_endpoints() 1891 tmp |= AMD_BIT(UDC_EPCTL_F); activate_control_endpoints() 1892 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); activate_control_endpoints() 1899 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum); activate_control_endpoints() 1901 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE, activate_control_endpoints() 1904 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE, activate_control_endpoints() 1906 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum); activate_control_endpoints() 1909 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt); activate_control_endpoints() 1911 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE, activate_control_endpoints() 1914 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE, activate_control_endpoints() 1916 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt); activate_control_endpoints() 1919 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt); activate_control_endpoints() 1921 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE, activate_control_endpoints() 1924 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE, activate_control_endpoints() 1926 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt); activate_control_endpoints() 1929 tmp = readl(&dev->csr->ne[0]); activate_control_endpoints() 1931 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE, activate_control_endpoints() 1934 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE, activate_control_endpoints() 1936 writel(tmp, &dev->csr->ne[0]); activate_control_endpoints() 1955 tmp = readl(&dev->regs->ctl); activate_control_endpoints() 1956 tmp |= AMD_BIT(UDC_DEVCTL_MODE) activate_control_endpoints() 1960 tmp |= AMD_BIT(UDC_DEVCTL_BF); activate_control_endpoints() 1962 tmp |= AMD_BIT(UDC_DEVCTL_DU); activate_control_endpoints() 1963 writel(tmp, &dev->regs->ctl); activate_control_endpoints() 1967 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); activate_control_endpoints() 1968 tmp |= AMD_BIT(UDC_EPCTL_CNAK); activate_control_endpoints() 1969 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); activate_control_endpoints() 1974 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl); activate_control_endpoints() 1975 tmp |= AMD_BIT(UDC_EPCTL_CNAK); activate_control_endpoints() 1976 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl); activate_control_endpoints() 1998 u32 tmp; amd5536_udc_start() local 2013 tmp = readl(&dev->regs->ctl); amd5536_udc_start() 2014 tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD); amd5536_udc_start() 2015 writel(tmp, &dev->regs->ctl); amd5536_udc_start() 2028 int tmp; variable 2033 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) 2034 empty_req_queue(&dev->ep[tmp]); 2044 u32 tmp; amd5536_udc_stop() local 2054 tmp = readl(&dev->regs->ctl); amd5536_udc_stop() 2055 tmp |= AMD_BIT(UDC_DEVCTL_SD); amd5536_udc_stop() 2056 writel(tmp, &dev->regs->ctl); amd5536_udc_stop() 2064 u32 tmp; udc_process_cnak_queue() local 2069 for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) { udc_process_cnak_queue() 2070 if (cnak_pending & (1 << tmp)) { udc_process_cnak_queue() 2071 DBG(dev, "CNAK pending for ep%d\n", tmp); udc_process_cnak_queue() 2073 reg = readl(&dev->ep[tmp].regs->ctl); udc_process_cnak_queue() 2075 writel(reg, &dev->ep[tmp].regs->ctl); udc_process_cnak_queue() 2076 dev->ep[tmp].naking = 0; udc_process_cnak_queue() 2077 UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num); udc_process_cnak_queue() 2124 u32 tmp; udc_data_out_isr() local 2134 tmp = readl(&ep->regs->sts); udc_data_out_isr() 2137 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) { udc_data_out_isr() 2141 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts); udc_data_out_isr() 2151 if (tmp & AMD_BIT(UDC_EPSTS_HE)) { udc_data_out_isr() 2155 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts); udc_data_out_isr() 2242 tmp = req->req.length - req->req.actual; udc_data_out_isr() 2243 if (count > tmp) { udc_data_out_isr() 2244 if ((tmp % ep->ep.maxpacket) != 0) { udc_data_out_isr() 2246 ep->ep.name, count, tmp); udc_data_out_isr() 2249 count = tmp; udc_data_out_isr() 2338 u32 tmp; udc_data_in_isr() local 2407 tmp = readl(&dev->regs->ep_irqmsk); udc_data_in_isr() 2408 tmp |= AMD_BIT(ep->num); udc_data_in_isr() 2409 writel(tmp, &dev->regs->ep_irqmsk); udc_data_in_isr() 2470 tmp = readl(&ep->regs->ctl); udc_data_in_isr() 2471 tmp |= AMD_BIT(UDC_EPCTL_P); udc_data_in_isr() 2472 writel(tmp, &ep->regs->ctl); udc_data_in_isr() 2478 tmp = readl( udc_data_in_isr() 2480 tmp |= AMD_BIT(ep->num); udc_data_in_isr() 2481 writel(tmp, udc_data_in_isr() 2499 u32 tmp; variable 2511 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts); 2513 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) { 2523 tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT); 2524 VDBG(dev, "data_typ = %x\n", tmp); 2527 if (tmp == UDC_EPSTS_OUT_SETUP) { 2534 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); 2535 tmp |= AMD_BIT(UDC_EPCTL_SNAK); 2536 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); 2616 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); 2621 tmp |= AMD_BIT(UDC_EPCTL_CNAK); 2622 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); 2628 tmp |= AMD_BIT(UDC_EPCTL_S); 2629 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); 2636 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl); 2637 tmp |= AMD_BIT(UDC_EPCTL_CNAK); 2638 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl); 2650 } else if (tmp == UDC_EPSTS_OUT_DATA) { 2713 u32 tmp; udc_control_in_isr() local 2723 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts); udc_control_in_isr() 2725 if (tmp & AMD_BIT(UDC_EPSTS_TDC)) { udc_control_in_isr() 2734 } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) { udc_control_in_isr() 2745 tmp = readl(&ep->regs->ctl); udc_control_in_isr() 2746 tmp |= AMD_BIT(UDC_EPCTL_S); udc_control_in_isr() 2747 writel(tmp, &ep->regs->ctl); udc_control_in_isr() 2765 tmp = udc_control_in_isr() 2767 tmp |= AMD_BIT(UDC_EPCTL_P); udc_control_in_isr() 2768 writel(tmp, udc_control_in_isr() 2815 u32 tmp; variable 2826 tmp = readl(&dev->regs->sts); 2827 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG); 2852 tmp = readl(&dev->csr->ne[udc_csr_epix]); 2854 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, 2857 writel(tmp, &dev->csr->ne[udc_csr_epix]); 2861 tmp = readl(&ep->regs->ctl); 2862 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S); 2863 writel(tmp, &ep->regs->ctl); 2867 tmp = dev->driver->setup(&dev->gadget, &setup_data.request); 2876 tmp = readl(&dev->regs->sts); 2877 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT); 2878 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF); 2907 tmp = readl(&dev->csr->ne[udc_csr_epix]); 2909 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, 2911 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */ 2913 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, 2916 writel(tmp, &dev->csr->ne[udc_csr_epix]); 2920 tmp = readl(&ep->regs->ctl); 2921 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S); 2922 writel(tmp, &ep->regs->ctl); 2927 tmp = dev->driver->setup(&dev->gadget, &setup_data.request); 2958 tmp = readl(&dev->regs->sts); 2959 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) 2971 tmp = readl(&dev->regs->cfg); 2972 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg); 2973 writel(tmp, &dev->regs->cfg); 2982 tmp = readl(&dev->regs->irqmsk); 2983 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US); 2984 writel(tmp, &dev->regs->irqmsk); 3023 tmp = readl(&dev->regs->sts); 3024 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) { 3026 tmp = readl(&dev->regs->irqmsk); 3027 tmp |= AMD_BIT(UDC_DEVINT_US); 3028 writel(tmp, &dev->regs->irqmsk); 3223 char tmp[128]; udc_probe() local 3243 snprintf(tmp, sizeof(tmp), "%d", dev->irq); udc_probe() 3246 tmp, dev->phys_addr, dev->chiprev, udc_probe() 3248 strcpy(tmp, UDC_DRIVER_VERSION_STRING); udc_probe() 3255 "driver version: %s(for Geode5536 B1)\n", tmp); udc_probe()
/linux-4.4.14/arch/cris/arch-v32/mm/
H A D	intmem.c	52 struct intmem_allocation* tmp; crisv32_intmem_alloc() local 58 list_for_each_entry_safe(allocation, tmp, &intmem_allocations, entry) { crisv32_intmem_alloc() 75 struct intmem_allocation *tmp; crisv32_intmem_alloc() local 76 tmp = kmalloc(sizeof *tmp, GFP_ATOMIC); crisv32_intmem_alloc() 77 tmp->offset = allocation->offset; crisv32_intmem_alloc() 78 tmp->size = alignment; crisv32_intmem_alloc() 79 tmp->status = STATUS_FREE; crisv32_intmem_alloc() 81 list_add_tail(&tmp->entry, crisv32_intmem_alloc() 97 struct intmem_allocation* tmp; crisv32_intmem_free() local 105 list_for_each_entry_safe(allocation, tmp, &intmem_allocations, entry) { crisv32_intmem_free()
/linux-4.4.14/arch/arm/include/asm/hardware/
H A D	entry-macro-iomd.S	14 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 16 ldr \tmp, =irq_prio_h 20 addeq \tmp, \tmp, #256 @ irq_prio_h table size 25 addeq \tmp, \tmp, #256 @ irq_prio_d table size 29 addeq \tmp, \tmp, #256 @ irq_prio_l table size 34 addeq \tmp, \tmp, #256 @ irq_prio_lc table size 37 2406: ldrneb \irqnr, [\tmp, \irqstat] @ get IRQ number
/linux-4.4.14/drivers/video/fbdev/aty/
H A D	radeon_pm.c	131 u32 tmp; radeon_pm_disable_dynamic_mode() local 136 tmp = INPLL(pllSCLK_CNTL); radeon_pm_disable_dynamic_mode() 137 tmp &= ~SCLK_CNTL__DYN_STOP_LAT_MASK; radeon_pm_disable_dynamic_mode() 138 tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | SCLK_CNTL__FORCEON_MASK; radeon_pm_disable_dynamic_mode() 139 OUTPLL(pllSCLK_CNTL, tmp); radeon_pm_disable_dynamic_mode() 141 tmp = INPLL(pllMCLK_CNTL); radeon_pm_disable_dynamic_mode() 142 tmp |= (MCLK_CNTL__FORCE_MCLKA | radeon_pm_disable_dynamic_mode() 148 OUTPLL(pllMCLK_CNTL, tmp); radeon_pm_disable_dynamic_mode() 153 tmp = INPLL(pllSCLK_CNTL); radeon_pm_disable_dynamic_mode() 154 tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_HDP | radeon_pm_disable_dynamic_mode() 161 OUTPLL(pllSCLK_CNTL, tmp); radeon_pm_disable_dynamic_mode() 167 tmp = INPLL(pllSCLK_CNTL2); radeon_pm_disable_dynamic_mode() 168 tmp |= (SCLK_CNTL2__R300_FORCE_TCL | radeon_pm_disable_dynamic_mode() 171 OUTPLL(pllSCLK_CNTL2, tmp); radeon_pm_disable_dynamic_mode() 173 tmp = INPLL(pllSCLK_CNTL); radeon_pm_disable_dynamic_mode() 174 tmp |= (SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP | radeon_pm_disable_dynamic_mode() 182 OUTPLL(pllSCLK_CNTL, tmp); radeon_pm_disable_dynamic_mode() 184 tmp = INPLL(pllSCLK_MORE_CNTL); radeon_pm_disable_dynamic_mode() 185 tmp |= (SCLK_MORE_CNTL__FORCE_DISPREGS | SCLK_MORE_CNTL__FORCE_MC_GUI | radeon_pm_disable_dynamic_mode() 187 OUTPLL(pllSCLK_MORE_CNTL, tmp); radeon_pm_disable_dynamic_mode() 189 tmp = INPLL(pllMCLK_CNTL); radeon_pm_disable_dynamic_mode() 190 tmp |= (MCLK_CNTL__FORCE_MCLKA | radeon_pm_disable_dynamic_mode() 195 OUTPLL(pllMCLK_CNTL, tmp); radeon_pm_disable_dynamic_mode() 197 tmp = INPLL(pllVCLK_ECP_CNTL); radeon_pm_disable_dynamic_mode() 198 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | radeon_pm_disable_dynamic_mode() 201 OUTPLL(pllVCLK_ECP_CNTL, tmp); radeon_pm_disable_dynamic_mode() 203 tmp = INPLL(pllPIXCLKS_CNTL); radeon_pm_disable_dynamic_mode() 204 tmp &= ~(PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb | radeon_pm_disable_dynamic_mode() 217 OUTPLL(pllPIXCLKS_CNTL, tmp); radeon_pm_disable_dynamic_mode() 225 tmp = INPLL(pllSCLK_CNTL); radeon_pm_disable_dynamic_mode() 226 tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_E2); radeon_pm_disable_dynamic_mode() 232 tmp |= SCLK_CNTL__FORCE_HDP| radeon_pm_disable_dynamic_mode() 250 tmp |= SCLK_CNTL__FORCE_HDP | radeon_pm_disable_dynamic_mode() 257 OUTPLL(pllSCLK_CNTL, tmp); radeon_pm_disable_dynamic_mode() 261 tmp = INPLL(pllSCLK_CNTL2); radeon_pm_disable_dynamic_mode() 262 tmp |= SCLK_CNTL2__R300_FORCE_TCL | radeon_pm_disable_dynamic_mode() 265 OUTPLL(pllSCLK_CNTL2, tmp); radeon_pm_disable_dynamic_mode() 269 tmp = INPLL(pllCLK_PIN_CNTL); radeon_pm_disable_dynamic_mode() 270 tmp &= ~CLK_PIN_CNTL__SCLK_DYN_START_CNTL; radeon_pm_disable_dynamic_mode() 271 OUTPLL(pllCLK_PIN_CNTL, tmp); radeon_pm_disable_dynamic_mode() 278 tmp = INPLL(pllMCLK_CNTL); radeon_pm_disable_dynamic_mode() 279 tmp &= ~(MCLK_CNTL__FORCE_MCLKA | radeon_pm_disable_dynamic_mode() 281 OUTPLL(pllMCLK_CNTL, tmp); radeon_pm_disable_dynamic_mode() 286 tmp = INPLL(pllMCLK_CNTL); radeon_pm_disable_dynamic_mode() 287 tmp |= (MCLK_CNTL__FORCE_MCLKA | radeon_pm_disable_dynamic_mode() 291 OUTPLL(pllMCLK_CNTL, tmp); radeon_pm_disable_dynamic_mode() 294 tmp = INPLL(pllMCLK_MISC); radeon_pm_disable_dynamic_mode() 295 tmp &= ~(MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT| radeon_pm_disable_dynamic_mode() 299 OUTPLL(pllMCLK_MISC, tmp); radeon_pm_disable_dynamic_mode() 304 tmp = INPLL(pllSCLK_MORE_CNTL); radeon_pm_disable_dynamic_mode() 305 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS| radeon_pm_disable_dynamic_mode() 308 OUTPLL(pllSCLK_MORE_CNTL, tmp); radeon_pm_disable_dynamic_mode() 312 tmp = INPLL(pllPIXCLKS_CNTL); radeon_pm_disable_dynamic_mode() 313 tmp &= ~(PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb | radeon_pm_disable_dynamic_mode() 320 OUTPLL(pllPIXCLKS_CNTL, tmp); radeon_pm_disable_dynamic_mode() 323 tmp = INPLL( pllVCLK_ECP_CNTL); radeon_pm_disable_dynamic_mode() 324 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | radeon_pm_disable_dynamic_mode() 326 OUTPLL( pllVCLK_ECP_CNTL, tmp); radeon_pm_disable_dynamic_mode() 332 u32 tmp; radeon_pm_enable_dynamic_mode() local 336 tmp = INPLL(pllSCLK_CNTL); radeon_pm_enable_dynamic_mode() 339 tmp &= ~(SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_RB); radeon_pm_enable_dynamic_mode() 340 tmp &= ~(SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 | radeon_pm_enable_dynamic_mode() 345 OUTPLL(pllSCLK_CNTL, tmp); radeon_pm_enable_dynamic_mode() 351 tmp = INPLL(pllSCLK_CNTL2); radeon_pm_enable_dynamic_mode() 352 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL | radeon_pm_enable_dynamic_mode() 355 tmp |= (SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT | radeon_pm_enable_dynamic_mode() 358 OUTPLL(pllSCLK_CNTL2, tmp); radeon_pm_enable_dynamic_mode() 360 tmp = INPLL(pllSCLK_CNTL); radeon_pm_enable_dynamic_mode() 361 tmp &= ~(SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP | radeon_pm_enable_dynamic_mode() 369 tmp |= SCLK_CNTL__DYN_STOP_LAT_MASK; radeon_pm_enable_dynamic_mode() 370 OUTPLL(pllSCLK_CNTL, tmp); radeon_pm_enable_dynamic_mode() 372 tmp = INPLL(pllSCLK_MORE_CNTL); radeon_pm_enable_dynamic_mode() 373 tmp &= ~SCLK_MORE_CNTL__FORCEON; radeon_pm_enable_dynamic_mode() 374 tmp |= SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT | radeon_pm_enable_dynamic_mode() 377 OUTPLL(pllSCLK_MORE_CNTL, tmp); radeon_pm_enable_dynamic_mode() 379 tmp = INPLL(pllVCLK_ECP_CNTL); radeon_pm_enable_dynamic_mode() 380 tmp |= (VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | radeon_pm_enable_dynamic_mode() 382 OUTPLL(pllVCLK_ECP_CNTL, tmp); radeon_pm_enable_dynamic_mode() 384 tmp = INPLL(pllPIXCLKS_CNTL); radeon_pm_enable_dynamic_mode() 385 tmp |= (PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb | radeon_pm_enable_dynamic_mode() 398 OUTPLL(pllPIXCLKS_CNTL, tmp); radeon_pm_enable_dynamic_mode() 400 tmp = INPLL(pllMCLK_MISC); radeon_pm_enable_dynamic_mode() 401 tmp |= (MCLK_MISC__MC_MCLK_DYN_ENABLE | radeon_pm_enable_dynamic_mode() 403 OUTPLL(pllMCLK_MISC, tmp); radeon_pm_enable_dynamic_mode() 405 tmp = INPLL(pllMCLK_CNTL); radeon_pm_enable_dynamic_mode() 406 tmp |= (MCLK_CNTL__FORCE_MCLKA | MCLK_CNTL__FORCE_MCLKB); radeon_pm_enable_dynamic_mode() 407 tmp &= ~(MCLK_CNTL__FORCE_YCLKA | radeon_pm_enable_dynamic_mode() 416 if ((tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKA) && radeon_pm_enable_dynamic_mode() 417 (tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKB)) { radeon_pm_enable_dynamic_mode() 419 tmp = INPLL(pllMCLK_CNTL); radeon_pm_enable_dynamic_mode() 422 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKB; radeon_pm_enable_dynamic_mode() 424 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKA; radeon_pm_enable_dynamic_mode() 426 tmp &= ~(MCLK_CNTL__R300_DISABLE_MC_MCLKA | radeon_pm_enable_dynamic_mode() 430 OUTPLL(pllMCLK_CNTL, tmp); radeon_pm_enable_dynamic_mode() 436 tmp = INPLL(pllSCLK_CNTL); radeon_pm_enable_dynamic_mode() 437 tmp &= ~(SCLK_CNTL__R300_FORCE_VAP); radeon_pm_enable_dynamic_mode() 438 tmp |= SCLK_CNTL__FORCE_CP; radeon_pm_enable_dynamic_mode() 439 OUTPLL(pllSCLK_CNTL, tmp); radeon_pm_enable_dynamic_mode() 442 tmp = INPLL(pllSCLK_CNTL2); radeon_pm_enable_dynamic_mode() 443 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL | radeon_pm_enable_dynamic_mode() 446 OUTPLL(pllSCLK_CNTL2, tmp); radeon_pm_enable_dynamic_mode() 451 tmp = INPLL( pllCLK_PWRMGT_CNTL); radeon_pm_enable_dynamic_mode() 452 tmp &= ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK| radeon_pm_enable_dynamic_mode() 455 tmp |= CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK | radeon_pm_enable_dynamic_mode() 457 OUTPLL( pllCLK_PWRMGT_CNTL, tmp); radeon_pm_enable_dynamic_mode() 460 tmp = INPLL(pllCLK_PIN_CNTL); radeon_pm_enable_dynamic_mode() 461 tmp |= CLK_PIN_CNTL__SCLK_DYN_START_CNTL; radeon_pm_enable_dynamic_mode() 462 OUTPLL(pllCLK_PIN_CNTL, tmp); radeon_pm_enable_dynamic_mode() 468 tmp = INPLL(pllSCLK_CNTL); radeon_pm_enable_dynamic_mode() 469 tmp &= ~SCLK_CNTL__FORCEON_MASK; radeon_pm_enable_dynamic_mode() 476 tmp |= SCLK_CNTL__FORCE_CP; radeon_pm_enable_dynamic_mode() 477 tmp |= SCLK_CNTL__FORCE_VIP; radeon_pm_enable_dynamic_mode() 479 OUTPLL(pllSCLK_CNTL, tmp); radeon_pm_enable_dynamic_mode() 485 tmp = INPLL(pllSCLK_MORE_CNTL); radeon_pm_enable_dynamic_mode() 486 tmp &= ~SCLK_MORE_CNTL__FORCEON; radeon_pm_enable_dynamic_mode() 492 tmp |= SCLK_MORE_CNTL__FORCEON; radeon_pm_enable_dynamic_mode() 494 OUTPLL(pllSCLK_MORE_CNTL, tmp); radeon_pm_enable_dynamic_mode() 503 tmp = INPLL(pllPLL_PWRMGT_CNTL); radeon_pm_enable_dynamic_mode() 504 tmp |= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE; radeon_pm_enable_dynamic_mode() 505 OUTPLL(pllPLL_PWRMGT_CNTL, tmp); radeon_pm_enable_dynamic_mode() 509 tmp = INPLL(pllPIXCLKS_CNTL); radeon_pm_enable_dynamic_mode() 510 tmp |= PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb | radeon_pm_enable_dynamic_mode() 517 OUTPLL(pllPIXCLKS_CNTL, tmp); radeon_pm_enable_dynamic_mode() 520 tmp = INPLL(pllVCLK_ECP_CNTL); radeon_pm_enable_dynamic_mode() 521 tmp |= VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | radeon_pm_enable_dynamic_mode() 523 OUTPLL(pllVCLK_ECP_CNTL, tmp); radeon_pm_enable_dynamic_mode() 528 tmp = INPLL(pllMCLK_CNTL); radeon_pm_enable_dynamic_mode() 529 tmp &= ~(MCLK_CNTL__FORCE_MCLKA | radeon_pm_enable_dynamic_mode() 533 OUTPLL(pllMCLK_CNTL, tmp); radeon_pm_enable_dynamic_mode() 536 tmp = INPLL(pllMCLK_MISC); radeon_pm_enable_dynamic_mode() 537 tmp |= MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT| radeon_pm_enable_dynamic_mode() 541 OUTPLL(pllMCLK_MISC, tmp); radeon_pm_enable_dynamic_mode() 833 u32 tmp; radeon_pm_setup_for_suspend() local 951 tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND; radeon_pm_setup_for_suspend() 952 OUTPLL( pllMCLK_MISC, tmp); radeon_pm_setup_for_suspend() 988 tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL; radeon_pm_setup_for_suspend() 989 OUTPLL( pllPLL_PWRMGT_CNTL, tmp); radeon_pm_setup_for_suspend() 1434 u32 tmp, tmp2; radeon_pm_reset_pad_ctlr_strength() local 1440 tmp = INREG(PAD_CTLR_STRENGTH); radeon_pm_reset_pad_ctlr_strength() 1444 if (tmp != tmp2) { radeon_pm_reset_pad_ctlr_strength() 1445 tmp = tmp2; radeon_pm_reset_pad_ctlr_strength() 1459 u32 tmp; radeon_pm_all_ppls_off() local 1461 tmp = INPLL(pllPPLL_CNTL); radeon_pm_all_ppls_off() 1462 OUTPLL(pllPPLL_CNTL, tmp | 0x3); radeon_pm_all_ppls_off() 1463 tmp = INPLL(pllP2PLL_CNTL); radeon_pm_all_ppls_off() 1464 OUTPLL(pllP2PLL_CNTL, tmp | 0x3); radeon_pm_all_ppls_off() 1465 tmp = INPLL(pllSPLL_CNTL); radeon_pm_all_ppls_off() 1466 OUTPLL(pllSPLL_CNTL, tmp | 0x3); radeon_pm_all_ppls_off() 1467 tmp = INPLL(pllMPLL_CNTL); radeon_pm_all_ppls_off() 1468 OUTPLL(pllMPLL_CNTL, tmp | 0x3); radeon_pm_all_ppls_off() 1473 u32 tmp; radeon_pm_start_mclk_sclk() local 1476 tmp = INPLL(pllSCLK_CNTL); radeon_pm_start_mclk_sclk() 1477 OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK); radeon_pm_start_mclk_sclk() 1480 tmp = INPLL(pllSPLL_CNTL); radeon_pm_start_mclk_sclk() 1483 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); radeon_pm_start_mclk_sclk() 1487 tmp = INPLL(pllM_SPLL_REF_FB_DIV); radeon_pm_start_mclk_sclk() 1488 tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul); radeon_pm_start_mclk_sclk() 1489 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp); radeon_pm_start_mclk_sclk() 1492 tmp = INPLL(pllSPLL_CNTL); radeon_pm_start_mclk_sclk() 1493 OUTPLL(pllSPLL_CNTL, tmp & ~1); radeon_pm_start_mclk_sclk() 1499 tmp = INPLL(pllSPLL_CNTL); radeon_pm_start_mclk_sclk() 1500 OUTPLL(pllSPLL_CNTL, tmp & ~0x2); radeon_pm_start_mclk_sclk() 1506 tmp = INPLL(pllSCLK_CNTL); radeon_pm_start_mclk_sclk() 1507 tmp &= ~SCLK_CNTL__SCLK_SRC_SEL_MASK; radeon_pm_start_mclk_sclk() 1508 tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK; radeon_pm_start_mclk_sclk() 1509 OUTPLL(pllSCLK_CNTL, tmp); radeon_pm_start_mclk_sclk() 1515 tmp = INPLL(pllMPLL_CNTL); radeon_pm_start_mclk_sclk() 1518 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); radeon_pm_start_mclk_sclk() 1522 tmp = INPLL(pllM_SPLL_REF_FB_DIV); radeon_pm_start_mclk_sclk() 1523 tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul); radeon_pm_start_mclk_sclk() 1525 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp); radeon_pm_start_mclk_sclk() 1527 tmp = INPLL(pllMPLL_CNTL); radeon_pm_start_mclk_sclk() 1528 OUTPLL(pllMPLL_CNTL, tmp & ~0x2); radeon_pm_start_mclk_sclk() 1534 tmp = INPLL(pllMPLL_CNTL); radeon_pm_start_mclk_sclk() 1535 OUTPLL(pllMPLL_CNTL, tmp & ~0x1); radeon_pm_start_mclk_sclk() 1541 tmp = INPLL(pllMCLK_CNTL); radeon_pm_start_mclk_sclk() 1542 tmp |= rinfo->save_regs[2] & 0xffff; radeon_pm_start_mclk_sclk() 1543 OUTPLL(pllMCLK_CNTL, tmp); radeon_pm_start_mclk_sclk() 1580 u32 r2ec, tmp; radeon_pm_m10_enable_lvds_spread_spectrum() local 1596 tmp = INPLL(pllSSPLL_CNTL); radeon_pm_m10_enable_lvds_spread_spectrum() 1597 OUTPLL(pllSSPLL_CNTL, tmp & ~0x2); radeon_pm_m10_enable_lvds_spread_spectrum() 1599 tmp = INPLL(pllSSPLL_CNTL); radeon_pm_m10_enable_lvds_spread_spectrum() 1600 OUTPLL(pllSSPLL_CNTL, tmp & ~0x1); radeon_pm_m10_enable_lvds_spread_spectrum() 1610 tmp = INREG(LVDS_GEN_CNTL); radeon_pm_m10_enable_lvds_spread_spectrum() 1611 OUTREG(LVDS_GEN_CNTL, tmp | LVDS_EN); radeon_pm_m10_enable_lvds_spread_spectrum() 1614 tmp = INREG(LVDS_PLL_CNTL); radeon_pm_m10_enable_lvds_spread_spectrum() 1615 tmp &= ~0x30000; radeon_pm_m10_enable_lvds_spread_spectrum() 1616 tmp |= 0x10000; radeon_pm_m10_enable_lvds_spread_spectrum() 1617 OUTREG(LVDS_PLL_CNTL, tmp); radeon_pm_m10_enable_lvds_spread_spectrum() 1628 tmp = INPLL(pllSS_TST_CNTL); radeon_pm_m10_enable_lvds_spread_spectrum() 1629 tmp |= 0x00400000; radeon_pm_m10_enable_lvds_spread_spectrum() 1630 OUTPLL(pllSS_TST_CNTL, tmp); radeon_pm_m10_enable_lvds_spread_spectrum() 1635 u32 tmp; radeon_pm_restore_pixel_pll() local 1642 tmp = INPLL(pllVCLK_ECP_CNTL); radeon_pm_restore_pixel_pll() 1643 OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80); radeon_pm_restore_pixel_pll() 1646 tmp = INPLL(pllPPLL_REF_DIV); radeon_pm_restore_pixel_pll() 1647 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div; radeon_pm_restore_pixel_pll() 1648 OUTPLL(pllPPLL_REF_DIV, tmp); radeon_pm_restore_pixel_pll() 1654 tmp = INPLL(pllPPLL_CNTL); radeon_pm_restore_pixel_pll() 1657 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); radeon_pm_restore_pixel_pll() 1665 tmp = INPLL(pllPPLL_CNTL); radeon_pm_restore_pixel_pll() 1666 OUTPLL(pllPPLL_CNTL, tmp & ~0x2); radeon_pm_restore_pixel_pll() 1669 tmp = INPLL(pllPPLL_CNTL); radeon_pm_restore_pixel_pll() 1670 OUTPLL(pllPPLL_CNTL, tmp & ~0x1); radeon_pm_restore_pixel_pll() 1673 tmp = INPLL(pllVCLK_ECP_CNTL); radeon_pm_restore_pixel_pll() 1674 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3); radeon_pm_restore_pixel_pll() 1677 tmp = INPLL(pllVCLK_ECP_CNTL); radeon_pm_restore_pixel_pll() 1678 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3); radeon_pm_restore_pixel_pll() 1722 u32 tmp, i; radeon_reinitialize_M10() local 1759 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK; radeon_reinitialize_M10() 1760 tmp |= 8 << TV_DAC_CNTL_BGADJ__SHIFT; radeon_reinitialize_M10() 1761 OUTREG(TV_DAC_CNTL, tmp); radeon_reinitialize_M10() 1763 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK; radeon_reinitialize_M10() 1764 tmp |= 7 << TV_DAC_CNTL_DACADJ__SHIFT; radeon_reinitialize_M10() 1765 OUTREG(TV_DAC_CNTL, tmp); radeon_reinitialize_M10() 1773 tmp = rinfo->save_regs[1] radeon_reinitialize_M10() 1776 OUTPLL(pllCLK_PWRMGT_CNTL, tmp); radeon_reinitialize_M10() 1803 tmp = rinfo->save_regs[2] & 0xff000000; radeon_reinitialize_M10() 1804 tmp |= MCLK_CNTL__FORCE_MCLKA | radeon_reinitialize_M10() 1809 OUTPLL(pllMCLK_CNTL, tmp); radeon_reinitialize_M10() 1812 tmp = INPLL(pllSCLK_CNTL); radeon_reinitialize_M10() 1813 tmp |= SCLK_CNTL__FORCE_DISP2| radeon_reinitialize_M10() 1829 tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | radeon_reinitialize_M10() 1841 OUTPLL(pllSCLK_CNTL, tmp); radeon_reinitialize_M10() 1879 tmp = INPLL(pllSCLK_CNTL2); /* What for ? */ radeon_reinitialize_M10() 1880 OUTPLL(pllSCLK_CNTL2, tmp); radeon_reinitialize_M10() 1882 tmp = INPLL(pllSCLK_MORE_CNTL); radeon_reinitialize_M10() 1883 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS | /* a guess */ radeon_reinitialize_M10() 1886 OUTPLL(pllSCLK_MORE_CNTL, tmp); radeon_reinitialize_M10() 1976 u32 tmp, i; radeon_reinitialize_M9P() local 2010 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK; radeon_reinitialize_M9P() 2011 tmp |= 6 << TV_DAC_CNTL_BGADJ__SHIFT; radeon_reinitialize_M9P() 2012 OUTREG(TV_DAC_CNTL, tmp); radeon_reinitialize_M9P() 2014 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK; radeon_reinitialize_M9P() 2015 tmp |= 6 << TV_DAC_CNTL_DACADJ__SHIFT; radeon_reinitialize_M9P() 2016 OUTREG(TV_DAC_CNTL, tmp); radeon_reinitialize_M9P() 2028 tmp = rinfo->save_regs[1] radeon_reinitialize_M9P() 2031 OUTPLL(pllCLK_PWRMGT_CNTL, tmp); radeon_reinitialize_M9P() 2043 tmp = rinfo->save_regs[2] & 0xff000000; radeon_reinitialize_M9P() 2044 tmp |= MCLK_CNTL__FORCE_MCLKA | radeon_reinitialize_M9P() 2050 OUTPLL(pllMCLK_CNTL, tmp); radeon_reinitialize_M9P() 2053 tmp = 0 | radeon_reinitialize_M9P() 2068 OUTPLL(pllSCLK_CNTL, tmp); radeon_reinitialize_M9P() 2101 tmp = rinfo->save_regs[0]; radeon_reinitialize_M9P() 2102 tmp &= ~PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK; radeon_reinitialize_M9P() 2103 tmp |= PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK; radeon_reinitialize_M9P() 2104 OUTPLL(PLL_PWRMGT_CNTL, tmp); radeon_reinitialize_M9P() 2154 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff; radeon_reinitialize_M9P() 2155 tmp |= rinfo->save_regs[34] & 0xffff0000; radeon_reinitialize_M9P() 2156 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS; radeon_reinitialize_M9P() 2157 OUTPLL(pllSCLK_MORE_CNTL, tmp); radeon_reinitialize_M9P() 2159 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff; radeon_reinitialize_M9P() 2160 tmp |= rinfo->save_regs[34] & 0xffff0000; radeon_reinitialize_M9P() 2161 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS; radeon_reinitialize_M9P() 2162 OUTPLL(pllSCLK_MORE_CNTL, tmp); radeon_reinitialize_M9P() 2177 tmp = INPLL(pllSSPLL_CNTL); radeon_reinitialize_M9P() 2178 tmp &= ~2; radeon_reinitialize_M9P() 2179 OUTPLL(pllSSPLL_CNTL, tmp); radeon_reinitialize_M9P() 2181 tmp &= ~1; radeon_reinitialize_M9P() 2182 OUTPLL(pllSSPLL_CNTL, tmp); radeon_reinitialize_M9P() 2184 tmp |= 3; radeon_reinitialize_M9P() 2185 OUTPLL(pllSSPLL_CNTL, tmp); radeon_reinitialize_M9P() 2215 u32 tmp, tmp2; 2252 tmp = INPLL(pllVCLK_ECP_CNTL); 2253 OUTPLL(pllVCLK_ECP_CNTL, tmp); 2254 tmp = INPLL(pllPIXCLKS_CNTL); 2255 OUTPLL(pllPIXCLKS_CNTL, tmp); 2269 tmp = INPLL(M_SPLL_REF_FB_DIV); 2270 OUTPLL(M_SPLL_REF_FB_DIV, tmp); 2271 tmp = INPLL(M_SPLL_REF_FB_DIV); 2272 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc); 2275 tmp = INPLL(MPLL_CNTL); 2278 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); 2281 tmp = INPLL(M_SPLL_REF_FB_DIV); 2282 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900); 2284 tmp = INPLL(MPLL_CNTL); 2285 OUTPLL(MPLL_CNTL, tmp & ~0x2); 2287 tmp = INPLL(MPLL_CNTL); 2288 OUTPLL(MPLL_CNTL, tmp & ~0x1); 2298 tmp = INPLL(SPLL_CNTL); 2301 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); 2304 tmp = INPLL(M_SPLL_REF_FB_DIV); 2305 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000); 2307 tmp = INPLL(SPLL_CNTL); 2308 OUTPLL(SPLL_CNTL, tmp & ~0x1); 2310 tmp = INPLL(SPLL_CNTL); 2311 OUTPLL(SPLL_CNTL, tmp & ~0x2); 2314 tmp = INPLL(SCLK_CNTL); 2315 OUTPLL(SCLK_CNTL, tmp | 2); 2377 tmp = INREG(FP_GEN_CNTL); 2378 tmp |= FP_CRTC_DONT_SHADOW_HEND | FP_CRTC_DONT_SHADOW_VPAR | 0x200; 2379 OUTREG(FP_GEN_CNTL, tmp); 2381 tmp = INREG(DISP_OUTPUT_CNTL); 2382 tmp &= ~0x400; 2383 OUTREG(DISP_OUTPUT_CNTL, tmp); 2389 tmp = INPLL(MCLK_MISC); 2390 tmp |= MCLK_MISC__MC_MCLK_DYN_ENABLE | MCLK_MISC__IO_MCLK_DYN_ENABLE; 2391 OUTPLL(MCLK_MISC, tmp); 2393 tmp = INPLL(SCLK_CNTL); 2394 OUTPLL(SCLK_CNTL, tmp); 2401 tmp = INPLL(VCLK_ECP_CNTL); 2402 OUTPLL(VCLK_ECP_CNTL, tmp); 2404 tmp = INPLL(PPLL_CNTL); 2405 OUTPLL(PPLL_CNTL, tmp); 2409 tmp = INREG(FP_GEN_CNTL); 2411 tmp |= 2; 2412 OUTREG(FP_GEN_CNTL, tmp); 2414 OUTREG(FP_GEN_CNTL, tmp); 2420 tmp = INREG(CRTC_MORE_CNTL); 2421 OUTREG(CRTC_MORE_CNTL, tmp); 2448 tmp = INPLL(PPLL_REF_DIV); 2449 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div; 2450 OUTPLL(PPLL_REF_DIV, tmp); 2458 tmp = INREG(CLOCK_CNTL_INDEX); 2460 OUTREG(CLOCK_CNTL_INDEX, tmp & 0xff); 2466 tmp = INPLL(PPLL_CNTL); 2467 OUTPLL(PPLL_CNTL, tmp & ~0x2); 2469 tmp = INPLL(PPLL_CNTL); 2470 OUTPLL(PPLL_CNTL, tmp & ~0x1); 2473 tmp = INPLL(VCLK_ECP_CNTL); 2474 OUTPLL(VCLK_ECP_CNTL, tmp | 3); 2477 tmp = INPLL(VCLK_ECP_CNTL); 2478 OUTPLL(VCLK_ECP_CNTL, tmp); 2493 tmp = INREG(TMDS_TRANSMITTER_CNTL); 2495 tmp |= TMDS_PLL_EN; 2496 OUTREG(TMDS_TRANSMITTER_CNTL, tmp); 2498 tmp &= ~TMDS_PLLRST; 2499 OUTREG(TMDS_TRANSMITTER_CNTL, tmp); 2538 u32 tmp; radeon_set_suspend() local 2578 tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET radeon_set_suspend() 2580 OUTPLL( pllMDLL_CKO, tmp ); radeon_set_suspend()
/linux-4.4.14/drivers/net/wireless/b43/
H A D	phy_common.c	347 u32 tmp; b43_phy_put_into_reset() local 352 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); b43_phy_put_into_reset() 353 tmp &= ~B43_BCMA_IOCTL_GMODE; b43_phy_put_into_reset() 354 tmp |= B43_BCMA_IOCTL_PHY_RESET; b43_phy_put_into_reset() 355 tmp |= BCMA_IOCTL_FGC; b43_phy_put_into_reset() 356 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); b43_phy_put_into_reset() 359 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); b43_phy_put_into_reset() 360 tmp &= ~BCMA_IOCTL_FGC; b43_phy_put_into_reset() 361 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); b43_phy_put_into_reset() 367 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); b43_phy_put_into_reset() 368 tmp &= ~B43_TMSLOW_GMODE; b43_phy_put_into_reset() 369 tmp |= B43_TMSLOW_PHYRESET; b43_phy_put_into_reset() 370 tmp |= SSB_TMSLOW_FGC; b43_phy_put_into_reset() 371 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); b43_phy_put_into_reset() 374 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); b43_phy_put_into_reset() 375 tmp &= ~SSB_TMSLOW_FGC; b43_phy_put_into_reset() 376 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); b43_phy_put_into_reset() 386 u32 tmp; b43_phy_take_out_of_reset() local 392 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); b43_phy_take_out_of_reset() 393 tmp &= ~B43_BCMA_IOCTL_PHY_RESET; b43_phy_take_out_of_reset() 394 tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN; b43_phy_take_out_of_reset() 395 tmp |= BCMA_IOCTL_FGC; b43_phy_take_out_of_reset() 396 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); b43_phy_take_out_of_reset() 400 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); b43_phy_take_out_of_reset() 401 tmp &= ~BCMA_IOCTL_FGC; b43_phy_take_out_of_reset() 402 tmp |= B43_BCMA_IOCTL_PHY_CLKEN; b43_phy_take_out_of_reset() 403 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); b43_phy_take_out_of_reset() 410 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); b43_phy_take_out_of_reset() 411 tmp &= ~B43_TMSLOW_PHYRESET; b43_phy_take_out_of_reset() 412 tmp &= ~B43_TMSLOW_PHYCLKEN; b43_phy_take_out_of_reset() 413 tmp |= SSB_TMSLOW_FGC; b43_phy_take_out_of_reset() 414 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); b43_phy_take_out_of_reset() 418 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); b43_phy_take_out_of_reset() 419 tmp &= ~SSB_TMSLOW_FGC; b43_phy_take_out_of_reset() 420 tmp |= B43_TMSLOW_PHYCLKEN; b43_phy_take_out_of_reset() 421 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); b43_phy_take_out_of_reset() 528 u32 tmp; b43_phy_shm_tssi_read() local 530 tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset); b43_phy_shm_tssi_read() 531 a = tmp & 0xFF; b43_phy_shm_tssi_read() 532 b = (tmp >> 8) & 0xFF; b43_phy_shm_tssi_read() 533 c = (tmp >> 16) & 0xFF; b43_phy_shm_tssi_read() 534 d = (tmp >> 24) & 0xFF; b43_phy_shm_tssi_read() 541 tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) | b43_phy_shm_tssi_read() 543 b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp); b43_phy_shm_tssi_read() 578 u32 tmp; b43_phy_force_clock() local 587 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); b43_phy_force_clock() 589 tmp |= BCMA_IOCTL_FGC; b43_phy_force_clock() 591 tmp &= ~BCMA_IOCTL_FGC; b43_phy_force_clock() 592 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); b43_phy_force_clock() 597 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); b43_phy_force_clock() 599 tmp |= SSB_TMSLOW_FGC; b43_phy_force_clock() 601 tmp &= ~SSB_TMSLOW_FGC; b43_phy_force_clock() 602 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); b43_phy_force_clock() 617 s32 tmp; b43_cordic() local 637 tmp = ret.i - (ret.q >> i); b43_cordic() 639 ret.i = tmp; b43_cordic() 642 tmp = ret.i + (ret.q >> i); b43_cordic() 644 ret.i = tmp; b43_cordic()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A D	nv44.c	42 u32 tmp[4]; nv44_vm_fill() local 44 tmp[0] = nvkm_ro32(pgt, base + 0x0); nv44_vm_fill() 45 tmp[1] = nvkm_ro32(pgt, base + 0x4); nv44_vm_fill() 46 tmp[2] = nvkm_ro32(pgt, base + 0x8); nv44_vm_fill() 47 tmp[3] = nvkm_ro32(pgt, base + 0xc); nv44_vm_fill() 53 tmp[0] &= ~0x07ffffff; nv44_vm_fill() 54 tmp[0] |= addr; nv44_vm_fill() 57 tmp[0] &= ~0xf8000000; nv44_vm_fill() 58 tmp[0] |= addr << 27; nv44_vm_fill() 59 tmp[1] &= ~0x003fffff; nv44_vm_fill() 60 tmp[1] |= addr >> 5; nv44_vm_fill() 63 tmp[1] &= ~0xffc00000; nv44_vm_fill() 64 tmp[1] |= addr << 22; nv44_vm_fill() 65 tmp[2] &= ~0x0001ffff; nv44_vm_fill() 66 tmp[2] |= addr >> 10; nv44_vm_fill() 69 tmp[2] &= ~0xfffe0000; nv44_vm_fill() 70 tmp[2] |= addr << 17; nv44_vm_fill() 71 tmp[3] &= ~0x00000fff; nv44_vm_fill() 72 tmp[3] |= addr >> 15; nv44_vm_fill() 77 nvkm_wo32(pgt, base + 0x0, tmp[0]); nv44_vm_fill() 78 nvkm_wo32(pgt, base + 0x4, tmp[1]); nv44_vm_fill() 79 nvkm_wo32(pgt, base + 0x8, tmp[2]); nv44_vm_fill() 80 nvkm_wo32(pgt, base + 0xc, tmp[3] | 0x40000000); nv44_vm_fill() 88 u32 tmp[4]; nv44_vm_map_sg() local 103 tmp[i] = *list++ >> 12; nv44_vm_map_sg() 104 nvkm_wo32(pgt, pte++ * 4, tmp[0] >> 0 | tmp[1] << 27); nv44_vm_map_sg() 105 nvkm_wo32(pgt, pte++ * 4, tmp[1] >> 5 | tmp[2] << 22); nv44_vm_map_sg() 106 nvkm_wo32(pgt, pte++ * 4, tmp[2] >> 10 | tmp[3] << 17); nv44_vm_map_sg() 107 nvkm_wo32(pgt, pte++ * 4, tmp[3] >> 15 | 0x40000000); nv44_vm_map_sg()
/linux-4.4.14/arch/c6x/include/asm/
H A D	cmpxchg.h	21 unsigned int tmp; __xchg() local 28 tmp = 0; __xchg() 29 tmp = *((unsigned char *) ptr); __xchg() 33 tmp = 0; __xchg() 34 tmp = *((unsigned short *) ptr); __xchg() 38 tmp = 0; __xchg() 39 tmp = *((unsigned int *) ptr); __xchg() 44 return tmp; __xchg()
/linux-4.4.14/arch/metag/include/asm/
H A D	spinlock_lnkget.h	26 int tmp; arch_spin_lock() local 37 : "=&d" (tmp) arch_spin_lock() 47 int tmp; arch_spin_trylock() local 59 : "=&d" (tmp) arch_spin_trylock() 65 return tmp; arch_spin_trylock() 88 int tmp; arch_write_lock() local 99 : "=&d" (tmp) arch_write_lock() 108 int tmp; arch_write_trylock() local 120 : "=&d" (tmp) arch_write_trylock() 126 return tmp; arch_write_trylock() 168 int tmp; arch_read_lock() local 178 : "=&d" (tmp) arch_read_lock() 187 int tmp; arch_read_unlock() local 198 : "=&d" (tmp) arch_read_unlock() 205 int tmp; arch_read_trylock() local 218 : "=&d" (tmp) arch_read_trylock() 224 return tmp; arch_read_trylock() 230 int tmp; arch_read_can_lock() local 236 : "=&d" (tmp) arch_read_can_lock() 239 return tmp; arch_read_can_lock()
/linux-4.4.14/arch/arm/mach-s3c64xx/
H A D	cpuidle.c	30 unsigned long tmp; s3c64xx_enter_idle() local 33 tmp = __raw_readl(S3C64XX_PWR_CFG); s3c64xx_enter_idle() 34 tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK; s3c64xx_enter_idle() 35 tmp |= S3C64XX_PWRCFG_CFG_WFI_IDLE; s3c64xx_enter_idle() 36 __raw_writel(tmp, S3C64XX_PWR_CFG); s3c64xx_enter_idle()
/linux-4.4.14/arch/arm/include/debug/
H A D	exynos.S	23 .macro addruart, rp, rv, tmp 24 mrc p15, 0, \tmp, c0, c0, 0 25 and \tmp, \tmp, #0xf0 26 teq \tmp, #0xf0 @@ A15
H A D	omap2plus.S	67 .macro addruart, rp, rv, tmp 74 sub \tmp, \rp, \rv @ make it effective 75 ldr \rp, [\tmp, #0] @ omap_uart_phys 76 ldr \rv, [\tmp, #4] @ omap_uart_virt 133 str \rp, [\tmp, #0] @ omap_uart_phys 135 str \rp, [\tmp, #4] @ omap_uart_virt 137 str \rp, [\tmp, #8] @ omap_uart_lsr 143 str \rp, [\tmp, #0] @ omap_uart_phys 146 str \rp, [\tmp, #4] @ omap_uart_virt 148 str \rp, [\tmp, #8] @ omap_uart_lsr 154 str \rp, [\tmp, #0] @ omap_uart_phys 157 str \rp, [\tmp, #4] @ omap_uart_virt 159 str \rp, [\tmp, #8] @ omap_uart_lsr 169 ldr \tmp, [\tmp, #8] @ omap_uart_lsr 170 add \rp, \rp, \tmp 171 add \rv, \rv, \tmp
H A D	efm32.S	19 .macro addruart, rx, tmp, tmp2 27 ldr \tmp, =(UARTn_CMD_TXEN) 28 str \tmp, [\rx, #UARTn_CMD]
/linux-4.4.14/net/bridge/netfilter/
H A D	ebt_mark.c	42 int tmp; ebt_mark_tg_check() local 44 tmp = info->target | ~EBT_VERDICT_BITS; ebt_mark_tg_check() 45 if (BASE_CHAIN && tmp == EBT_RETURN) ebt_mark_tg_check() 47 if (tmp < -NUM_STANDARD_TARGETS || tmp >= 0) ebt_mark_tg_check() 49 tmp = info->target & ~EBT_VERDICT_BITS; ebt_mark_tg_check() 50 if (tmp != MARK_SET_VALUE && tmp != MARK_OR_VALUE && ebt_mark_tg_check() 51 tmp != MARK_AND_VALUE && tmp != MARK_XOR_VALUE) ebt_mark_tg_check()
H A D	ebt_snat.c	48 int tmp; ebt_snat_tg_check() local 50 tmp = info->target | ~EBT_VERDICT_BITS; ebt_snat_tg_check() 51 if (BASE_CHAIN && tmp == EBT_RETURN) ebt_snat_tg_check() 54 if (tmp < -NUM_STANDARD_TARGETS || tmp >= 0) ebt_snat_tg_check() 56 tmp = info->target | EBT_VERDICT_BITS; ebt_snat_tg_check() 57 if ((tmp & ~NAT_ARP_BIT) != ~NAT_ARP_BIT) ebt_snat_tg_check()
/linux-4.4.14/arch/mips/sgi-ip22/
H A D	ip22-mc.c	57 unsigned int tmp = get_bank_config(i); probe_memory() local 58 if (!(tmp & SGIMC_MCONFIG_BVALID)) probe_memory() 61 bank[cnt].size = get_bank_size(tmp); probe_memory() 62 bank[cnt].addr = get_bank_addr(tmp); probe_memory() 108 u32 tmp; sgimc_init() local 125 tmp = sgimc->cpuctrl0; sgimc_init() 126 tmp &= ~SGIMC_CCTRL0_WDOG; sgimc_init() 127 sgimc->cpuctrl0 = tmp; sgimc_init() 140 tmp = sgimc->cpuctrl0; sgimc_init() 142 tmp |= SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM; sgimc_init() 144 tmp |= SGIMC_CCTRL0_R4KNOCHKPARR; sgimc_init() 145 sgimc->cpuctrl0 = tmp; sgimc_init() 150 tmp = sgimc->cpuctrl1; sgimc_init() 151 tmp &= ~0xf; sgimc_init() 152 tmp |= 0xd; sgimc_init() 153 sgimc->cpuctrl1 = tmp; sgimc_init() 179 tmp = sgimc->giopar & SGIMC_GIOPAR_GFX64; /* keep gfx 64bit settings */ sgimc_init() 180 tmp |= SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */ sgimc_init() 181 tmp |= SGIMC_GIOPAR_ONEBUS; /* Only one physical GIO bus exists */ sgimc_init() 186 tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC at 64bits */ sgimc_init() 187 tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp0 pipelines */ sgimc_init() 188 tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */ sgimc_init() 189 tmp |= SGIMC_GIOPAR_RTIMEEXP0; /* exp0 is realtime */ sgimc_init() 191 tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC 64bits */ sgimc_init() 192 tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp[01] pipelined */ sgimc_init() 193 tmp |= SGIMC_GIOPAR_PLINEEXP1; sgimc_init() 194 tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */ sgimc_init() 198 tmp |= SGIMC_GIOPAR_EISA64; /* MC talks to EISA at 64bits */ sgimc_init() 199 tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */ sgimc_init() 201 sgimc->giopar = tmp; /* poof */ sgimc_init()
H A D	ip22-gio.c	64 struct device *tmp; gio_dev_get() local 68 tmp = get_device(&dev->dev); gio_dev_get() 69 if (tmp) gio_dev_get() 70 return to_gio_device(tmp); gio_dev_get() 228 u32 tmp = sgimc->giopar; gio_set_master() local 232 tmp |= SGIMC_GIOPAR_MASTERGFX; gio_set_master() 235 tmp |= SGIMC_GIOPAR_MASTEREXP0; gio_set_master() 238 tmp |= SGIMC_GIOPAR_MASTEREXP1; gio_set_master() 241 sgimc->giopar = tmp; gio_set_master() 247 u32 tmp = sgimc->giopar; ip22_gio_set_64bit() local 251 tmp |= SGIMC_GIOPAR_GFX64; ip22_gio_set_64bit() 254 tmp |= SGIMC_GIOPAR_EXP064; ip22_gio_set_64bit() 257 tmp |= SGIMC_GIOPAR_EXP164; ip22_gio_set_64bit() 260 sgimc->giopar = tmp; ip22_gio_set_64bit() 310 u32 tmp; ip22_is_gr2() local 315 if (!get_dbe(tmp, ptr)) { ip22_is_gr2() 316 if (tmp == 0xdeadbeef) ip22_is_gr2() 327 u32 tmp; ip22_check_gio() local 333 tmp = 0x7f; ip22_check_gio() 335 if (!ip22_gio_id(addr, &tmp)) { ip22_check_gio() 341 if (ip22_gio_id(addr + NEWPORT_USTATUS_OFFS, &tmp)) ip22_check_gio() 342 tmp = 0x7e; ip22_check_gio() 344 tmp = 0; ip22_check_gio() 347 if (tmp) { ip22_check_gio() 348 id = GIO_ID(tmp); ip22_check_gio() 349 if (tmp & GIO_32BIT_ID) { ip22_check_gio() 350 if (tmp & GIO_64BIT_IFACE) ip22_check_gio()
/linux-4.4.14/drivers/video/fbdev/mmp/hw/
H A D	mmp_ctrl.c	46 u32 isr, imask, tmp; ctrl_handle_irq() local 53 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR); ctrl_handle_irq() 54 if (tmp & isr) ctrl_handle_irq() 134 u32 tmp; dmafetch_set_fmt() local 136 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id)); dmafetch_set_fmt() 137 tmp &= ~dma_mask(overlay_is_vid(overlay)); dmafetch_set_fmt() 138 tmp |= fmt_to_reg(overlay, overlay->win.pix_fmt); dmafetch_set_fmt() 139 writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); dmafetch_set_fmt() 176 u32 tmp; dmafetch_onoff() local 180 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id)); dmafetch_onoff() 181 tmp &= ~mask; dmafetch_onoff() 182 tmp |= (on ? enable : 0); dmafetch_onoff() 183 writel(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); dmafetch_onoff() 189 u32 tmp; path_enabledisable() local 191 tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path)); path_enabledisable() 193 tmp &= ~SCLK_DISABLE; path_enabledisable() 195 tmp |= SCLK_DISABLE; path_enabledisable() 196 writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path)); path_enabledisable() 261 u32 total_x, total_y, vsync_ctrl, tmp, sclk_src, sclk_div, path_set_mode() local 271 tmp = readl_relaxed(ctrl_regs(path) + intf_ctrl(path->id)) & 0x1; path_set_mode() 272 tmp |= mode->vsync_invert ? 0 : 0x8; path_set_mode() 273 tmp |= mode->hsync_invert ? 0 : 0x4; path_set_mode() 274 tmp |= link_config & CFG_DUMBMODE_MASK; path_set_mode() 275 tmp |= CFG_DUMB_ENA(1); path_set_mode() 276 writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id)); path_set_mode() 279 tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) & path_set_mode() 281 tmp |= dsi_rbswap & CFG_INTFRBSWAP_MASK; path_set_mode() 282 writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id)); path_set_mode() 312 tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path)); path_set_mode() 313 tmp &= ~CLK_INT_DIV_MASK; path_set_mode() 314 tmp |= sclk_div; path_set_mode() 315 writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path)); path_set_mode() 329 u32 tmp, irq_mask; ctrl_set_default() local 335 tmp = readl_relaxed(ctrl->reg_base + LCD_TOP_CTRL); ctrl_set_default() 336 tmp |= 0xfff0; ctrl_set_default() 337 writel_relaxed(tmp, ctrl->reg_base + LCD_TOP_CTRL); ctrl_set_default() 343 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA); ctrl_set_default() 344 tmp &= ~irq_mask; ctrl_set_default() 345 tmp |= irq_mask; ctrl_set_default() 346 writel_relaxed(tmp, ctrl->reg_base + SPU_IRQ_ENA); ctrl_set_default() 352 u32 dma_ctrl1, mask, tmp, path_config; path_set_default() local 359 tmp = readl_relaxed(ctrl_regs(path) + SPU_IOPAD_CONTROL); path_set_default() 360 tmp &= ~mask; path_set_default() 361 tmp |= path_config; path_set_default() 362 writel_relaxed(tmp, ctrl_regs(path) + SPU_IOPAD_CONTROL); path_set_default() 366 tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path)); path_set_default() 367 tmp &= ~SCLK_SRC_SEL_MASK; path_set_default() 368 tmp |= path_config; path_set_default() 369 writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path)); path_set_default() 392 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id)); path_set_default() 393 tmp |= mask; path_set_default() 395 tmp &= ~CFG_ARBFAST_ENA(1); path_set_default() 396 writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); path_set_default()
H A D	mmp_spi.c	46 u32 tmp; lcd_spi_write() local 68 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); lcd_spi_write() 69 tmp &= ~CFG_SPI_START_MASK; lcd_spi_write() 70 tmp |= CFG_SPI_START(1); lcd_spi_write() 71 writel(tmp, reg_base + LCD_SPU_SPI_CTRL); lcd_spi_write() 84 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); lcd_spi_write() 85 tmp &= ~CFG_SPI_START_MASK; lcd_spi_write() 86 tmp |= CFG_SPI_START(0); lcd_spi_write() 87 writel_relaxed(tmp, reg_base + LCD_SPU_SPI_CTRL); lcd_spi_write() 98 u32 tmp; lcd_spi_setup() local 100 tmp = CFG_SCLKCNT(16) | lcd_spi_setup() 104 writel(tmp, reg_base + LCD_SPU_SPI_CTRL); lcd_spi_setup() 111 tmp = readl_relaxed(reg_base + SPU_IOPAD_CONTROL); lcd_spi_setup() 112 if ((tmp & CFG_IOPADMODE_MASK) != IOPAD_DUMB18SPI) lcd_spi_setup() 114 (tmp & ~CFG_IOPADMODE_MASK), lcd_spi_setup()
/linux-4.4.14/block/partitions/
H A D	amiga.c	75 char tmp[7 + 10 + 1 + 1]; amiga_partition() local 78 snprintf(tmp, sizeof(tmp), " RDSK (%d)", blksize * 512); amiga_partition() 79 strlcat(state->pp_buf, tmp, PAGE_SIZE); amiga_partition() 117 char tmp[42]; amiga_partition() local 122 snprintf(tmp, sizeof(tmp), " (%c%c%c^%c)", amiga_partition() 126 snprintf(tmp, sizeof(tmp), " (%c%c%c%c)", amiga_partition() 129 strlcat(state->pp_buf, tmp, PAGE_SIZE); amiga_partition() 130 snprintf(tmp, sizeof(tmp), "(res %d spb %d)", amiga_partition() 133 strlcat(state->pp_buf, tmp, PAGE_SIZE); amiga_partition()
H A D	sysv68.c	57 char tmp[64]; sysv68_partition() local 77 snprintf(tmp, sizeof(tmp), "sysV68: %s(s%u)", state->name, slices); sysv68_partition() 78 strlcat(state->pp_buf, tmp, PAGE_SIZE); sysv68_partition() 87 snprintf(tmp, sizeof(tmp), "(s%u)", i); sysv68_partition() 88 strlcat(state->pp_buf, tmp, PAGE_SIZE); sysv68_partition()
H A D	check.h	44 char tmp[1 + BDEVNAME_SIZE + 10 + 1]; put_partition() local 48 snprintf(tmp, sizeof(tmp), " %s%d", p->name, n); put_partition() 49 strlcat(p->pp_buf, tmp, PAGE_SIZE); put_partition()
/linux-4.4.14/drivers/clk/mmp/
H A D	clk-gate.c	32 u32 tmp; mmp_clk_gate_enable() local 37 tmp = readl(gate->reg); mmp_clk_gate_enable() 38 tmp &= ~gate->mask; mmp_clk_gate_enable() 39 tmp |= gate->val_enable; mmp_clk_gate_enable() 40 writel(tmp, gate->reg); mmp_clk_gate_enable() 58 u32 tmp; mmp_clk_gate_disable() local 63 tmp = readl(gate->reg); mmp_clk_gate_disable() 64 tmp &= ~gate->mask; mmp_clk_gate_disable() 65 tmp |= gate->val_disable; mmp_clk_gate_disable() 66 writel(tmp, gate->reg); mmp_clk_gate_disable() 76 u32 tmp; mmp_clk_gate_is_enabled() local 81 tmp = readl(gate->reg); mmp_clk_gate_is_enabled() 86 return (tmp & gate->mask) == gate->val_enable; mmp_clk_gate_is_enabled()
/linux-4.4.14/arch/mn10300/unit-asb2364/include/unit/
H A D	timex.h	46 u16 tmp; stop_jiffies_counter() local 48 tmp = TMTMD; stop_jiffies_counter() 53 u32 tmp; reload_jiffies_counter() local 56 tmp = TMTBR; reload_jiffies_counter() 60 tmp = TMTMD; reload_jiffies_counter() 76 u8 tmp; stop_jiffies_counter1() local 79 tmp = TM4MD; stop_jiffies_counter1() 80 tmp = TM5MD; stop_jiffies_counter1() 85 u32 tmp; reload_jiffies_counter1() local 88 tmp = TM45BR; reload_jiffies_counter1() 91 tmp = TM4MD; reload_jiffies_counter1() 95 tmp = TM5MD; reload_jiffies_counter1() 98 tmp = TM4MD; reload_jiffies_counter1()
/linux-4.4.14/arch/powerpc/platforms/pseries/
H A D	reconfig.c	122 char *tmp; parse_next_property() local 126 tmp = strchr(buf, ' '); parse_next_property() 127 if (!tmp) { parse_next_property() 132 *tmp = '\0'; parse_next_property() 134 if (++tmp >= end) { parse_next_property() 142 *length = simple_strtoul(tmp, &tmp, 10); parse_next_property() 148 if (*tmp != ' ' || ++tmp >= end) { parse_next_property() 155 *value = tmp; parse_next_property() 156 tmp += *length; parse_next_property() 157 if (tmp > end) { parse_next_property() 162 else if (tmp < end && *tmp != ' ' && *tmp != '\0') { parse_next_property() 167 tmp++; parse_next_property() 170 return tmp; parse_next_property() 220 /* rv = build_prop_list(tmp, bufsize - (tmp - buf), &proplist); */ do_add_node() 305 char *tmp; do_remove_property() local 312 tmp = strchr(buf,' '); do_remove_property() 313 if (tmp) do_remove_property() 314 *tmp = '\0'; do_remove_property() 371 char *tmp; ofdt_write() local 384 tmp = strchr(kbuf, ' '); ofdt_write() 385 if (!tmp) { ofdt_write() 389 *tmp = '\0'; ofdt_write() 390 tmp++; ofdt_write() 393 rv = do_add_node(tmp, count - (tmp - kbuf)); ofdt_write() 395 rv = do_remove_node(tmp); ofdt_write() 397 rv = do_add_property(tmp, count - (tmp - kbuf)); ofdt_write() 399 rv = do_remove_property(tmp, count - (tmp - kbuf)); ofdt_write() 401 rv = do_update_property(tmp, count - (tmp - kbuf)); ofdt_write()
/linux-4.4.14/arch/arc/include/uapi/asm/
H A D	swab.h	26 unsigned int tmp = x; \ 29 : "=r" (tmp) \ 30 : "r" (tmp)); \ 31 tmp; \ 70 __tmp = __in << 8 | __in >> 24; /* ror tmp,in,24 */ \ 81 unsigned int tmp = x; \ 85 : "=r" (tmp) \ 86 : "r" (tmp)); \ 87 tmp; \
/linux-4.4.14/arch/arm/mach-s3c24xx/
H A D	pm-s3c2412.c	41 unsigned long tmp; s3c2412_cpu_suspend() local 45 tmp = __raw_readl(S3C2412_PWRCFG); s3c2412_cpu_suspend() 46 tmp |= S3C2412_PWRCFG_STANDBYWFI_SLEEP; s3c2412_cpu_suspend() 47 __raw_writel(tmp, S3C2412_PWRCFG); s3c2412_cpu_suspend() 118 unsigned long tmp; s3c2412_pm_resume() local 120 tmp = __raw_readl(S3C2412_PWRCFG); s3c2412_pm_resume() 121 tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK; s3c2412_pm_resume() 122 tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE; s3c2412_pm_resume() 123 __raw_writel(tmp, S3C2412_PWRCFG); s3c2412_pm_resume()
H A D	simtec-audio.c	33 unsigned int tmp; simtec_audio_startup_lrroute() local 38 tmp = __raw_readb(BAST_VA_CTRL1); simtec_audio_startup_lrroute() 39 tmp &= ~BAST_CPLD_CTRL1_LRMASK; simtec_audio_startup_lrroute() 40 tmp |= BAST_CPLD_CTRL1_LRCDAC; simtec_audio_startup_lrroute() 41 __raw_writeb(tmp, BAST_VA_CTRL1); simtec_audio_startup_lrroute()
/linux-4.4.14/drivers/ssb/
H A D	driver_chipcommon.c	47 u32 tmp; ssb_chipco_set_clockmode() local 74 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); ssb_chipco_set_clockmode() 75 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW; ssb_chipco_set_clockmode() 76 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); ssb_chipco_set_clockmode() 81 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); ssb_chipco_set_clockmode() 82 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; ssb_chipco_set_clockmode() 83 tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL; ssb_chipco_set_clockmode() 84 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); ssb_chipco_set_clockmode() 94 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); ssb_chipco_set_clockmode() 95 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; ssb_chipco_set_clockmode() 96 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL; ssb_chipco_set_clockmode() 97 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL; ssb_chipco_set_clockmode() 98 if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != ssb_chipco_set_clockmode() 100 tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL; ssb_chipco_set_clockmode() 101 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); ssb_chipco_set_clockmode() 105 if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL) ssb_chipco_set_clockmode() 122 u32 uninitialized_var(tmp); chipco_pctl_get_slowclksrc() 129 pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp); chipco_pctl_get_slowclksrc() 130 if (tmp & 0x10) chipco_pctl_get_slowclksrc() 136 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); chipco_pctl_get_slowclksrc() 137 tmp &= 0x7; chipco_pctl_get_slowclksrc() 138 if (tmp == 0) chipco_pctl_get_slowclksrc() 140 if (tmp == 1) chipco_pctl_get_slowclksrc() 142 if (tmp == 2) chipco_pctl_get_slowclksrc() 155 u32 tmp; chipco_pctl_clockfreqlimit() local 175 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); chipco_pctl_clockfreqlimit() 176 divisor = (tmp >> 16) + 1; chipco_pctl_clockfreqlimit() 181 tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL); chipco_pctl_clockfreqlimit() 182 divisor = (tmp >> 16) + 1; chipco_pctl_clockfreqlimit() 263 unsigned int tmp; calc_fast_powerup_delay() local 279 tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq; calc_fast_powerup_delay() 280 SSB_WARN_ON(tmp & ~0xFFFF); calc_fast_powerup_delay() 282 cc->fast_pwrup_delay = tmp; calc_fast_powerup_delay() 439 u32 tmp; ssb_chipco_timing_init() local 443 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ ssb_chipco_timing_init() 444 tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */ ssb_chipco_timing_init() 445 tmp |= DIV_ROUND_UP(240, ns); /* Waitcount-0 = 240ns */ ssb_chipco_timing_init() 446 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */ ssb_chipco_timing_init() 449 tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */ ssb_chipco_timing_init() 450 tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */ ssb_chipco_timing_init() 451 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120nS */ ssb_chipco_timing_init() 454 chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp); ssb_chipco_timing_init() 458 chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp); ssb_chipco_timing_init() 462 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ ssb_chipco_timing_init() 463 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */ ssb_chipco_timing_init() 464 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */ ssb_chipco_timing_init() 465 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120ns */ ssb_chipco_timing_init() 466 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */ ssb_chipco_timing_init()
/linux-4.4.14/fs/xfs/libxfs/
H A D	xfs_bit.c	53 uint tmp; xfs_contig_bits() local 61 tmp = *p++; xfs_contig_bits() 63 tmp |= (~0U >> (NBWORD-start_bit)); xfs_contig_bits() 64 if (tmp != ~0U) xfs_contig_bits() 70 if ((tmp = *p++) != ~0U) xfs_contig_bits() 77 return result + ffz(tmp) - start_bit; xfs_contig_bits() 92 uint tmp; xfs_next_bit() local 101 tmp = *p++; xfs_next_bit() 103 tmp &= (~0U << start_bit); xfs_next_bit() 104 if (tmp != 0U) xfs_next_bit() 110 if ((tmp = *p++) != 0U) xfs_next_bit() 117 return result + ffs(tmp) - 1; xfs_next_bit()
/linux-4.4.14/drivers/video/fbdev/
H A D	atafb_utils.h	92 long tmp; fb_memclear() local 109 : "=a" (s), "=d" (count), "=d" (tmp) fb_memclear() 157 long tmp; fb_memmove() local 175 : "=a" (d), "=a" (s), "=d" (count), "=d" (tmp) fb_memmove() 189 long tmp; fb_memmove() local 208 : "=a" (d), "=a" (s), "=d" (count), "=d" (tmp) fb_memmove() 281 u32 tmp = m[0]; fill8_col() local 282 dst[0] = tmp; fill8_col() 283 dst[2] = (tmp >>= 8); fill8_col() 285 dst[4] = (tmp >>= 8); fill8_col() 286 dst[6] = tmp >> 8; fill8_col() 289 tmp = m[1]; fill8_col() 290 dst[8] = tmp; fill8_col() 291 dst[10] = (tmp >>= 8); fill8_col() 292 dst[12] = (tmp >>= 8); fill8_col() 293 dst[14] = tmp >> 8; fill8_col() 302 u32 fgm[2], bgm[2], tmp; fill8_2col() local 310 tmp = (mask & fgm[0]) ^ bgm[0]; fill8_2col() 311 dst[0] = tmp; fill8_2col() 312 dst[2] = (tmp >>= 8); fill8_2col() 314 dst[4] = (tmp >>= 8); fill8_2col() 315 dst[6] = tmp >> 8; fill8_2col() 318 tmp = (mask & fgm[1]) ^ bgm[1]; fill8_2col() 319 dst[8] = tmp; fill8_2col() 320 dst[10] = (tmp >>= 8); fill8_2col() 321 dst[12] = (tmp >>= 8); fill8_2col() 322 dst[14] = tmp >> 8; fill8_2col()
/linux-4.4.14/arch/mips/bcm63xx/
H A D	cpu.c	129 unsigned int tmp, mips_pll_fcvo; detect_cpu_clock() local 131 tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG); detect_cpu_clock() 132 mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK) detect_cpu_clock() 164 unsigned int tmp, n1, n2, m1; detect_cpu_clock() local 167 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG); detect_cpu_clock() 168 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT; detect_cpu_clock() 169 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT; detect_cpu_clock() 170 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT; detect_cpu_clock() 179 unsigned int tmp, n1, n2, m1; detect_cpu_clock() local 182 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG); detect_cpu_clock() 183 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT; detect_cpu_clock() 184 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT; detect_cpu_clock() 185 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT; detect_cpu_clock() 191 unsigned int tmp, mips_pll_fcvo; detect_cpu_clock() local 193 tmp = bcm_misc_readl(MISC_STRAPBUS_6362_REG); detect_cpu_clock() 194 mips_pll_fcvo = (tmp & STRAPBUS_6362_FCVO_MASK) detect_cpu_clock() 227 unsigned int tmp, p1, p2, ndiv, m1; detect_cpu_clock() local 230 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG); detect_cpu_clock() 232 p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >> detect_cpu_clock() 235 p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >> detect_cpu_clock() 238 ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >> detect_cpu_clock() 241 tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG); detect_cpu_clock() 242 m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >> detect_cpu_clock() 296 unsigned int tmp; bcm63xx_cpu_init() local 334 tmp = bcm_readl(chipid_reg); bcm63xx_cpu_init() 335 bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; bcm63xx_cpu_init() 336 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; bcm63xx_cpu_init()
/linux-4.4.14/drivers/gpu/drm/sti/
H A D	sti_vtg.c	152 u32 tmp; vtg_set_mode() local 167 tmp = (mode->hsync_end - mode->hsync_start + HDMI_DELAY) << 16; vtg_set_mode() 168 tmp |= HDMI_DELAY; vtg_set_mode() 169 writel(tmp, vtg->regs + VTG_H_HD_1); vtg_set_mode() 171 tmp = (mode->vsync_end - mode->vsync_start + 1) << 16; vtg_set_mode() 172 tmp |= 1; vtg_set_mode() 173 writel(tmp, vtg->regs + VTG_TOP_V_VD_1); vtg_set_mode() 174 writel(tmp, vtg->regs + VTG_BOT_V_VD_1); vtg_set_mode() 176 tmp = HDMI_DELAY << 16; vtg_set_mode() 177 tmp |= HDMI_DELAY; vtg_set_mode() 178 writel(tmp, vtg->regs + VTG_TOP_V_HD_1); vtg_set_mode() 179 writel(tmp, vtg->regs + VTG_BOT_V_HD_1); vtg_set_mode() 182 tmp = (mode->hsync_end - mode->hsync_start) << 16; vtg_set_mode() 183 writel(tmp, vtg->regs + VTG_H_HD_2); vtg_set_mode() 185 tmp = (mode->vsync_end - mode->vsync_start + 1) << 16; vtg_set_mode() 186 tmp |= 1; vtg_set_mode() 187 writel(tmp, vtg->regs + VTG_TOP_V_VD_2); vtg_set_mode() 188 writel(tmp, vtg->regs + VTG_BOT_V_VD_2); vtg_set_mode() 193 tmp = (mode->hsync_end - mode->hsync_start + AWG_DELAY_HD) << 16; vtg_set_mode() 194 tmp |= mode->htotal + AWG_DELAY_HD; vtg_set_mode() 195 writel(tmp, vtg->regs + VTG_H_HD_3); vtg_set_mode() 197 tmp = (mode->vsync_end - mode->vsync_start) << 16; vtg_set_mode() 198 tmp |= mode->vtotal; vtg_set_mode() 199 writel(tmp, vtg->regs + VTG_TOP_V_VD_3); vtg_set_mode() 200 writel(tmp, vtg->regs + VTG_BOT_V_VD_3); vtg_set_mode() 202 tmp = (mode->htotal + AWG_DELAY_HD) << 16; vtg_set_mode() 203 tmp |= mode->htotal + AWG_DELAY_HD; vtg_set_mode() 204 writel(tmp, vtg->regs + VTG_TOP_V_HD_3); vtg_set_mode() 205 writel(tmp, vtg->regs + VTG_BOT_V_HD_3); vtg_set_mode() 208 tmp = (mode->hsync_end - mode->hsync_start) << 16; vtg_set_mode() 209 writel(tmp, vtg->regs + VTG_H_HD_4); vtg_set_mode() 211 tmp = (mode->vsync_end - mode->vsync_start + 1) << 16; vtg_set_mode() 212 tmp |= 1; vtg_set_mode() 213 writel(tmp, vtg->regs + VTG_TOP_V_VD_4); vtg_set_mode() 214 writel(tmp, vtg->regs + VTG_BOT_V_VD_4); vtg_set_mode()
/linux-4.4.14/arch/mips/include/asm/
H A D	spinlock.h	65 int tmp; arch_spin_lock() local 99 [ticket] "=&r" (tmp), arch_spin_lock() 132 [ticket] "=&r" (tmp), arch_spin_lock() 150 int tmp, tmp2, tmp3; arch_spin_trylock() local 173 [ticket] "=&r" (tmp), arch_spin_trylock() 197 [ticket] "=&r" (tmp), arch_spin_trylock() 205 return tmp; arch_spin_trylock() 231 unsigned int tmp; arch_read_lock() local 243 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) arch_read_lock() 253 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) arch_read_lock() 256 } while (unlikely(!tmp)); arch_read_lock() 264 unsigned int tmp; arch_read_unlock() local 274 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) arch_read_unlock() 283 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) arch_read_unlock() 286 } while (unlikely(!tmp)); arch_read_unlock() 292 unsigned int tmp; arch_write_lock() local 304 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) arch_write_lock() 314 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) arch_write_lock() 317 } while (unlikely(!tmp)); arch_write_lock() 337 unsigned int tmp; arch_read_trylock() local 354 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret) arch_read_trylock() 371 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret) arch_read_trylock() 381 unsigned int tmp; arch_write_trylock() local 398 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret) arch_write_trylock() 411 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), arch_write_trylock() 415 } while (unlikely(!tmp)); arch_write_trylock()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A D	g84.c	123 u32 tmp; g84_gr_tlb_flush() local 132 for (tmp = nvkm_rd32(device, 0x400380); tmp && idle; tmp >>= 3) { g84_gr_tlb_flush() 133 if ((tmp & 7) == 1) g84_gr_tlb_flush() 137 for (tmp = nvkm_rd32(device, 0x400384); tmp && idle; tmp >>= 3) { g84_gr_tlb_flush() 138 if ((tmp & 7) == 1) g84_gr_tlb_flush() 142 for (tmp = nvkm_rd32(device, 0x400388); tmp && idle; tmp >>= 3) { g84_gr_tlb_flush() 143 if ((tmp & 7) == 1) g84_gr_tlb_flush() 152 tmp = nvkm_rd32(device, 0x400700); g84_gr_tlb_flush() 153 nvkm_snprintbf(status, sizeof(status), nv50_gr_status, tmp); g84_gr_tlb_flush() 154 nvkm_error(subdev, "PGRAPH_STATUS %08x [%s]\n", tmp, status); g84_gr_tlb_flush()
/linux-4.4.14/arch/um/kernel/
H A D	Makefile	28 targets := config.c config.tmp 33 $(obj)/config.tmp: $(objtree)/.config FORCE 40 $(obj)/config.c: $(src)/config.c.in $(obj)/config.tmp FORCE 46 -e 'r $(obj)/config.tmp' \
/linux-4.4.14/arch/sh/kernel/
H A D	return_address.c	24 struct dwarf_frame *tmp; return_address() local 26 tmp = dwarf_unwind_stack(ra, frame); return_address() 27 if (!tmp) return_address() 33 frame = tmp; return_address()
H A D	io_trapped.c	186 unsigned long long tmp = 0; copy_word() local 190 tmp = __raw_readb(src_addr); copy_word() 193 tmp = __raw_readw(src_addr); copy_word() 196 tmp = __raw_readl(src_addr); copy_word() 199 tmp = __raw_readq(src_addr); copy_word() 205 __raw_writeb(tmp, dst_addr); copy_word() 208 __raw_writew(tmp, dst_addr); copy_word() 211 __raw_writel(tmp, dst_addr); copy_word() 214 __raw_writeq(tmp, dst_addr); copy_word() 218 return tmp; copy_word() 225 unsigned long long tmp; from_device() local 235 tmp = copy_word(src_addr, from_device() 240 pr_debug("trapped io read 0x%08lx -> 0x%08llx\n", src_addr, tmp); from_device() 248 unsigned long long tmp; to_device() local 258 tmp = copy_word((unsigned long)src, cnt, to_device() 262 pr_debug("trapped io write 0x%08lx -> 0x%08llx\n", dst_addr, tmp); to_device() 275 int tmp; handle_trapped_io() local 292 tmp = handle_unaligned_access(instruction, regs, handle_trapped_io() 295 return tmp == 0; handle_trapped_io()
/linux-4.4.14/arch/mn10300/kernel/
H A D	irq.c	44 u16 tmp; mn10300_cpupic_ack() local 48 tmp = GxICR(irq); mn10300_cpupic_ack() 56 u16 tmp; __mask_and_set_icr() local 59 tmp = GxICR(irq); __mask_and_set_icr() 60 GxICR(irq) = (tmp & mask) | set; __mask_and_set_icr() 61 tmp = GxICR(irq); __mask_and_set_icr() 75 u16 tmp; mn10300_cpupic_mask_ack() local 80 tmp = GxICR(irq); mn10300_cpupic_mask_ack() 81 GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT; mn10300_cpupic_mask_ack() 82 tmp = GxICR(irq); mn10300_cpupic_mask_ack() 85 tmp = GxICR(irq); mn10300_cpupic_mask_ack() 86 GxICR(irq) = (tmp & GxICR_LEVEL); mn10300_cpupic_mask_ack() 93 (tmp & (GxICR_LEVEL | GxICR_ENABLE)) | GxICR_DETECT; mn10300_cpupic_mask_ack() 94 tmp = CROSS_GxICR(irq, irq_affinity_online[irq]); mn10300_cpupic_mask_ack() 117 u16 tmp; mn10300_cpupic_unmask_clear() local 122 tmp = GxICR(irq); mn10300_cpupic_unmask_clear() 123 GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT; mn10300_cpupic_unmask_clear() 124 tmp = GxICR(irq); mn10300_cpupic_unmask_clear() 126 tmp = GxICR(irq); mn10300_cpupic_unmask_clear() 130 CROSS_GxICR(irq, irq_affinity_online[irq]) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT; mn10300_cpupic_unmask_clear() 131 tmp = CROSS_GxICR(irq, irq_affinity_online[irq]); mn10300_cpupic_unmask_clear() 334 u16 x, tmp; migrate_irqs() local 338 tmp = GxICR(irq); migrate_irqs() 345 tmp = CROSS_GxICR(irq, new); migrate_irqs() 351 tmp = CROSS_GxICR(irq, new); migrate_irqs()
H A D	gdb-io-ttysm.c	40 int tmp; gdbstub_io_init() local 68 tmp = *gdbstub_port->rx_icr; gdbstub_io_init() 86 tmp = *gdbstub_port->_control; gdbstub_io_init() 101 unsigned xdiv, tmp; gdbstub_io_set_baud() local 118 tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1; gdbstub_io_set_baud() 119 if (tmp > 0 && tmp <= 65535) gdbstub_io_set_baud() 123 tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1; gdbstub_io_set_baud() 124 if (tmp > 0 && tmp <= 65535) gdbstub_io_set_baud() 128 tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1; gdbstub_io_set_baud() 129 if (tmp > 0 && tmp <= 65535) gdbstub_io_set_baud() 136 tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1; gdbstub_io_set_baud() 137 if (tmp > 0 && tmp <= 255) gdbstub_io_set_baud() 141 tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1; gdbstub_io_set_baud() 142 if (tmp > 0 && tmp <= 255) gdbstub_io_set_baud() 146 tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1; gdbstub_io_set_baud() 147 if (tmp > 0 && tmp <= 255) gdbstub_io_set_baud()
H A D	mn10300-watchdog.c	51 irq_cpustat_t tmp[1]; check_watchdog() local 55 memcpy(tmp, irq_stat, sizeof(tmp)); check_watchdog() 60 if (nmi_count(0) - tmp[0].__nmi_count <= 5) { check_watchdog() 78 unsigned tmp; setup_watchdog() local 92 tmp = WDCTR; setup_watchdog() 94 tmp = __muldiv64u(1 << (16 + ctr * 2), 1000000, MN10300_WDCLK); setup_watchdog() 95 tmp = 1000000000 / tmp; setup_watchdog() 96 watchdog_hz = (tmp + 500) / 1000; setup_watchdog() 137 u8 wdt, tmp; watchdog_interrupt() local 141 tmp = WDCTR; watchdog_interrupt() 202 tmp = WDCTR; 204 tmp = WDCTR;
/linux-4.4.14/arch/arm/kvm/
H A D	mmio.c	34 } tmp; mmio_write_buf() local 38 tmp.byte = data; mmio_write_buf() 39 datap = &tmp.byte; mmio_write_buf() 42 tmp.hword = data; mmio_write_buf() 43 datap = &tmp.hword; mmio_write_buf() 46 tmp.word = data; mmio_write_buf() 47 datap = &tmp.word; mmio_write_buf() 50 tmp.dword = data; mmio_write_buf() 51 datap = &tmp.dword; mmio_write_buf() 65 } tmp; mmio_read_buf() local 72 memcpy(&tmp.hword, buf, len); mmio_read_buf() 73 data = tmp.hword; mmio_read_buf() 76 memcpy(&tmp.word, buf, len); mmio_read_buf() 77 data = tmp.word; mmio_read_buf() 80 memcpy(&tmp.dword, buf, len); mmio_read_buf() 81 data = tmp.dword; mmio_read_buf()
/linux-4.4.14/drivers/gpio/
H A D	gpio-spear-spics.c	67 u32 tmp; spics_set_value() local 70 tmp = readl_relaxed(spics->base + spics->perip_cfg); spics_set_value() 73 tmp &= ~(spics->cs_enable_mask << spics->cs_enable_shift); spics_set_value() 74 tmp |= offset << spics->cs_enable_shift; spics_set_value() 78 tmp &= ~(0x1 << spics->cs_value_bit); spics_set_value() 79 tmp |= value << spics->cs_value_bit; spics_set_value() 80 writel_relaxed(tmp, spics->base + spics->perip_cfg); spics_set_value() 99 u32 tmp; spics_request() local 102 tmp = readl_relaxed(spics->base + spics->perip_cfg); spics_request() 103 tmp |= 0x1 << spics->sw_enable_bit; spics_request() 104 tmp |= 0x1 << spics->cs_value_bit; spics_request() 105 writel_relaxed(tmp, spics->base + spics->perip_cfg); spics_request() 115 u32 tmp; spics_free() local 118 tmp = readl_relaxed(spics->base + spics->perip_cfg); spics_free() 119 tmp &= ~(0x1 << spics->sw_enable_bit); spics_free() 120 writel_relaxed(tmp, spics->base + spics->perip_cfg); spics_free()
/linux-4.4.14/drivers/staging/olpc_dcon/
H A D	olpc_dcon_xo_1_5.c	52 u_int8_t tmp; dcon_was_irq() local 55 tmp = inb(VX855_GPI_STATUS_CHG); dcon_was_irq() 56 return !!(tmp & BIT_GPIO12); dcon_was_irq() 88 unsigned char tmp; set_i2c_line() local 93 tmp = inb(0x3c5); set_i2c_line() 96 tmp |= 0x20; set_i2c_line() 98 tmp &= ~0x20; set_i2c_line() 101 tmp |= 0x10; set_i2c_line() 103 tmp &= ~0x10; set_i2c_line() 105 tmp |= 0x01; set_i2c_line() 108 outb(tmp, 0x3c5); set_i2c_line()
/linux-4.4.14/drivers/video/fbdev/via/
H A D	accel.c	58 u32 ge_cmd = 0, tmp, i; hw_bitblt_1() local 104 tmp = src_x | (src_y << 16); hw_bitblt_1() 105 writel(tmp, engine + 0x08); hw_bitblt_1() 113 tmp = dst_x | (dst_y << 16); hw_bitblt_1() 114 writel(tmp, engine + 0x0C); hw_bitblt_1() 121 tmp = (width - 1) | ((height - 1) << 16); hw_bitblt_1() 122 writel(tmp, engine + 0x10); hw_bitblt_1() 131 tmp = src_mem ? 0 : src_addr; hw_bitblt_1() 134 "address %X\n", tmp); hw_bitblt_1() 137 tmp >>= 3; hw_bitblt_1() 138 writel(tmp, engine + 0x30); hw_bitblt_1() 146 tmp = dst_addr >> 3; hw_bitblt_1() 147 writel(tmp, engine + 0x34); hw_bitblt_1() 150 tmp = 0; hw_bitblt_1() 152 tmp = src_pitch; hw_bitblt_1() 153 if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) { hw_bitblt_1() 155 tmp, dst_pitch); hw_bitblt_1() 158 tmp = VIA_PITCH_ENABLE | (tmp >> 3) | (dst_pitch << (16 - 3)); hw_bitblt_1() 159 writel(tmp, engine + 0x38); hw_bitblt_1() 177 tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) + hw_bitblt_1() 180 for (i = 0; i < tmp; i++) hw_bitblt_1() 191 u32 ge_cmd = 0, tmp, i; hw_bitblt_2() local 231 tmp = 0; hw_bitblt_2() 233 tmp = src_pitch; hw_bitblt_2() 234 if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) { hw_bitblt_2() 236 tmp, dst_pitch); hw_bitblt_2() 239 tmp = (tmp >> 3) | (dst_pitch << (16 - 3)); hw_bitblt_2() 240 writel(tmp, engine + 0x08); hw_bitblt_2() 247 tmp = (width - 1) | ((height - 1) << 16); hw_bitblt_2() 248 writel(tmp, engine + 0x0C); hw_bitblt_2() 255 tmp = dst_x | (dst_y << 16); hw_bitblt_2() 256 writel(tmp, engine + 0x10); hw_bitblt_2() 263 tmp = dst_addr >> 3; hw_bitblt_2() 264 writel(tmp, engine + 0x14); hw_bitblt_2() 273 tmp = src_x | (src_y << 16); hw_bitblt_2() 274 writel(tmp, engine + 0x18); hw_bitblt_2() 276 tmp = src_mem ? 0 : src_addr; hw_bitblt_2() 279 "address %X\n", tmp); hw_bitblt_2() 282 tmp >>= 3; hw_bitblt_2() 283 writel(tmp, engine + 0x1C); hw_bitblt_2() 309 tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) + hw_bitblt_2() 312 for (i = 0; i < tmp; i++) hw_bitblt_2()
H A D	via_aux_vt1621.c	37 u8 tmp; via_aux_vt1621_probe() local 39 if (!via_aux_read(&drv, 0x1B, &tmp, 1) || tmp != 0x02) via_aux_vt1621_probe()
/linux-4.4.14/drivers/infiniband/hw/qib/
H A D	qib_fs.c	227 char *tmp; qsfp_1_read() local 230 tmp = kmalloc(PAGE_SIZE, GFP_KERNEL); qsfp_1_read() 231 if (!tmp) qsfp_1_read() 234 ret = qib_qsfp_dump(dd->pport, tmp, PAGE_SIZE); qsfp_1_read() 236 ret = simple_read_from_buffer(buf, count, ppos, tmp, ret); qsfp_1_read() 237 kfree(tmp); qsfp_1_read() 248 char *tmp; qsfp_2_read() local 254 tmp = kmalloc(PAGE_SIZE, GFP_KERNEL); qsfp_2_read() 255 if (!tmp) qsfp_2_read() 258 ret = qib_qsfp_dump(dd->pport + 1, tmp, PAGE_SIZE); qsfp_2_read() 260 ret = simple_read_from_buffer(buf, count, ppos, tmp, ret); qsfp_2_read() 261 kfree(tmp); qsfp_2_read() 276 char *tmp; flash_read() local 293 tmp = kmalloc(count, GFP_KERNEL); flash_read() 294 if (!tmp) { flash_read() 300 if (qib_eeprom_read(dd, pos, tmp, count)) { flash_read() 306 if (copy_to_user(buf, tmp, count)) { flash_read() 315 kfree(tmp); flash_read() 327 char *tmp; flash_write() local 341 tmp = kmalloc(count, GFP_KERNEL); flash_write() 342 if (!tmp) { flash_write() 347 if (copy_from_user(tmp, buf, count)) { flash_write() 353 if (qib_eeprom_write(dd, pos, tmp, count)) { flash_write() 363 kfree(tmp); flash_write() 377 struct dentry *dir, *tmp; add_cntr_files() local 391 ret = create_file("counters", S_IFREG|S_IRUGO, dir, &tmp, add_cntr_files() 398 ret = create_file("counter_names", S_IFREG|S_IRUGO, dir, &tmp, add_cntr_files() 405 ret = create_file("portcounter_names", S_IFREG|S_IRUGO, dir, &tmp, add_cntr_files() 417 ret = create_file(fname, S_IFREG|S_IRUGO, dir, &tmp, add_cntr_files() 427 ret = create_file(fname, S_IFREG|S_IRUGO, dir, &tmp, add_cntr_files() 436 ret = create_file("flash", S_IFREG|S_IWUSR|S_IRUGO, dir, &tmp, add_cntr_files() 447 struct dentry *tmp; remove_file() local 450 tmp = lookup_one_len(name, parent, strlen(name)); remove_file() 452 if (IS_ERR(tmp)) { remove_file() 453 ret = PTR_ERR(tmp); remove_file() 457 spin_lock(&tmp->d_lock); remove_file() 458 if (simple_positive(tmp)) { remove_file() 459 __d_drop(tmp); remove_file() 460 spin_unlock(&tmp->d_lock); remove_file() 461 simple_unlink(d_inode(parent), tmp); remove_file() local 463 spin_unlock(&tmp->d_lock); remove_file() 465 dput(tmp); remove_file() 527 struct qib_devdata *dd, *tmp; qibfs_fill_super() local 545 list_for_each_entry_safe(dd, tmp, &qib_dev_list, list) { qibfs_fill_super()
/linux-4.4.14/arch/m32r/include/asm/
H A D	cmpxchg.h	20 unsigned long tmp = 0; __xchg() local 30 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory"); __xchg() 36 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory"); __xchg() 42 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory"); __xchg() 50 : "=&r" (tmp) : "r" (x), "r" (ptr) __xchg() 64 return (tmp); __xchg() 74 unsigned long tmp = 0; __xchg_local() local 83 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory"); __xchg_local() 89 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory"); __xchg_local() 95 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory"); __xchg_local() 103 return (tmp); __xchg_local()
/linux-4.4.14/arch/m68k/include/asm/
H A D	cmpxchg.h	14 unsigned long flags, tmp; __xchg() local 20 tmp = *(u8 *)ptr; __xchg() 22 x = tmp; __xchg() 25 tmp = *(u16 *)ptr; __xchg() 27 x = tmp; __xchg() 30 tmp = *(u32 *)ptr; __xchg() 32 x = tmp; __xchg() 35 tmp = __invalid_xchg_size(x, ptr, size); __xchg()
H A D	uaccess_mm.h	205 #define __constant_copy_from_user_asm(res, to, from, tmp, n, s1, s2, s3)\ 235 : "+d" (res), "+&a" (to), "+a" (from), "=&d" (tmp) \ 241 unsigned long res = 0, tmp; __constant_copy_from_user() local 251 __constant_copy_from_user_asm(res, to, from, tmp, 3, w, b,); __constant_copy_from_user() 257 __constant_copy_from_user_asm(res, to, from, tmp, 5, l, b,); __constant_copy_from_user() 260 __constant_copy_from_user_asm(res, to, from, tmp, 6, l, w,); __constant_copy_from_user() 263 __constant_copy_from_user_asm(res, to, from, tmp, 7, l, w, b); __constant_copy_from_user() 266 __constant_copy_from_user_asm(res, to, from, tmp, 8, l, l,); __constant_copy_from_user() 269 __constant_copy_from_user_asm(res, to, from, tmp, 9, l, l, b); __constant_copy_from_user() 272 __constant_copy_from_user_asm(res, to, from, tmp, 10, l, l, w); __constant_copy_from_user() 275 __constant_copy_from_user_asm(res, to, from, tmp, 12, l, l, l); __constant_copy_from_user() 285 #define __constant_copy_to_user_asm(res, to, from, tmp, n, s1, s2, s3) \ 316 : "+d" (res), "+a" (to), "+a" (from), "=&d" (tmp) \ 322 unsigned long res = 0, tmp; __constant_copy_to_user() local 332 __constant_copy_to_user_asm(res, to, from, tmp, 3, w, b,); __constant_copy_to_user() 338 __constant_copy_to_user_asm(res, to, from, tmp, 5, l, b,); __constant_copy_to_user() 341 __constant_copy_to_user_asm(res, to, from, tmp, 6, l, w,); __constant_copy_to_user() 344 __constant_copy_to_user_asm(res, to, from, tmp, 7, l, w, b); __constant_copy_to_user() 347 __constant_copy_to_user_asm(res, to, from, tmp, 8, l, l,); __constant_copy_to_user() 350 __constant_copy_to_user_asm(res, to, from, tmp, 9, l, l, b); __constant_copy_to_user() 353 __constant_copy_to_user_asm(res, to, from, tmp, 10, l, l, w); __constant_copy_to_user() 356 __constant_copy_to_user_asm(res, to, from, tmp, 12, l, l, l); __constant_copy_to_user()
H A D	raw_io.h	133 unsigned int tmp; raw_insw() local 136 tmp = (nr & 15) - 1; raw_insw() 139 : "=a" (buf), "=d" (tmp) raw_insw() 141 "1" (tmp)); raw_insw() 144 tmp = (nr >> 4) - 1; raw_insw() 164 : "=a" (buf), "=d" (tmp) raw_insw() 166 "1" (tmp)); raw_insw() 173 unsigned int tmp; raw_outsw() local 176 tmp = (nr & 15) - 1; raw_outsw() 179 : "=a" (buf), "=d" (tmp) raw_outsw() 181 "1" (tmp)); raw_outsw() 184 tmp = (nr >> 4) - 1; raw_outsw() 204 : "=a" (buf), "=d" (tmp) raw_outsw() 206 "1" (tmp)); raw_outsw() 212 unsigned int tmp; raw_insl() local 215 tmp = (nr & 15) - 1; raw_insl() 218 : "=a" (buf), "=d" (tmp) raw_insl() 220 "1" (tmp)); raw_insl() 223 tmp = (nr >> 4) - 1; raw_insl() 243 : "=a" (buf), "=d" (tmp) raw_insl() 245 "1" (tmp)); raw_insl() 252 unsigned int tmp; raw_outsl() local 255 tmp = (nr & 15) - 1; raw_outsl() 258 : "=a" (buf), "=d" (tmp) raw_outsl() 260 "1" (tmp)); raw_outsl() 263 tmp = (nr >> 4) - 1; raw_outsl() 283 : "=a" (buf), "=d" (tmp) raw_outsl() 285 "1" (tmp)); raw_outsl()
/linux-4.4.14/drivers/net/ethernet/mellanox/mlxsw/
H A D	item.h	80 u16 tmp; __mlxsw_item_get16() local 82 tmp = be16_to_cpu(b[offset]); __mlxsw_item_get16() 83 tmp >>= item->shift; __mlxsw_item_get16() 84 tmp &= GENMASK(item->size.bits - 1, 0); __mlxsw_item_get16() 86 tmp <<= item->shift; __mlxsw_item_get16() 87 return tmp; __mlxsw_item_get16() 97 u16 tmp; __mlxsw_item_set16() local 102 tmp = be16_to_cpu(b[offset]); __mlxsw_item_set16() 103 tmp &= ~mask; __mlxsw_item_set16() 104 tmp |= val; __mlxsw_item_set16() 105 b[offset] = cpu_to_be16(tmp); __mlxsw_item_set16() 113 u32 tmp; __mlxsw_item_get32() local 115 tmp = be32_to_cpu(b[offset]); __mlxsw_item_get32() 116 tmp >>= item->shift; __mlxsw_item_get32() 117 tmp &= GENMASK(item->size.bits - 1, 0); __mlxsw_item_get32() 119 tmp <<= item->shift; __mlxsw_item_get32() 120 return tmp; __mlxsw_item_get32() 130 u32 tmp; __mlxsw_item_set32() local 135 tmp = be32_to_cpu(b[offset]); __mlxsw_item_set32() 136 tmp &= ~mask; __mlxsw_item_set32() 137 tmp |= val; __mlxsw_item_set32() 138 b[offset] = cpu_to_be32(tmp); __mlxsw_item_set32() 146 u64 tmp; __mlxsw_item_get64() local 148 tmp = be64_to_cpu(b[offset]); __mlxsw_item_get64() 149 tmp >>= item->shift; __mlxsw_item_get64() 150 tmp &= GENMASK_ULL(item->size.bits - 1, 0); __mlxsw_item_get64() 152 tmp <<= item->shift; __mlxsw_item_get64() 153 return tmp; __mlxsw_item_get64() 162 u64 tmp; __mlxsw_item_set64() local 167 tmp = be64_to_cpu(b[offset]); __mlxsw_item_set64() 168 tmp &= ~mask; __mlxsw_item_set64() 169 tmp |= val; __mlxsw_item_set64() 170 b[offset] = cpu_to_be64(tmp); __mlxsw_item_set64() 218 u8 shift, tmp; __mlxsw_item_bit_array_get() local 221 tmp = buf[offset]; __mlxsw_item_bit_array_get() 222 tmp >>= shift; __mlxsw_item_bit_array_get() 223 tmp &= GENMASK(item->element_size - 1, 0); __mlxsw_item_bit_array_get() 224 return tmp; __mlxsw_item_bit_array_get() 230 u8 shift, tmp; __mlxsw_item_bit_array_set() local 236 tmp = buf[offset]; __mlxsw_item_bit_array_set() 237 tmp &= ~mask; __mlxsw_item_bit_array_set() 238 tmp |= val; __mlxsw_item_bit_array_set() 239 buf[offset] = tmp; __mlxsw_item_bit_array_set()
/linux-4.4.14/drivers/video/console/
H A D	fbcon_rotate.h	25 u32 tmp = (y * pitch) + x, index = tmp / 8, bit = tmp % 8; pattern_test_bit() local 33 u32 tmp = (y * pitch) + x, index = tmp / 8, bit = tmp % 8; pattern_set_bit() local
/linux-4.4.14/arch/alpha/include/asm/
H A D	fpu.h	15 unsigned long tmp, ret; rdfpcr() local 23 : "=r"(tmp), "=r"(ret)); rdfpcr() 30 : "=m"(tmp), "=m"(ret)); rdfpcr() 39 unsigned long tmp; wrfpcr() local 47 : "=&r"(tmp) : "r"(val)); wrfpcr() 54 : "=m"(tmp) : "m"(val)); wrfpcr()
H A D	atomic.h	180 long c, tmp; atomic64_add_unless() local 183 "1: ldq_l %[tmp],%[mem]\n" atomic64_add_unless() 184 " cmpeq %[tmp],%[u],%[c]\n" atomic64_add_unless() 185 " addq %[tmp],%[a],%[tmp]\n" atomic64_add_unless() 187 " stq_c %[tmp],%[mem]\n" atomic64_add_unless() 188 " beq %[tmp],3f\n" atomic64_add_unless() 193 : [tmp] "=&r"(tmp), [c] "=&r"(c) atomic64_add_unless() 209 long old, tmp; atomic64_dec_if_positive() local 213 " subq %[old],1,%[tmp]\n" atomic64_dec_if_positive() 215 " stq_c %[tmp],%[mem]\n" atomic64_dec_if_positive() 216 " beq %[tmp],3f\n" atomic64_dec_if_positive() 221 : [old] "=&r"(old), [tmp] "=&r"(tmp) atomic64_dec_if_positive()
/linux-4.4.14/fs/gfs2/
H A D	bmap.h	35 unsigned int tmp; gfs2_write_calc_reserv() local 41 for (tmp = *data_blocks; tmp > sdp->sd_diptrs;) { gfs2_write_calc_reserv() 42 tmp = DIV_ROUND_UP(tmp, sdp->sd_inptrs); gfs2_write_calc_reserv() 43 *ind_blocks += tmp; gfs2_write_calc_reserv()
/linux-4.4.14/arch/microblaze/include/asm/
H A D	irqflags.h	52 unsigned long flags, tmp; arch_local_irq_save() local 58 : "=r"(flags), "=r"(tmp) arch_local_irq_save() 66 unsigned long tmp; arch_local_irq_disable() local 72 : "=r"(tmp) arch_local_irq_disable() 79 unsigned long tmp; arch_local_irq_enable() local 85 : "=r"(tmp) arch_local_irq_enable()
/linux-4.4.14/drivers/net/wireless/cw1200/
H A D	hwio.h	172 __le32 tmp; cw1200_reg_read_16() local 174 i = cw1200_reg_read(priv, addr, &tmp, sizeof(tmp)); cw1200_reg_read_16() 175 *val = le32_to_cpu(tmp) & 0xfffff; cw1200_reg_read_16() 182 __le32 tmp = cpu_to_le32((u32)val); cw1200_reg_write_16() local 183 return cw1200_reg_write(priv, addr, &tmp, sizeof(tmp)); cw1200_reg_write_16() 189 __le32 tmp; cw1200_reg_read_32() local 190 int i = cw1200_reg_read(priv, addr, &tmp, sizeof(tmp)); cw1200_reg_read_32() 191 *val = le32_to_cpu(tmp); cw1200_reg_read_32() 198 __le32 tmp = cpu_to_le32(val); cw1200_reg_write_32() local 199 return cw1200_reg_write(priv, addr, &tmp, sizeof(val)); cw1200_reg_write_32() 226 __le32 tmp; cw1200_apb_read_32() local 227 int i = cw1200_apb_read(priv, addr, &tmp, sizeof(tmp)); cw1200_apb_read_32() 228 *val = le32_to_cpu(tmp); cw1200_apb_read_32() 235 __le32 tmp = cpu_to_le32(val); cw1200_apb_write_32() local 236 return cw1200_apb_write(priv, addr, &tmp, sizeof(val)); cw1200_apb_write_32() 241 __le32 tmp; cw1200_ahb_read_32() local 242 int i = cw1200_ahb_read(priv, addr, &tmp, sizeof(tmp)); cw1200_ahb_read_32() 243 *val = le32_to_cpu(tmp); cw1200_ahb_read_32()
/linux-4.4.14/arch/mips/kernel/
H A D	ptrace32.c	62 u32 tmp; compat_arch_ptrace() local 72 copied = access_process_vm(child, (u64)addrOthers, &tmp, compat_arch_ptrace() 73 sizeof(tmp), 0); compat_arch_ptrace() 74 if (copied != sizeof(tmp)) compat_arch_ptrace() 76 ret = put_user(tmp, (u32 __user *) (unsigned long) data); compat_arch_ptrace() 84 unsigned int tmp; compat_arch_ptrace() local 91 tmp = regs->regs[addr]; compat_arch_ptrace() 96 tmp = -1; compat_arch_ptrace() 106 tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE], compat_arch_ptrace() 110 tmp = get_fpr32(&fregs[addr - FPR_BASE], 0); compat_arch_ptrace() 113 tmp = regs->cp0_epc; compat_arch_ptrace() 116 tmp = regs->cp0_cause; compat_arch_ptrace() 119 tmp = regs->cp0_badvaddr; compat_arch_ptrace() 122 tmp = regs->hi; compat_arch_ptrace() 125 tmp = regs->lo; compat_arch_ptrace() 128 tmp = child->thread.fpu.fcr31; compat_arch_ptrace() 132 tmp = boot_cpu_data.fpu_id; compat_arch_ptrace() 138 tmp = 0; compat_arch_ptrace() 143 tmp = (unsigned long) (dregs[addr - DSP_BASE]); compat_arch_ptrace() 148 tmp = 0; compat_arch_ptrace() 152 tmp = child->thread.dsp.dspcontrol; compat_arch_ptrace() 155 tmp = 0; compat_arch_ptrace() 159 ret = put_user(tmp, (unsigned __user *) (unsigned long) data); compat_arch_ptrace()
/linux-4.4.14/drivers/net/wireless/b43legacy/
H A D	xmit.c	375 s32 tmp; b43legacy_rssi_postprocess() local 380 tmp = in_rssi; b43legacy_rssi_postprocess() 381 if (tmp > 127) b43legacy_rssi_postprocess() 382 tmp -= 256; b43legacy_rssi_postprocess() 383 tmp *= 73; b43legacy_rssi_postprocess() 384 tmp /= 64; b43legacy_rssi_postprocess() 386 tmp += 25; b43legacy_rssi_postprocess() 388 tmp -= 3; b43legacy_rssi_postprocess() 394 tmp = phy->nrssi_lt[in_rssi]; b43legacy_rssi_postprocess() 395 tmp = 31 - tmp; b43legacy_rssi_postprocess() 396 tmp *= -131; b43legacy_rssi_postprocess() 397 tmp /= 128; b43legacy_rssi_postprocess() 398 tmp -= 57; b43legacy_rssi_postprocess() 400 tmp = in_rssi; b43legacy_rssi_postprocess() 401 tmp = 31 - tmp; b43legacy_rssi_postprocess() 402 tmp *= -149; b43legacy_rssi_postprocess() 403 tmp /= 128; b43legacy_rssi_postprocess() 404 tmp -= 68; b43legacy_rssi_postprocess() 408 tmp += 25; b43legacy_rssi_postprocess() 413 tmp = in_rssi - 256; b43legacy_rssi_postprocess() 415 tmp = in_rssi; b43legacy_rssi_postprocess() 418 tmp = in_rssi; b43legacy_rssi_postprocess() 419 tmp -= 11; b43legacy_rssi_postprocess() 420 tmp *= 103; b43legacy_rssi_postprocess() 421 tmp /= 64; b43legacy_rssi_postprocess() 423 tmp -= 109; b43legacy_rssi_postprocess() 425 tmp -= 83; b43legacy_rssi_postprocess() 428 return (s8)tmp; b43legacy_rssi_postprocess() 614 u8 tmp; b43legacy_handle_hwtxstatus() local 619 tmp = hw->count; b43legacy_handle_hwtxstatus() 620 status.frame_count = (tmp >> 4); b43legacy_handle_hwtxstatus() 621 status.rts_count = (tmp & 0x0F); b43legacy_handle_hwtxstatus() 622 tmp = hw->flags << 1; b43legacy_handle_hwtxstatus() 623 status.supp_reason = ((tmp & 0x1C) >> 2); b43legacy_handle_hwtxstatus() 624 status.pm_indicated = !!(tmp & 0x80); b43legacy_handle_hwtxstatus() 625 status.intermediate = !!(tmp & 0x40); b43legacy_handle_hwtxstatus() 626 status.for_ampdu = !!(tmp & 0x20); b43legacy_handle_hwtxstatus() 627 status.acked = !!(tmp & 0x02); b43legacy_handle_hwtxstatus()
/linux-4.4.14/drivers/video/fbdev/intelfb/
H A D	intelfbhw.c	69 u32 tmp; intelfbhw_get_chipset() local 92 tmp = 0; intelfbhw_get_chipset() 95 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp); intelfbhw_get_chipset() 96 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) & intelfbhw_get_chipset() 177 u16 tmp; intelfbhw_get_memory() local 190 tmp = 0; intelfbhw_get_memory() 191 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp); intelfbhw_get_memory() 211 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M) intelfbhw_get_memory() 224 switch (tmp & INTEL_830_GMCH_GMS_MASK) { intelfbhw_get_memory() 242 tmp & INTEL_830_GMCH_GMS_MASK); intelfbhw_get_memory() 247 switch (tmp & INTEL_855_GMCH_GMS_MASK) { intelfbhw_get_memory() 274 tmp & INTEL_855_GMCH_GMS_MASK); intelfbhw_get_memory() 315 int tmp; intelfbhw_validate_mode() local 326 tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel; intelfbhw_validate_mode() 327 if (tmp > dinfo->fb.size) { intelfbhw_validate_mode() 330 BtoKB(tmp), BtoKB(dinfo->fb.size)); intelfbhw_validate_mode() 366 tmp = 1000000000 / var->pixclock; intelfbhw_validate_mode() 367 if (tmp < MIN_CLOCK) { intelfbhw_validate_mode() 369 (tmp + 500) / 1000, MIN_CLOCK / 1000); intelfbhw_validate_mode() 372 if (tmp > MAX_CLOCK) { intelfbhw_validate_mode() 374 (tmp + 500) / 1000, MAX_CLOCK / 1000); intelfbhw_validate_mode() 418 u32 tmp; intelfbhw_do_blank() local 425 tmp = INREG(DSPACNTR); intelfbhw_do_blank() 427 tmp &= ~DISPPLANE_PLANE_ENABLE; intelfbhw_do_blank() 429 tmp |= DISPPLANE_PLANE_ENABLE; intelfbhw_do_blank() 430 OUTREG(DSPACNTR, tmp); intelfbhw_do_blank() 432 tmp = INREG(DSPABASE); intelfbhw_do_blank() 433 OUTREG(DSPABASE, tmp); intelfbhw_do_blank() 449 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK; intelfbhw_do_blank() 453 tmp |= ADPA_DPMS_D0; intelfbhw_do_blank() 456 tmp |= ADPA_DPMS_D1; intelfbhw_do_blank() 459 tmp |= ADPA_DPMS_D2; intelfbhw_do_blank() 462 tmp |= ADPA_DPMS_D3; intelfbhw_do_blank() 465 OUTREG(ADPA, tmp); intelfbhw_do_blank() 1283 u32 tmp; intelfbhw_program_mode() local 1299 tmp = INREG(VGACNTRL); intelfbhw_program_mode() 1300 tmp |= VGA_DISABLE; intelfbhw_program_mode() 1301 OUTREG(VGACNTRL, tmp); intelfbhw_program_mode() 1356 tmp = INREG(pipe_conf_reg); intelfbhw_program_mode() 1357 tmp &= ~PIPECONF_ENABLE; intelfbhw_program_mode() 1358 OUTREG(pipe_conf_reg, tmp); intelfbhw_program_mode() 1368 tmp = INREG(pipe_conf_reg); intelfbhw_program_mode() 1369 tmp &= ~PIPECONF_ENABLE; intelfbhw_program_mode() 1370 OUTREG(pipe_conf_reg, tmp); intelfbhw_program_mode() 1377 tmp = INREG(DSPACNTR); intelfbhw_program_mode() 1378 tmp &= ~DISPPLANE_PLANE_ENABLE; intelfbhw_program_mode() 1379 OUTREG(DSPACNTR, tmp); intelfbhw_program_mode() 1380 tmp = INREG(DSPBCNTR); intelfbhw_program_mode() 1381 tmp &= ~DISPPLANE_PLANE_ENABLE; intelfbhw_program_mode() 1382 OUTREG(DSPBCNTR, tmp); intelfbhw_program_mode() 1392 tmp = INREG(ADPA); intelfbhw_program_mode() 1393 tmp &= ~ADPA_DPMS_CONTROL_MASK; intelfbhw_program_mode() 1394 tmp |= ADPA_DPMS_D3; intelfbhw_program_mode() 1395 OUTREG(ADPA, tmp); intelfbhw_program_mode() 1401 tmp = INREG(dpll_reg); intelfbhw_program_mode() 1402 tmp &= ~DPLL_VCO_ENABLE; intelfbhw_program_mode() 1403 OUTREG(dpll_reg, tmp); intelfbhw_program_mode() 1447 tmp = INREG(ADPA); intelfbhw_program_mode() 1448 tmp &= ~ADPA_DPMS_CONTROL_MASK; intelfbhw_program_mode() 1449 tmp |= ADPA_DPMS_D0; intelfbhw_program_mode() 1450 OUTREG(ADPA, tmp); intelfbhw_program_mode() 1459 tmp = INREG(DSPACNTR); intelfbhw_program_mode() 1460 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) { intelfbhw_program_mode() 1461 tmp |= DISPPLANE_PLANE_ENABLE; intelfbhw_program_mode() 1462 OUTREG(DSPACNTR, tmp); intelfbhw_program_mode() 1475 tmp = INREG(DSPACNTR); intelfbhw_program_mode() 1476 tmp |= DISPPLANE_PLANE_ENABLE; intelfbhw_program_mode() 1477 OUTREG(DSPACNTR, tmp); intelfbhw_program_mode() 1590 u32 tmp; reset_state() local 1600 tmp = INREG(PRI_RING_LENGTH); reset_state() 1601 if (tmp & RING_ENABLE) { reset_state() 1754 int nbytes, ndwords, pad, tmp; intelfbhw_do_drawglyph() local 1785 tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords; intelfbhw_do_drawglyph() 1786 br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp; intelfbhw_do_drawglyph() 1841 u32 tmp; intelfbhw_cursor_init() local 1850 tmp = INREG(CURSOR_A_CONTROL); intelfbhw_cursor_init() 1851 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE | intelfbhw_cursor_init() 1854 tmp |= CURSOR_MODE_DISABLE; intelfbhw_cursor_init() 1855 OUTREG(CURSOR_A_CONTROL, tmp); intelfbhw_cursor_init() 1858 tmp = INREG(CURSOR_CONTROL); intelfbhw_cursor_init() 1859 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE | intelfbhw_cursor_init() 1861 tmp |= CURSOR_FORMAT_3C; intelfbhw_cursor_init() 1862 OUTREG(CURSOR_CONTROL, tmp); intelfbhw_cursor_init() 1864 tmp = (64 << CURSOR_SIZE_H_SHIFT) | intelfbhw_cursor_init() 1866 OUTREG(CURSOR_SIZE, tmp); intelfbhw_cursor_init() 1872 u32 tmp; intelfbhw_cursor_hide() local 1882 tmp = INREG(CURSOR_A_CONTROL); intelfbhw_cursor_hide() 1883 tmp &= ~CURSOR_MODE_MASK; intelfbhw_cursor_hide() 1884 tmp |= CURSOR_MODE_DISABLE; intelfbhw_cursor_hide() 1885 OUTREG(CURSOR_A_CONTROL, tmp); intelfbhw_cursor_hide() 1889 tmp = INREG(CURSOR_CONTROL); intelfbhw_cursor_hide() 1890 tmp &= ~CURSOR_ENABLE; intelfbhw_cursor_hide() 1891 OUTREG(CURSOR_CONTROL, tmp); intelfbhw_cursor_hide() 1897 u32 tmp; intelfbhw_cursor_show() local 1911 tmp = INREG(CURSOR_A_CONTROL); intelfbhw_cursor_show() 1912 tmp &= ~CURSOR_MODE_MASK; intelfbhw_cursor_show() 1913 tmp |= CURSOR_MODE_64_4C_AX; intelfbhw_cursor_show() 1914 OUTREG(CURSOR_A_CONTROL, tmp); intelfbhw_cursor_show() 1918 tmp = INREG(CURSOR_CONTROL); intelfbhw_cursor_show() 1919 tmp |= CURSOR_ENABLE; intelfbhw_cursor_show() 1920 OUTREG(CURSOR_CONTROL, tmp); intelfbhw_cursor_show() 1926 u32 tmp; intelfbhw_cursor_setpos() local 1938 tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) | intelfbhw_cursor_setpos() 1940 OUTREG(CURSOR_A_POSITION, tmp); intelfbhw_cursor_setpos() 2010 u16 tmp; intelfbhw_irq() local 2015 tmp = INREG16(IIR); intelfbhw_irq() 2017 tmp &= PIPE_A_EVENT_INTERRUPT; intelfbhw_irq() 2019 tmp &= VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */ intelfbhw_irq() 2021 if (tmp == 0) { intelfbhw_irq() 2029 OUTREG16(IIR, tmp); intelfbhw_irq() 2045 u16 tmp; intelfbhw_enable_irq() local 2060 tmp = PIPE_A_EVENT_INTERRUPT; intelfbhw_enable_irq() 2062 tmp = VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */ intelfbhw_enable_irq() 2063 if (tmp != INREG16(IER)) { intelfbhw_enable_irq() 2064 DBG_MSG("changing IER to 0x%X\n", tmp); intelfbhw_enable_irq() 2065 OUTREG16(IER, tmp); intelfbhw_enable_irq()
/linux-4.4.14/drivers/mfd/
H A D	ezx-pcap.c	114 u32 tmp = PCAP_REGISTER_READ_OP_BIT | ezx_pcap_set_bits() local 118 ret = ezx_pcap_putget(pcap, &tmp); ezx_pcap_set_bits() 122 tmp &= (PCAP_REGISTER_VALUE_MASK & ~mask); ezx_pcap_set_bits() 123 tmp |= (val & mask) | PCAP_REGISTER_WRITE_OP_BIT | ezx_pcap_set_bits() 126 ret = ezx_pcap_putget(pcap, &tmp); ezx_pcap_set_bits() 219 u32 tmp; pcap_set_ts_bits() local 222 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); pcap_set_ts_bits() 223 tmp &= ~(PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR); pcap_set_ts_bits() 224 tmp |= bits & (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR); pcap_set_ts_bits() 225 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); pcap_set_ts_bits() 232 u32 tmp; pcap_disable_adc() local 234 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); pcap_disable_adc() 235 tmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY); pcap_disable_adc() 236 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); pcap_disable_adc() 241 u32 tmp; pcap_adc_trigger() local 253 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); pcap_adc_trigger() 254 tmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR); pcap_adc_trigger() 255 tmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN; pcap_adc_trigger() 258 tmp |= PCAP_ADC_AD_SEL1; pcap_adc_trigger() 260 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); pcap_adc_trigger() 270 u32 tmp; pcap_adc_irq() local 281 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); pcap_adc_irq() 282 tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK); pcap_adc_irq() 283 tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT); pcap_adc_irq() 284 tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT); pcap_adc_irq() 285 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); pcap_adc_irq() 286 ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp); pcap_adc_irq() 287 res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT; pcap_adc_irq() 288 res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT; pcap_adc_irq()
/linux-4.4.14/drivers/media/pci/cobalt/
H A D	cobalt-cpld.c	40 u32 tmp; cpld_info_ver3() local 79 tmp = (rd * 33 * 1000) / (483 * 10); cpld_info_ver3() 80 cobalt_info("\t\tVDD 3V3: %u,%03uV\n", tmp / 1000, tmp % 1000); cpld_info_ver3() 82 tmp = (rd * 74 * 2197) / (27 * 1000); cpld_info_ver3() 83 cobalt_info("\t\tADC ch3 5V: %u,%03uV\n", tmp / 1000, tmp % 1000); cpld_info_ver3() 85 tmp = (rd * 74 * 2197) / (47 * 1000); cpld_info_ver3() 86 cobalt_info("\t\tADC ch4 3V: %u,%03uV\n", tmp / 1000, tmp % 1000); cpld_info_ver3() 88 tmp = (rd * 57 * 2197) / (47 * 1000); cpld_info_ver3() 89 cobalt_info("\t\tADC ch5 2V5: %u,%03uV\n", tmp / 1000, tmp % 1000); cpld_info_ver3() 91 tmp = (rd * 2197) / 1000; cpld_info_ver3() 92 cobalt_info("\t\tADC ch6 1V8: %u,%03uV\n", tmp / 1000, tmp % 1000); cpld_info_ver3() 94 tmp = (rd * 2197) / 1000; cpld_info_ver3() 95 cobalt_info("\t\tADC ch7 1V5: %u,%03uV\n", tmp / 1000, tmp % 1000); cpld_info_ver3() 97 tmp = (rd * 2197) / 1000; cpld_info_ver3() 98 cobalt_info("\t\tADC ch8 0V9: %u,%03uV\n", tmp / 1000, tmp % 1000); cpld_info_ver3()
/linux-4.4.14/arch/m68k/kernel/
H A D	ptrace.c	128 unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS; singlestep_disable() local 129 put_reg(child, PT_SR, tmp); singlestep_disable() 143 unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS; user_enable_single_step() local 144 put_reg(child, PT_SR, tmp | T1_BIT); user_enable_single_step() 151 unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS; user_enable_block_step() local 152 put_reg(child, PT_SR, tmp | T0_BIT); user_enable_block_step() 164 unsigned long tmp; arch_ptrace() local 176 tmp = get_reg(child, regno); arch_ptrace() 178 tmp = child->thread.fp[regno - 21]; arch_ptrace() 183 tmp = ((tmp & 0xffff0000) << 15) | arch_ptrace() 184 ((tmp & 0x0000ffff) << 16); arch_ptrace() 187 tmp = child->mm->start_code; arch_ptrace() 189 tmp = child->mm->start_data; arch_ptrace() 191 tmp = child->mm->end_code; arch_ptrace() 195 ret = put_user(tmp, datap); arch_ptrace() 226 tmp = get_reg(child, i); arch_ptrace() 227 ret = put_user(tmp, datap); arch_ptrace() 236 ret = get_user(tmp, datap); arch_ptrace() 240 tmp &= SR_MASK; arch_ptrace() 241 tmp |= get_reg(child, PT_SR) & ~SR_MASK; arch_ptrace() 243 put_reg(child, i, tmp); arch_ptrace()
/linux-4.4.14/sound/soc/nuc900/
H A D	nuc900-ac97.c	101 unsigned long tmp, timeout = 0x10000; nuc900_ac97_write() local 105 tmp = nuc900_checkready(); nuc900_ac97_write() 106 if (tmp) nuc900_ac97_write() 116 tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0); nuc900_ac97_write() 117 tmp |= SLOT1_VALID | SLOT2_VALID | VALID_FRAME; nuc900_ac97_write() 118 AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, tmp); nuc900_ac97_write() 130 tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0); nuc900_ac97_write() 131 tmp &= ~(SLOT1_VALID | SLOT2_VALID); nuc900_ac97_write() 132 AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, tmp); nuc900_ac97_write() 213 unsigned long val, tmp; nuc900_ac97_trigger() local 222 tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0); nuc900_ac97_trigger() 223 tmp |= (SLOT3_VALID | SLOT4_VALID | VALID_FRAME); nuc900_ac97_trigger() 224 AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, tmp); nuc900_ac97_trigger() 226 tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_PSR); nuc900_ac97_trigger() 227 tmp |= (P_DMA_END_IRQ | P_DMA_MIDDLE_IRQ); nuc900_ac97_trigger() 228 AUDIO_WRITE(nuc900_audio->mmio + ACTL_PSR, tmp); nuc900_ac97_trigger() 231 tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_RSR); nuc900_ac97_trigger() 232 tmp |= (R_DMA_END_IRQ | R_DMA_MIDDLE_IRQ); nuc900_ac97_trigger() 234 AUDIO_WRITE(nuc900_audio->mmio + ACTL_RSR, tmp); nuc900_ac97_trigger() 245 tmp = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0); nuc900_ac97_trigger() 246 tmp &= ~(SLOT3_VALID | SLOT4_VALID); nuc900_ac97_trigger() 247 AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, tmp); nuc900_ac97_trigger()
/linux-4.4.14/sound/isa/gus/
H A D	gus_timer.c	35 unsigned char tmp; snd_gf1_timer1_start() local 42 tmp = (gus->gf1.timer_enabled |= 4); snd_gf1_timer1_start() 44 snd_gf1_write8(gus, SNDRV_GF1_GB_SOUND_BLASTER_CONTROL, tmp); /* enable timer 1 IRQ */ snd_gf1_timer1_start() 45 snd_gf1_adlib_write(gus, 0x04, tmp >> 2); /* timer 2 start */ snd_gf1_timer1_start() 53 unsigned char tmp; snd_gf1_timer1_stop() local 58 tmp = (gus->gf1.timer_enabled &= ~4); snd_gf1_timer1_stop() 59 snd_gf1_write8(gus, SNDRV_GF1_GB_SOUND_BLASTER_CONTROL, tmp); /* disable timer #1 */ snd_gf1_timer1_stop() 71 unsigned char tmp; snd_gf1_timer2_start() local 78 tmp = (gus->gf1.timer_enabled |= 8); snd_gf1_timer2_start() 80 snd_gf1_write8(gus, SNDRV_GF1_GB_SOUND_BLASTER_CONTROL, tmp); /* enable timer 2 IRQ */ snd_gf1_timer2_start() 81 snd_gf1_adlib_write(gus, 0x04, tmp >> 2); /* timer 2 start */ snd_gf1_timer2_start() 89 unsigned char tmp; snd_gf1_timer2_stop() local 94 tmp = (gus->gf1.timer_enabled &= ~8); snd_gf1_timer2_stop() 95 snd_gf1_write8(gus, SNDRV_GF1_GB_SOUND_BLASTER_CONTROL, tmp); /* disable timer #1 */ snd_gf1_timer2_stop()
/linux-4.4.14/drivers/staging/rdma/ipath/
H A D	ipath_fs.c	133 char *tmp; flash_read() local 150 tmp = kmalloc(count, GFP_KERNEL); flash_read() 151 if (!tmp) { flash_read() 157 if (ipath_eeprom_read(dd, pos, tmp, count)) { flash_read() 163 if (copy_to_user(buf, tmp, count)) { flash_read() 172 kfree(tmp); flash_read() 184 char *tmp; flash_write() local 198 tmp = memdup_user(buf, count); flash_write() 199 if (IS_ERR(tmp)) flash_write() 200 return PTR_ERR(tmp); flash_write() 203 if (ipath_eeprom_write(dd, pos, tmp, count)) { flash_write() 213 kfree(tmp); flash_write() 228 struct dentry *dir, *tmp; create_device_files() local 240 ret = create_file("atomic_counters", S_IFREG|S_IRUGO, dir, &tmp, create_device_files() 248 ret = create_file("flash", S_IFREG|S_IWUSR|S_IRUGO, dir, &tmp, create_device_files() 262 struct dentry *tmp; remove_file() local 265 tmp = lookup_one_len(name, parent, strlen(name)); remove_file() 267 if (IS_ERR(tmp)) { remove_file() 268 ret = PTR_ERR(tmp); remove_file() 272 spin_lock(&tmp->d_lock); remove_file() 273 if (simple_positive(tmp)) { remove_file() 274 dget_dlock(tmp); remove_file() 275 __d_drop(tmp); remove_file() 276 spin_unlock(&tmp->d_lock); remove_file() 277 simple_unlink(d_inode(parent), tmp); remove_file() local 279 spin_unlock(&tmp->d_lock); remove_file() 322 struct ipath_devdata *dd, *tmp; ipathfs_fill_super() local 339 list_for_each_entry_safe(dd, tmp, &ipath_dev_list, ipath_list) { ipathfs_fill_super()
/linux-4.4.14/arch/cris/arch-v32/kernel/
H A D	ptrace.c	82 unsigned long tmp; user_enable_single_step() local 90 tmp = get_reg(child, PT_ERP) & ~1; user_enable_single_step() 91 put_reg(child, PT_SPC, tmp); user_enable_single_step() 93 tmp = get_reg(child, PT_CCS) | SBIT_USER; user_enable_single_step() 94 put_reg(child, PT_CCS, tmp); user_enable_single_step() 102 unsigned long tmp; user_disable_single_step() local 104 tmp = get_reg(child, PT_CCS) & ~SBIT_USER; user_disable_single_step() 105 put_reg(child, PT_CCS, tmp); user_disable_single_step() 137 unsigned long tmp; arch_ptrace() local 148 tmp = *(unsigned long*)addr; arch_ptrace() 150 copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0); arch_ptrace() 152 if (copied != sizeof(tmp)) arch_ptrace() 156 ret = put_user(tmp,datap); arch_ptrace() 162 unsigned long tmp; arch_ptrace() local 168 tmp = get_reg(child, regno); arch_ptrace() 169 ret = put_user(tmp, datap); arch_ptrace() 200 unsigned long tmp; arch_ptrace() local 203 tmp = get_reg(child, i); arch_ptrace() 205 if (put_user(tmp, datap)) { arch_ptrace() 220 unsigned long tmp; arch_ptrace() local 223 if (get_user(tmp, datap)) { arch_ptrace() 229 tmp &= CCS_MASK; arch_ptrace() 230 tmp |= get_reg(child, PT_CCS) & ~CCS_MASK; arch_ptrace() 233 put_reg(child, i, tmp); arch_ptrace() 346 unsigned long tmp; deconfigure_bp() local 352 tmp = get_debugreg(pid, PT_BP_CTRL) & ~(3 << (2 + (bp * 4))); deconfigure_bp() 353 put_debugreg(pid, PT_BP_CTRL, tmp); deconfigure_bp()
/linux-4.4.14/drivers/media/pci/cx25821/
H A D	cx25821-medusa-video.c	39 u32 tmp = 0; medusa_enable_bluefield_output() local 77 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); medusa_enable_bluefield_output() 83 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); medusa_enable_bluefield_output() 95 u32 tmp = 0; medusa_initialize_ntsc() local 100 MODE_CTRL + (0x200 * i), &tmp); medusa_initialize_ntsc() 109 HORIZ_TIM_CTRL + (0x200 * i), &tmp); medusa_initialize_ntsc() 116 VERT_TIM_CTRL + (0x200 * i), &tmp); medusa_initialize_ntsc() 128 OUT_CTRL_NS + (0x200 * i), &tmp); medusa_initialize_ntsc() 136 OUT_CTRL1 + (0x200 * i), &tmp); medusa_initialize_ntsc() 147 MISC_TIM_CTRL + (0x200 * i), &tmp); medusa_initialize_ntsc() 156 DFE_CTRL1 + (0x200 * i), &tmp); medusa_initialize_ntsc() 168 DENC_A_REG_1 + (0x100 * i), &tmp); medusa_initialize_ntsc() 176 DENC_A_REG_2 + (0x100 * i), &tmp); medusa_initialize_ntsc() 183 DENC_A_REG_3 + (0x100 * i), &tmp); medusa_initialize_ntsc() 191 DENC_A_REG_4 + (0x100 * i), &tmp); medusa_initialize_ntsc() 198 DENC_A_REG_5 + (0x100 * i), &tmp); medusa_initialize_ntsc() 219 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); medusa_initialize_ntsc() 229 u32 value = 0, tmp = 0; medusa_PALCombInit() local 241 COMB_FLAT_THRESH_CTRL + (0x200 * dec), &tmp); medusa_PALCombInit() 262 u32 tmp = 0; medusa_initialize_pal() local 267 MODE_CTRL + (0x200 * i), &tmp); medusa_initialize_pal() 276 HORIZ_TIM_CTRL + (0x200 * i), &tmp); medusa_initialize_pal() 284 VERT_TIM_CTRL + (0x200 * i), &tmp); medusa_initialize_pal() 296 OUT_CTRL_NS + (0x200 * i), &tmp); medusa_initialize_pal() 304 OUT_CTRL1 + (0x200 * i), &tmp); medusa_initialize_pal() 315 MISC_TIM_CTRL + (0x200 * i), &tmp); medusa_initialize_pal() 324 DFE_CTRL1 + (0x200 * i), &tmp); medusa_initialize_pal() 338 DENC_A_REG_1 + (0x100 * i), &tmp); medusa_initialize_pal() 346 DENC_A_REG_2 + (0x100 * i), &tmp); medusa_initialize_pal() 354 DENC_A_REG_3 + (0x100 * i), &tmp); medusa_initialize_pal() 362 DENC_A_REG_4 + (0x100 * i), &tmp); medusa_initialize_pal() 369 DENC_A_REG_5 + (0x100 * i), &tmp); medusa_initialize_pal() 390 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); medusa_initialize_pal() 400 u32 value = 0, tmp = 0; medusa_set_videostandard() local 408 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4, &tmp); medusa_set_videostandard() 413 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_B_REG_4, &tmp); medusa_set_videostandard() 484 u32 tmp = 0; medusa_set_decoderduration() local 510 fld_cnt = cx25821_i2c_read(&dev->i2c_bus[0], disp_cnt_reg, &tmp); medusa_set_decoderduration() 569 u32 val = 0, tmp = 0; medusa_set_brightness() local 579 VDEC_A_BRITE_CTRL + (0x200 * decoder), &tmp); medusa_set_brightness() 590 u32 val = 0, tmp = 0; medusa_set_contrast() local 599 VDEC_A_CNTRST_CTRL + (0x200 * decoder), &tmp); medusa_set_contrast() 611 u32 val = 0, tmp = 0; medusa_set_hue() local 622 VDEC_A_HUE_CTRL + (0x200 * decoder), &tmp); medusa_set_hue() 635 u32 val = 0, tmp = 0; medusa_set_saturation() local 646 VDEC_A_USAT_CTRL + (0x200 * decoder), &tmp); medusa_set_saturation() 652 VDEC_A_VSAT_CTRL + (0x200 * decoder), &tmp); medusa_set_saturation() 664 u32 value = 0, tmp = 0; medusa_video_init() local 669 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp); medusa_video_init() 677 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp); medusa_video_init() 694 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_AB_CTRL, &tmp); medusa_video_init() 703 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); medusa_video_init() 711 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp); medusa_video_init() 720 value = cx25821_i2c_read(&dev->i2c_bus[0], PIN_OE_CTRL, &tmp); medusa_video_init()
/linux-4.4.14/drivers/isdn/i4l/
H A D	isdn_x25iface.c	86 ix25_pdata_t *tmp = kmalloc(sizeof(ix25_pdata_t), GFP_KERNEL); isdn_x25iface_proto_new() local 88 if (tmp) { isdn_x25iface_proto_new() 89 tmp->magic = ISDN_X25IFACE_MAGIC; isdn_x25iface_proto_new() 90 tmp->state = WAN_UNCONFIGURED; isdn_x25iface_proto_new() 93 spin_lock_init(&tmp->priv.lock); isdn_x25iface_proto_new() 94 tmp->priv.dops = NULL; isdn_x25iface_proto_new() 95 tmp->priv.net_dev = NULL; isdn_x25iface_proto_new() 96 tmp->priv.pops = &ix25_pops; isdn_x25iface_proto_new() 97 tmp->priv.flags = 0; isdn_x25iface_proto_new() 98 tmp->priv.proto_data = tmp; isdn_x25iface_proto_new() 99 return (&(tmp->priv)); isdn_x25iface_proto_new() 108 ix25_pdata_t *tmp; isdn_x25iface_proto_close() local 121 tmp = cprot->proto_data; isdn_x25iface_proto_close() 122 if (pdata_is_bad(tmp)) { isdn_x25iface_proto_close() 125 tmp->state = WAN_UNCONFIGURED; isdn_x25iface_proto_close() 135 ix25_pdata_t *tmp; isdn_x25iface_proto_del() local 143 tmp = cprot->proto_data; isdn_x25iface_proto_del() 144 if (tmp == NULL) { isdn_x25iface_proto_del() 153 tmp->magic = 0; isdn_x25iface_proto_del() 156 kfree(tmp); isdn_x25iface_proto_del()
/linux-4.4.14/drivers/iio/frequency/
H A D	adf4350.c	133 u64 tmp; adf4350_set_freq() local 178 tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1); adf4350_set_freq() 179 do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */ adf4350_set_freq() 180 st->r0_fract = do_div(tmp, st->r1_mod); adf4350_set_freq() 181 st->r0_int = tmp; adf4350_set_freq() 252 unsigned long tmp; adf4350_write() local 271 tmp = clk_round_rate(st->clk, readin); adf4350_write() 272 if (tmp != readin) { adf4350_write() 276 ret = clk_set_rate(st->clk, tmp); adf4350_write() 385 unsigned int tmp; adf4350_parse_dt() local 394 tmp = 10000; adf4350_parse_dt() 395 of_property_read_u32(np, "adi,channel-spacing", &tmp); adf4350_parse_dt() 396 pdata->channel_spacing = tmp; adf4350_parse_dt() 398 tmp = 0; adf4350_parse_dt() 399 of_property_read_u32(np, "adi,power-up-frequency", &tmp); adf4350_parse_dt() 400 pdata->power_up_frequency = tmp; adf4350_parse_dt() 402 tmp = 0; adf4350_parse_dt() 403 of_property_read_u32(np, "adi,reference-div-factor", &tmp); adf4350_parse_dt() 404 pdata->ref_div_factor = tmp; adf4350_parse_dt() 428 tmp = 2500; adf4350_parse_dt() 429 of_property_read_u32(np, "adi,charge-pump-current", &tmp); adf4350_parse_dt() 430 pdata->r2_user_settings |= ADF4350_REG2_CHARGE_PUMP_CURR_uA(tmp); adf4350_parse_dt() 432 tmp = 0; adf4350_parse_dt() 433 of_property_read_u32(np, "adi,muxout-select", &tmp); adf4350_parse_dt() 434 pdata->r2_user_settings |= ADF4350_REG2_MUXOUT(tmp); adf4350_parse_dt() 456 tmp = 0; adf4350_parse_dt() 457 of_property_read_u32(np, "adi,12bit-clk-divider", &tmp); adf4350_parse_dt() 458 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV(tmp); adf4350_parse_dt() 460 tmp = 0; adf4350_parse_dt() 461 of_property_read_u32(np, "adi,clk-divider-mode", &tmp); adf4350_parse_dt() 462 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV_MODE(tmp); adf4350_parse_dt() 476 tmp = 0; adf4350_parse_dt() 477 of_property_read_u32(np, "adi,output-power", &tmp); adf4350_parse_dt() 478 pdata->r4_user_settings |= ADF4350_REG4_OUTPUT_PWR(tmp); adf4350_parse_dt() 480 tmp = 0; adf4350_parse_dt() 481 of_property_read_u32(np, "adi,aux-output-power", &tmp); adf4350_parse_dt() 482 pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_PWR(tmp); adf4350_parse_dt()
/linux-4.4.14/arch/score/kernel/
H A D	ptrace.c	178 unsigned int tmp, tmp2; user_enable_single_step() local 188 tmp = epc_insn & 0xFFE; user_enable_single_step() 189 epc = (epc & 0xFFFFF000) | tmp; user_enable_single_step() 192 tmp = (epc_insn & 0xFF) << 1; user_enable_single_step() 193 tmp = tmp << 23; user_enable_single_step() 194 tmp = (unsigned int)((int) tmp >> 23); user_enable_single_step() 195 far_epc = epc + tmp; user_enable_single_step() 199 tmp = (epc_insn >> 4) & 0xF; user_enable_single_step() 200 far_epc = regs->regs[tmp]; user_enable_single_step() 206 tmp = epc_insn & 0x03FFFFFE; user_enable_single_step() 207 tmp2 = tmp & 0x7FFF; user_enable_single_step() 208 tmp = (((tmp >> 16) & 0x3FF) << 15) | tmp2; user_enable_single_step() 209 epc = (epc & 0xFFC00000) | tmp; user_enable_single_step() 212 tmp = epc_insn & 0x03FFFFFE; /* discard LK bit */ user_enable_single_step() 213 tmp2 = tmp & 0x3FF; user_enable_single_step() 214 tmp = (((tmp >> 16) & 0x3FF) << 10) | tmp2; /* 20bit */ user_enable_single_step() 215 tmp = tmp << 12; user_enable_single_step() 216 tmp = (unsigned int)((int) tmp >> 12); user_enable_single_step() 217 far_epc = epc + tmp; user_enable_single_step() 221 tmp = (epc_insn >> 16) & 0x1F; user_enable_single_step() 222 far_epc = regs->regs[tmp]; user_enable_single_step()
/linux-4.4.14/drivers/media/tuners/
H A D	fc0013.c	197 u8 tmp; fc0013_set_vhf_track() local 199 ret = fc0013_readreg(priv, 0x1d, &tmp); fc0013_set_vhf_track() 202 tmp &= 0xe3; fc0013_set_vhf_track() 204 ret = fc0013_writereg(priv, 0x1d, tmp | 0x1c); fc0013_set_vhf_track() 206 ret = fc0013_writereg(priv, 0x1d, tmp | 0x18); fc0013_set_vhf_track() 208 ret = fc0013_writereg(priv, 0x1d, tmp | 0x14); fc0013_set_vhf_track() 210 ret = fc0013_writereg(priv, 0x1d, tmp | 0x10); fc0013_set_vhf_track() 212 ret = fc0013_writereg(priv, 0x1d, tmp | 0x0c); fc0013_set_vhf_track() 214 ret = fc0013_writereg(priv, 0x1d, tmp | 0x08); fc0013_set_vhf_track() 216 ret = fc0013_writereg(priv, 0x1d, tmp | 0x04); fc0013_set_vhf_track() 218 ret = fc0013_writereg(priv, 0x1d, tmp | 0x1c); fc0013_set_vhf_track() 231 unsigned char reg[7], am, pm, multi, tmp; fc0013_set_params() local 266 ret = fc0013_readreg(priv, 0x07, &tmp); fc0013_set_params() 269 ret = fc0013_writereg(priv, 0x07, tmp | 0x10); fc0013_set_params() 274 ret = fc0013_readreg(priv, 0x14, &tmp); fc0013_set_params() 277 ret = fc0013_writereg(priv, 0x14, tmp & 0x1f); fc0013_set_params() 282 ret = fc0013_readreg(priv, 0x07, &tmp); fc0013_set_params() 285 ret = fc0013_writereg(priv, 0x07, tmp & 0xef); fc0013_set_params() 290 ret = fc0013_readreg(priv, 0x14, &tmp); fc0013_set_params() 293 ret = fc0013_writereg(priv, 0x14, (tmp & 0x1f) | 0x40); fc0013_set_params() 298 ret = fc0013_readreg(priv, 0x07, &tmp); fc0013_set_params() 301 ret = fc0013_writereg(priv, 0x07, tmp & 0xef); fc0013_set_params() 306 ret = fc0013_readreg(priv, 0x14, &tmp); fc0013_set_params() 309 ret = fc0013_writereg(priv, 0x14, (tmp & 0x1f) | 0x20); fc0013_set_params() 430 ret = fc0013_readreg(priv, 0x11, &tmp); fc0013_set_params() 434 ret = fc0013_writereg(priv, 0x11, tmp | 0x04); fc0013_set_params() 436 ret = fc0013_writereg(priv, 0x11, tmp & 0xfb); fc0013_set_params() 451 ret = fc0013_readreg(priv, 0x0e, &tmp); fc0013_set_params() 457 tmp &= 0x3f; fc0013_set_params() 460 if (tmp > 0x3c) { fc0013_set_params() 469 if (tmp < 0x02) { fc0013_set_params() 517 unsigned char tmp; fc0013_get_rf_strength() local 538 ret = fc0013_readreg(priv, 0x13, &tmp); fc0013_get_rf_strength() 541 int_temp = tmp; fc0013_get_rf_strength() 543 ret = fc0013_readreg(priv, 0x14, &tmp); fc0013_get_rf_strength() 546 lna_gain = tmp & 0x1f; fc0013_get_rf_strength()
/linux-4.4.14/arch/alpha/lib/
H A D	memcpy.c	79 unsigned long tmp; __memcpy_unaligned_up() local 86 :"=r" (tmp) __memcpy_unaligned_up() 89 *(unsigned long *) d = low_word | tmp; __memcpy_unaligned_up() 122 unsigned long tmp; __memcpy_aligned_up() local 123 __asm__("ldq %0,%1":"=r" (tmp):"m" (*(unsigned long *) s)); __memcpy_aligned_up() 126 *(unsigned long *) d = tmp; __memcpy_aligned_up() 140 unsigned long tmp; __memcpy_aligned_dn() local 142 __asm__("ldq %0,%1":"=r" (tmp):"m" (*(unsigned long *) s)); __memcpy_aligned_dn() 145 *(unsigned long *) d = tmp; __memcpy_aligned_dn()
/linux-4.4.14/kernel/power/
H A D	console.c	47 struct pm_vt_switch *entry, *tmp; pm_vt_switch_required() local 50 list_for_each_entry(tmp, &pm_vt_switch_list, head) { pm_vt_switch_required() 51 if (tmp->dev == dev) { pm_vt_switch_required() 53 tmp->required = required; pm_vt_switch_required() 79 struct pm_vt_switch *tmp; pm_vt_switch_unregister() local 82 list_for_each_entry(tmp, &pm_vt_switch_list, head) { pm_vt_switch_unregister() 83 if (tmp->dev == dev) { pm_vt_switch_unregister() 84 list_del(&tmp->head); pm_vt_switch_unregister() 85 kfree(tmp); pm_vt_switch_unregister()
/linux-4.4.14/arch/arm/mach-lpc32xx/
H A D	serial.c	74 u32 tmp, clkmodes = 0; lpc32xx_serial_init() local 103 tmp = __raw_readl( lpc32xx_serial_init() 117 tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart)); lpc32xx_serial_init() 122 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); lpc32xx_serial_init() 123 tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS; lpc32xx_serial_init() 124 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); lpc32xx_serial_init() 127 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); lpc32xx_serial_init() 128 tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB; lpc32xx_serial_init() 129 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); lpc32xx_serial_init()
/linux-4.4.14/arch/arm/mach-exynos/
H A D	suspend.c	356 unsigned int tmp; exynos3250_pm_prepare() local 361 tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION); exynos3250_pm_prepare() 362 tmp &= ~EXYNOS5_OPTION_USE_RETENTION; exynos3250_pm_prepare() 363 pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION); exynos3250_pm_prepare() 373 unsigned int tmp; exynos5420_pm_prepare() local 397 tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION); exynos5420_pm_prepare() 398 tmp &= ~EXYNOS5_USE_RETENTION; exynos5420_pm_prepare() 399 pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION); exynos5420_pm_prepare() 401 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); exynos5420_pm_prepare() 402 tmp |= EXYNOS5420_UFS; exynos5420_pm_prepare() 403 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); exynos5420_pm_prepare() 405 tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION); exynos5420_pm_prepare() 406 tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE; exynos5420_pm_prepare() 407 pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION); exynos5420_pm_prepare() 409 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION); exynos5420_pm_prepare() 410 tmp |= EXYNOS5420_EMULATION; exynos5420_pm_prepare() 411 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION); exynos5420_pm_prepare() 413 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION); exynos5420_pm_prepare() 414 tmp |= EXYNOS5420_EMULATION; exynos5420_pm_prepare() 415 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); exynos5420_pm_prepare() 516 unsigned long tmp; exynos5420_pm_resume() local 519 tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG); exynos5420_pm_resume() 520 pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN, exynos5420_pm_resume() 542 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); exynos5420_pm_resume() 543 tmp &= ~EXYNOS5420_UFS; exynos5420_pm_resume() 544 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); exynos5420_pm_resume() 546 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION); exynos5420_pm_resume() 547 tmp &= ~EXYNOS5420_EMULATION; exynos5420_pm_resume() 548 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION); exynos5420_pm_resume() 550 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION); exynos5420_pm_resume() 551 tmp &= ~EXYNOS5420_EMULATION; exynos5420_pm_resume() 552 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); exynos5420_pm_resume() 717 u32 tmp; exynos_pm_init() local 733 tmp = pmu_raw_readl(S5P_WAKEUP_MASK); exynos_pm_init() 734 tmp |= pm_data->wake_disable_mask; exynos_pm_init() 735 pmu_raw_writel(tmp, S5P_WAKEUP_MASK); exynos_pm_init()
H A D	pm.c	60 unsigned long tmp; exynos_cpu_save_register() local 64 : "=r" (tmp) : : "cc"); exynos_cpu_save_register() 66 save_arm_register[0] = tmp; exynos_cpu_save_register() 70 : "=r" (tmp) : : "cc"); exynos_cpu_save_register() 72 save_arm_register[1] = tmp; exynos_cpu_save_register() 77 unsigned long tmp; exynos_cpu_restore_register() local 80 tmp = save_arm_register[0]; exynos_cpu_restore_register() 83 : : "r" (tmp) exynos_cpu_restore_register() 87 tmp = save_arm_register[1]; exynos_cpu_restore_register() 90 : : "r" (tmp) exynos_cpu_restore_register() 96 unsigned long tmp; exynos_pm_central_suspend() local 99 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); exynos_pm_central_suspend() 100 tmp &= ~S5P_CENTRAL_LOWPWR_CFG; exynos_pm_central_suspend() 101 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); exynos_pm_central_suspend() 106 unsigned long tmp; exynos_pm_central_resume() local 114 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); exynos_pm_central_resume() 115 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { exynos_pm_central_resume() 116 tmp |= S5P_CENTRAL_LOWPWR_CFG; exynos_pm_central_resume() 117 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); exynos_pm_central_resume()
/linux-4.4.14/drivers/clk/zte/
H A D	clk.c	180 u32 sel, integ, fra_div, tmp; calc_reg() local 187 tmp = (u32)tmp64 % BPAR; calc_reg() 188 sel = tmp / BPAR; calc_reg() 190 tmp = tmp % BPAR; calc_reg() 191 fra_div = tmp * 0xff / BPAR; calc_reg() 192 tmp = (sel << 24) | (integ << 16) | (0xff << 8) | fra_div; calc_reg() 197 tmp |= BIT(28); calc_reg() 198 return tmp; calc_reg() 203 u32 sel, integ, fra_div, tmp; calc_rate() local 206 tmp = reg; calc_rate() 207 sel = (tmp >> 24) & BIT(0); calc_rate() 208 integ = (tmp >> 16) & 0xff; calc_rate() 209 fra_div = tmp & 0xff; calc_rate() 211 tmp = fra_div * BPAR; calc_rate() 212 tmp = tmp / 0xff; calc_rate() 213 tmp += sel * BPAR; calc_rate() 214 tmp += 2 * integ * BPAR; calc_rate() 215 do_div(tmp64, tmp); calc_rate()
/linux-4.4.14/scripts/
H A D	extract-vmlinux	33 tail -c+$pos "$img" | $3 > $tmp 2> /dev/null 34 check_vmlinux $tmp 48 tmp=$(mktemp /tmp/vmlinux-XXX) 49 trap "rm -f $tmp" 0
/linux-4.4.14/arch/arm/mach-s3c24xx/include/mach/
H A D	pm-core.h	21 unsigned long tmp = __raw_readl(S3C2410_CLKCON); s3c_pm_debug_init_uart() local 24 tmp |= S3C2410_CLKCON_UART0; s3c_pm_debug_init_uart() 25 tmp |= S3C2410_CLKCON_UART1; s3c_pm_debug_init_uart() 26 tmp |= S3C2410_CLKCON_UART2; s3c_pm_debug_init_uart() 28 __raw_writel(tmp, S3C2410_CLKCON); s3c_pm_debug_init_uart()
/linux-4.4.14/arch/arm/mach-cns3xxx/
H A D	devices.c	55 u32 tmp; cns3xxx_ahci_init() local 57 tmp = __raw_readl(MISC_SATA_POWER_MODE); cns3xxx_ahci_init() 58 tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */ cns3xxx_ahci_init() 59 tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */ cns3xxx_ahci_init() 60 __raw_writel(tmp, MISC_SATA_POWER_MODE); cns3xxx_ahci_init()
/linux-4.4.14/arch/arm64/net/
H A D	bpf_jit_comp.c	79 u64 tmp = val; emit_a64_mov_i64() local 82 emit(A64_MOVZ(1, reg, tmp & 0xffff, shift), ctx); emit_a64_mov_i64() 83 tmp >>= 16; emit_a64_mov_i64() 85 while (tmp) { emit_a64_mov_i64() 86 if (tmp & 0xffff) emit_a64_mov_i64() 87 emit(A64_MOVK(1, reg, tmp & 0xffff, shift), ctx); emit_a64_mov_i64() 88 tmp >>= 16; emit_a64_mov_i64() 252 const u8 tmp = bpf2a64[TMP_REG_1]; build_insn() local 325 emit(A64_UDIV(is64, tmp, dst, src), ctx); build_insn() 326 emit(A64_MUL(is64, tmp, tmp, src), ctx); build_insn() 327 emit(A64_SUB(is64, dst, dst, tmp), ctx); build_insn() 398 emit_a64_mov_i(is64, tmp, imm, ctx); build_insn() 399 emit(A64_ADD(is64, dst, dst, tmp), ctx); build_insn() 404 emit_a64_mov_i(is64, tmp, imm, ctx); build_insn() 405 emit(A64_SUB(is64, dst, dst, tmp), ctx); build_insn() 410 emit_a64_mov_i(is64, tmp, imm, ctx); build_insn() 411 emit(A64_AND(is64, dst, dst, tmp), ctx); build_insn() 416 emit_a64_mov_i(is64, tmp, imm, ctx); build_insn() 417 emit(A64_ORR(is64, dst, dst, tmp), ctx); build_insn() 422 emit_a64_mov_i(is64, tmp, imm, ctx); build_insn() 423 emit(A64_EOR(is64, dst, dst, tmp), ctx); build_insn() 428 emit_a64_mov_i(is64, tmp, imm, ctx); build_insn() 429 emit(A64_MUL(is64, dst, dst, tmp), ctx); build_insn() 434 emit_a64_mov_i(is64, tmp, imm, ctx); build_insn() 435 emit(A64_UDIV(is64, dst, dst, tmp), ctx); build_insn() 441 emit(A64_UDIV(is64, tmp, dst, tmp2), ctx); build_insn() 442 emit(A64_MUL(is64, tmp, tmp, tmp2), ctx); build_insn() 443 emit(A64_SUB(is64, dst, dst, tmp), ctx); build_insn() 510 emit_a64_mov_i(1, tmp, imm, ctx); build_insn() 511 emit(A64_CMP(1, dst, tmp), ctx); build_insn() 515 emit_a64_mov_i(1, tmp, imm, ctx); build_insn() 516 emit(A64_TST(1, dst, tmp), ctx); build_insn() 525 emit_a64_mov_i64(tmp, func, ctx); build_insn() 528 emit(A64_BLR(tmp), ctx); build_insn() 571 emit_a64_mov_i(1, tmp, off, ctx); build_insn() 574 emit(A64_LDR32(dst, src, tmp), ctx); build_insn() 577 emit(A64_LDRH(dst, src, tmp), ctx); build_insn() 580 emit(A64_LDRB(dst, src, tmp), ctx); build_insn() 583 emit(A64_LDR64(dst, src, tmp), ctx); build_insn() 596 emit_a64_mov_i(1, tmp, imm, ctx); build_insn() 599 emit(A64_STR32(tmp, dst, tmp2), ctx); build_insn() 602 emit(A64_STRH(tmp, dst, tmp2), ctx); build_insn() 605 emit(A64_STRB(tmp, dst, tmp2), ctx); build_insn() 608 emit(A64_STR64(tmp, dst, tmp2), ctx); build_insn() 619 emit_a64_mov_i(1, tmp, off, ctx); build_insn() 622 emit(A64_STR32(src, dst, tmp), ctx); build_insn() 625 emit(A64_STRH(src, dst, tmp), ctx); build_insn() 628 emit(A64_STRB(src, dst, tmp), ctx); build_insn() 631 emit(A64_STR64(src, dst, tmp), ctx); build_insn()
/linux-4.4.14/drivers/mmc/host/
H A D	sdhci-pxav2.c	62 u16 tmp = 0; pxav2_reset() local 69 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); pxav2_reset() 71 tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT); pxav2_reset() 72 tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) pxav2_reset() 74 tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT); pxav2_reset() 75 tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT; pxav2_reset() 77 writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); pxav2_reset() 81 tmp = readw(host->ioaddr + SD_FIFO_PARAM); pxav2_reset() 82 tmp &= ~CLK_GATE_SETTING_BITS; pxav2_reset() 83 writew(tmp, host->ioaddr + SD_FIFO_PARAM); pxav2_reset() 85 tmp = readw(host->ioaddr + SD_FIFO_PARAM); pxav2_reset() 86 tmp &= ~CLK_GATE_SETTING_BITS; pxav2_reset() 87 tmp |= CLK_GATE_SETTING_BITS; pxav2_reset() 88 writew(tmp, host->ioaddr + SD_FIFO_PARAM); pxav2_reset() 96 u16 tmp; pxav2_mmc_set_bus_width() local 99 tmp = readw(host->ioaddr + SD_CE_ATA_2); pxav2_mmc_set_bus_width() 102 tmp |= MMC_CARD | MMC_WIDTH; pxav2_mmc_set_bus_width() 104 tmp &= ~(MMC_CARD | MMC_WIDTH); pxav2_mmc_set_bus_width() 110 writew(tmp, host->ioaddr + SD_CE_ATA_2); pxav2_mmc_set_bus_width()
/linux-4.4.14/include/linux/
H A D	rbtree_augmented.h	141 struct rb_node *tmp = node->rb_left; __rb_erase_augmented() local 145 if (!tmp) { __rb_erase_augmented() 161 tmp = parent; __rb_erase_augmented() 164 tmp->__rb_parent_color = pc = node->__rb_parent_color; __rb_erase_augmented() 166 __rb_change_child(node, tmp, parent, root); __rb_erase_augmented() 168 tmp = parent; __rb_erase_augmented() 172 tmp = child->rb_left; __rb_erase_augmented() 173 if (!tmp) { __rb_erase_augmented() 204 successor = tmp; __rb_erase_augmented() 205 tmp = tmp->rb_left; __rb_erase_augmented() 206 } while (tmp); __rb_erase_augmented() 216 tmp = node->rb_left; __rb_erase_augmented() 217 WRITE_ONCE(successor->rb_left, tmp); __rb_erase_augmented() 218 rb_set_parent(tmp, successor); __rb_erase_augmented() 221 tmp = __rb_parent(pc); __rb_erase_augmented() 222 __rb_change_child(node, successor, tmp, root); __rb_erase_augmented() 233 tmp = successor; __rb_erase_augmented() 236 augment->propagate(tmp, NULL); __rb_erase_augmented()
/linux-4.4.14/drivers/staging/lustre/lustre/libcfs/
H A D	prng.c	113 int rem, tmp; cfs_get_random_bytes() local 119 get_random_bytes(&tmp, sizeof(tmp)); cfs_get_random_bytes() 120 tmp ^= cfs_rand(); cfs_get_random_bytes() 121 memcpy(buf, &tmp, rem); cfs_get_random_bytes() 127 get_random_bytes(&tmp, sizeof(tmp)); cfs_get_random_bytes() 128 *p = cfs_rand() ^ tmp; cfs_get_random_bytes() 134 get_random_bytes(&tmp, sizeof(tmp)); cfs_get_random_bytes() 135 tmp ^= cfs_rand(); cfs_get_random_bytes() 136 memcpy(buf, &tmp, size); cfs_get_random_bytes()
/linux-4.4.14/drivers/media/pci/ttpci/
H A D	ttpci-eeprom.c	53 u16 tmp = 0xffff; check_mac_tt() local 56 tmp = (tmp << 8) | ((tmp >> 8) ^ buf[i]); check_mac_tt() 57 tmp ^= (tmp >> 4) & 0x0f; check_mac_tt() 58 tmp ^= (tmp << 12) ^ ((tmp & 0xff) << 5); check_mac_tt() 60 tmp ^= 0xffff; check_mac_tt() 61 return (((tmp >> 8) ^ buf[8]) | ((tmp & 0xff) ^ buf[9])); check_mac_tt()
/linux-4.4.14/drivers/net/phy/
H A D	bcm-phy-lib.c	57 int tmp; bcm_phy_write_misc() local 64 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL); bcm_phy_write_misc() 65 tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA; bcm_phy_write_misc() 66 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); bcm_phy_write_misc() 70 tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg; bcm_phy_write_misc() 71 rc = bcm_phy_write_exp(phydev, tmp, val); bcm_phy_write_misc() 81 int tmp; bcm_phy_read_misc() local 88 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL); bcm_phy_read_misc() 89 tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA; bcm_phy_read_misc() 90 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); bcm_phy_read_misc() 94 tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg; bcm_phy_read_misc() 95 rc = bcm_phy_read_exp(phydev, tmp); bcm_phy_read_misc()
/linux-4.4.14/arch/x86/crypto/
H A D	glue_helper-asm-avx.S	48 #define inc_le128(x, minus_one, tmp) \ 49 vpcmpeqq minus_one, x, tmp; \ 51 vpslldq $8, tmp, tmp; \ 52 vpsubq tmp, x, x; 93 #define gf128mul_x_ble(iv, mask, tmp) \ 94 vpsrad $31, iv, tmp; \ 96 vpshufd $0x13, tmp, tmp; \ 97 vpand mask, tmp, tmp; \ 98 vpxor tmp, iv, iv;
/linux-4.4.14/drivers/clk/
H A D	clk-clps711x.c	51 u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi; _clps711x_clk_init() local 65 tmp = readl(base + CLPS711X_PLLR) >> 24; _clps711x_clk_init() 66 if (((tmp >= 10) && (tmp <= 50)) || !fref) _clps711x_clk_init() 67 f_pll = DIV_ROUND_UP(CLPS711X_OSC_FREQ * tmp, 2); _clps711x_clk_init() 71 tmp = readl(base + CLPS711X_SYSFLG2); _clps711x_clk_init() 72 if (tmp & SYSFLG2_CKMODE) { _clps711x_clk_init() 88 if (tmp & SYSFLG2_CKMODE) { _clps711x_clk_init() 96 tmp = readl(base + CLPS711X_SYSCON1); _clps711x_clk_init() 101 tmp &= ~(SYSCON1_TC1M | SYSCON1_TC1S); _clps711x_clk_init() 106 tmp |= SYSCON1_TC2M | SYSCON1_TC2S; _clps711x_clk_init() 107 writel(tmp, base + CLPS711X_SYSCON1); _clps711x_clk_init()
/linux-4.4.14/arch/c6x/kernel/
H A D	time.c	54 u64 tmp = (u64)NSEC_PER_SEC << SCHED_CLOCK_SHIFT; time_init() local 56 do_div(tmp, c6x_core_freq); time_init() 57 sched_clock_multiplier = tmp; time_init()
/linux-4.4.14/arch/powerpc/kernel/
H A D	io.c	34 u8 tmp; _insb() local 40 tmp = *port; _insb() 42 *tbuf++ = tmp; _insb() 44 asm volatile("twi 0,%0,0; isync" : : "r" (tmp)); _insb() 65 u16 tmp; _insw_ns() local 71 tmp = *port; _insw_ns() 73 *tbuf++ = tmp; _insw_ns() 75 asm volatile("twi 0,%0,0; isync" : : "r" (tmp)); _insw_ns() 96 u32 tmp; _insl_ns() local 102 tmp = *port; _insl_ns() 104 *tbuf++ = tmp; _insl_ns() 106 asm volatile("twi 0,%0,0; isync" : : "r" (tmp)); _insl_ns()
/linux-4.4.14/arch/mips/mm/
H A D	sc-mips.c	131 unsigned int tmp; mips_sc_is_activated() local 148 tmp = (config2 >> 4) & 0x0f; mips_sc_is_activated() 149 if (0 < tmp && tmp <= 7) mips_sc_is_activated() 150 c->scache.linesz = 2 << tmp; mips_sc_is_activated() 197 unsigned int tmp; mips_sc_probe() local 227 tmp = (config2 >> 8) & 0x0f; mips_sc_probe() 228 if (tmp <= 7) mips_sc_probe() 229 c->scache.sets = 64 << tmp; mips_sc_probe() 233 tmp = (config2 >> 0) & 0x0f; mips_sc_probe() 234 if (tmp <= 7) mips_sc_probe() 235 c->scache.ways = tmp + 1; mips_sc_probe()
/linux-4.4.14/arch/mips/sibyte/swarm/
H A D	rtc_xicor1241.c	115 int tmp; xicor_set_time() local 142 tmp = tm.tm_year / 100; xicor_set_time() 145 xicor_write(X1241REG_Y2K, tmp); xicor_set_time() 148 tmp = xicor_read(X1241REG_HR); xicor_set_time() 149 if (tmp & X1241REG_HR_MIL) { xicor_set_time() 152 tmp = (tmp & ~0x3f) | (tm.tm_hour & 0x3f); xicor_set_time() 155 tmp = tmp & ~0x3f; xicor_set_time() 157 tmp |= 0x20; xicor_set_time() 161 tmp |= tm.tm_hour; xicor_set_time() 163 xicor_write(X1241REG_HR, tmp); xicor_set_time()
/linux-4.4.14/virt/lib/
H A D	irqbypass.c	89 struct irq_bypass_producer *tmp; irq_bypass_register_producer() local 99 list_for_each_entry(tmp, &producers, node) { irq_bypass_register_producer() 100 if (tmp->token == producer->token) { irq_bypass_register_producer() 136 struct irq_bypass_producer *tmp; irq_bypass_unregister_producer() local 146 list_for_each_entry(tmp, &producers, node) { irq_bypass_unregister_producer() 147 if (tmp->token != producer->token) irq_bypass_unregister_producer() 177 struct irq_bypass_consumer *tmp; irq_bypass_register_consumer() local 190 list_for_each_entry(tmp, &consumers, node) { irq_bypass_register_consumer() 191 if (tmp->token == consumer->token) { irq_bypass_register_consumer() 227 struct irq_bypass_consumer *tmp; irq_bypass_unregister_consumer() local 237 list_for_each_entry(tmp, &consumers, node) { irq_bypass_unregister_consumer() 238 if (tmp->token != consumer->token) irq_bypass_unregister_consumer()
/linux-4.4.14/drivers/gpu/drm/cirrus/
H A D	cirrus_mode.c	110 u8 tmp; cirrus_set_start_address() local 117 tmp = RREG8(CRT_DATA); cirrus_set_start_address() 118 tmp &= 0xf2; cirrus_set_start_address() 119 tmp |= (addr >> 16) & 0x01; cirrus_set_start_address() 120 tmp |= (addr >> 15) & 0x0c; cirrus_set_start_address() 121 WREG_CRT(0x1b, tmp); cirrus_set_start_address() 123 tmp = RREG8(CRT_DATA); cirrus_set_start_address() 124 tmp &= 0x7f; cirrus_set_start_address() 125 tmp |= (addr >> 12) & 0x80; cirrus_set_start_address() 126 WREG_CRT(0x1d, tmp); cirrus_set_start_address() 202 int tmp; cirrus_crtc_mode_set() local 229 tmp = 0x40; cirrus_crtc_mode_set() 231 tmp |= 0x20; cirrus_crtc_mode_set() 232 WREG_CRT(VGA_CRTC_MAX_SCAN, tmp); cirrus_crtc_mode_set() 237 tmp = 16; cirrus_crtc_mode_set() 239 tmp |= 1; cirrus_crtc_mode_set() 241 tmp |= 2; cirrus_crtc_mode_set() 243 tmp |= 8; cirrus_crtc_mode_set() 245 tmp |= 32; cirrus_crtc_mode_set() 247 tmp |= 64; cirrus_crtc_mode_set() 248 WREG_CRT(VGA_CRTC_OVERFLOW, tmp); cirrus_crtc_mode_set() 250 tmp = 0; cirrus_crtc_mode_set() 255 tmp |= 16; cirrus_crtc_mode_set() 257 tmp |= 32; cirrus_crtc_mode_set() 259 tmp |= 64; cirrus_crtc_mode_set() 261 tmp |= 128; cirrus_crtc_mode_set() 263 WREG_CRT(CL_CRT1A, tmp); cirrus_crtc_mode_set() 295 tmp = crtc->primary->fb->pitches[0] / 8; cirrus_crtc_mode_set() 296 WREG_CRT(VGA_CRTC_OFFSET, tmp); cirrus_crtc_mode_set() 299 tmp = 0x22; cirrus_crtc_mode_set() 300 tmp |= (crtc->primary->fb->pitches[0] >> 7) & 0x10; cirrus_crtc_mode_set() 301 tmp |= (crtc->primary->fb->pitches[0] >> 6) & 0x40; cirrus_crtc_mode_set() 302 WREG_CRT(0x1b, tmp); cirrus_crtc_mode_set()
/linux-4.4.14/drivers/bcma/
H A D	driver_chipcommon_pmu.c	341 u32 tmp, div, ndiv, p1, p2, fc; bcma_pmu_pll_clock() local 351 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); bcma_pmu_pll_clock() 352 if (tmp & 0x40000) bcma_pmu_pll_clock() 356 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); bcma_pmu_pll_clock() 357 p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT; bcma_pmu_pll_clock() 358 p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT; bcma_pmu_pll_clock() 360 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF); bcma_pmu_pll_clock() 361 div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) & bcma_pmu_pll_clock() 364 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF); bcma_pmu_pll_clock() 365 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT; bcma_pmu_pll_clock() 377 u32 tmp, ndiv, p1div, p2div; bcma_pmu_pll_clock_bcm4706() local 383 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF); bcma_pmu_pll_clock_bcm4706() 384 ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK) bcma_pmu_pll_clock_bcm4706() 386 p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK) bcma_pmu_pll_clock_bcm4706() 388 p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK) bcma_pmu_pll_clock_bcm4706() 391 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); bcma_pmu_pll_clock_bcm4706() 392 if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION) bcma_pmu_pll_clock_bcm4706() 481 u32 tmp = 0; bcma_pmu_spuravoid_pllupdate() local 502 tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); bcma_pmu_spuravoid_pllupdate() 503 tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK)); bcma_pmu_spuravoid_pllupdate() 504 tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT); bcma_pmu_spuravoid_pllupdate() 505 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); bcma_pmu_spuravoid_pllupdate() 510 tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); bcma_pmu_spuravoid_pllupdate() 511 tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK); bcma_pmu_spuravoid_pllupdate() 512 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; bcma_pmu_spuravoid_pllupdate() 513 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); bcma_pmu_spuravoid_pllupdate() 515 tmp = BCMA_CC_PMU_CTL_PLL_UPD; bcma_pmu_spuravoid_pllupdate() 536 tmp = BCMA_CC_PMU_CTL_PLL_UPD; bcma_pmu_spuravoid_pllupdate() 569 tmp = BCMA_CC_PMU_CTL_PLL_UPD; bcma_pmu_spuravoid_pllupdate() 603 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW; bcma_pmu_spuravoid_pllupdate() 641 tmp = BCMA_CC_PMU_CTL_PLL_UPD; bcma_pmu_spuravoid_pllupdate() 649 tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL); bcma_pmu_spuravoid_pllupdate() 650 bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp); bcma_pmu_spuravoid_pllupdate()

Completed in 7569 milliseconds

1234567891011>>