1/*
2 * The ARM LDRD and Thumb LDRSB instructions use bit 20/11 (ARM/Thumb)
3 * differently than every other instruction, so it is set to 0 (write)
4 * even though the instructions are read instructions. This means that
5 * during an abort the instructions will be treated as a write and the
6 * handler will raise a signal from unwriteable locations if they
7 * fault. We have to specifically check for these instructions
8 * from the abort handlers to treat them properly.
9 *
10 */
11
12	.macro	do_thumb_abort, fsr, pc, psr, tmp
13	tst	\psr, #PSR_T_BIT
14	beq	not_thumb
15	ldrh	\tmp, [\pc]			@ Read aborted Thumb instruction
16	uaccess_disable ip			@ disable userspace access
17	and	\tmp, \tmp, # 0xfe00		@ Mask opcode field
18	cmp	\tmp, # 0x5600			@ Is it ldrsb?
19	orreq	\tmp, \tmp, #1 << 11		@ Set L-bit if yes
20	tst	\tmp, #1 << 11			@ L = 0 -> write
21	orreq	\fsr, \fsr, #1 << 11		@ yes.
22	b	do_DataAbort
23not_thumb:
24	.endm
25
26/*
27 * We check for the following instruction encoding for LDRD.
28 *
29 * [27:25] == 000
30 *   [7:4] == 1101
31 *    [20] == 0
32 */
33	.macro	teq_ldrd, tmp, insn
34	mov	\tmp, #0x0e100000
35	orr	\tmp, #0x000000f0
36	and	\tmp, \insn, \tmp
37	teq	\tmp, #0x000000d0
38	.endm
39