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Searched refs:wptr (Results 1 – 44 of 44) sorted by relevance

/linux-4.1.27/drivers/media/usb/pvrusb2/
Dpvrusb2-debugifc.c69 const char *wptr; in debugifc_isolate_word() local
74 wptr = NULL; in debugifc_isolate_word()
82 wptr = buf; in debugifc_isolate_word()
87 *wstrPtr = wptr; in debugifc_isolate_word()
198 const char *wptr; in pvr2_debugifc_do1cmd() local
202 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); in pvr2_debugifc_do1cmd()
205 if (!wptr) return 0; in pvr2_debugifc_do1cmd()
207 pvr2_trace(PVR2_TRACE_DEBUGIFC,"debugifc cmd: \"%.*s\"",wlen,wptr); in pvr2_debugifc_do1cmd()
208 if (debugifc_match_keyword(wptr,wlen,"reset")) { in pvr2_debugifc_do1cmd()
209 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); in pvr2_debugifc_do1cmd()
[all …]
/linux-4.1.27/drivers/gpu/drm/radeon/
Dvce_v1_0.c80 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_set_wptr()
82 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_set_wptr()
101 WREG32(VCE_RB_RPTR, ring->wptr); in vce_v1_0_start()
102 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_start()
108 WREG32(VCE_RB_RPTR2, ring->wptr); in vce_v1_0_start()
109 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_start()
Dradeon_ring.c84 ring->ring_free_dw -= ring->wptr; in radeon_ring_free_size()
125 ring->wptr_old = ring->wptr; in radeon_ring_alloc()
173 while (ring->wptr & ring->align_mask) { in radeon_ring_commit()
211 ring->wptr = ring->wptr_old; in radeon_ring_undo()
308 size = ring->wptr + (ring->ring_size / 4); in radeon_ring_backup()
468 uint32_t rptr, wptr, rptr_next; in radeon_debugfs_ring_info() local
474 wptr = radeon_ring_get_wptr(rdev, ring); in radeon_debugfs_ring_info()
476 wptr, wptr); in radeon_debugfs_ring_info()
490 ring->wptr, ring->wptr); in radeon_debugfs_ring_info()
Dr600_dma.c89 WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc); in r600_dma_set_wptr()
167 ring->wptr = 0; in r600_dma_resume()
168 WREG32(DMA_RB_WPTR, ring->wptr << 2); in r600_dma_resume()
405 u32 next_rptr = ring->wptr + 4; in r600_dma_ring_ib_execute()
418 while ((ring->wptr & 7) != 5) in r600_dma_ring_ib_execute()
Dni_dma.c111 WREG32(reg, (ring->wptr << 2) & 0x3fffc); in cayman_dma_set_wptr()
129 u32 next_rptr = ring->wptr + 4; in cayman_dma_ring_ib_execute()
142 while ((ring->wptr & 7) != 5) in cayman_dma_ring_ib_execute()
243 ring->wptr = 0; in cayman_dma_resume()
244 WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2); in cayman_dma_resume()
Devergreen_dma.c73 u32 next_rptr = ring->wptr + 4; in evergreen_dma_ring_ib_execute()
86 while ((ring->wptr & 7) != 5) in evergreen_dma_ring_ib_execute()
Duvd_v1_0.c70 WREG32(UVD_RBC_RB_WPTR, ring->wptr); in uvd_v1_0_set_wptr()
369 ring->wptr = RREG32(UVD_RBC_RB_RPTR); in uvd_v1_0_start()
370 WREG32(UVD_RBC_RB_WPTR, ring->wptr); in uvd_v1_0_start()
Dni.c1418 uint32_t next_rptr = ring->wptr + 3 + 4 + 8; in cayman_ring_ib_execute()
1477 u32 wptr; in cayman_gfx_get_wptr() local
1480 wptr = RREG32(CP_RB0_WPTR); in cayman_gfx_get_wptr()
1482 wptr = RREG32(CP_RB1_WPTR); in cayman_gfx_get_wptr()
1484 wptr = RREG32(CP_RB2_WPTR); in cayman_gfx_get_wptr()
1486 return wptr; in cayman_gfx_get_wptr()
1493 WREG32(CP_RB0_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1496 WREG32(CP_RB1_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1499 WREG32(CP_RB2_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1699 ring->wptr = 0; in cayman_cp_resume()
[all …]
Dcik_sdma.c121 WREG32(reg, (ring->wptr << 2) & 0x3fffc); in cik_sdma_set_wptr()
140 u32 next_rptr = ring->wptr + 5; in cik_sdma_ring_ib_execute()
152 while ((ring->wptr & 7) != 4) in cik_sdma_ring_ib_execute()
411 ring->wptr = 0; in cik_sdma_gfx_resume()
412 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2); in cik_sdma_gfx_resume()
Dr600.c2580 u32 wptr; in r600_gfx_get_wptr() local
2582 wptr = RREG32(R600_CP_RB_WPTR); in r600_gfx_get_wptr()
2584 return wptr; in r600_gfx_get_wptr()
2590 WREG32(R600_CP_RB_WPTR, ring->wptr); in r600_gfx_set_wptr()
2694 ring->wptr = 0; in r600_cp_resume()
2695 WREG32(CP_RB_WPTR, ring->wptr); in r600_cp_resume()
3285 next_rptr = ring->wptr + 3 + 4; in r600_ring_ib_execute()
3291 next_rptr = ring->wptr + 5 + 4; in r600_ring_ib_execute()
3946 u32 wptr, tmp; in r600_get_ih_wptr() local
3949 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); in r600_get_ih_wptr()
[all …]
Dradeon_kfd.c71 uint32_t queue_id, uint32_t __user *wptr);
433 uint32_t queue_id, uint32_t __user *wptr) in kgd_hqd_load() argument
440 is_wptr_shadow_valid = !get_user(wptr_shadow, wptr); in kgd_hqd_load()
Dcik.c4131 next_rptr = ring->wptr + 3 + 4; in cik_ring_ib_execute()
4137 next_rptr = ring->wptr + 5 + 4; in cik_ring_ib_execute()
4472 ring->wptr = 0; in cik_cp_gfx_resume()
4473 WREG32(CP_RB0_WPTR, ring->wptr); in cik_cp_gfx_resume()
4523 u32 wptr; in cik_gfx_get_wptr() local
4525 wptr = RREG32(CP_RB0_WPTR); in cik_gfx_get_wptr()
4527 return wptr; in cik_gfx_get_wptr()
4533 WREG32(CP_RB0_WPTR, ring->wptr); in cik_gfx_set_wptr()
4558 u32 wptr; in cik_compute_get_wptr() local
4562 wptr = rdev->wb.wb[ring->wptr_offs/4]; in cik_compute_get_wptr()
[all …]
Dsi.c3413 next_rptr = ring->wptr + 3 + 4 + 8; in si_ring_ib_execute()
3419 next_rptr = ring->wptr + 5 + 4 + 8; in si_ring_ib_execute()
3672 ring->wptr = 0; in si_cp_resume()
3673 WREG32(CP_RB0_WPTR, ring->wptr); in si_cp_resume()
3703 ring->wptr = 0; in si_cp_resume()
3704 WREG32(CP_RB1_WPTR, ring->wptr); in si_cp_resume()
3727 ring->wptr = 0; in si_cp_resume()
3728 WREG32(CP_RB2_WPTR, ring->wptr); in si_cp_resume()
6395 u32 wptr, tmp; in si_get_ih_wptr() local
6398 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); in si_get_ih_wptr()
[all …]
Devergreen.c2981 next_rptr = ring->wptr + 3 + 4; in evergreen_ring_ib_execute()
2987 next_rptr = ring->wptr + 5 + 4; in evergreen_ring_ib_execute()
3139 ring->wptr = 0; in evergreen_cp_resume()
3140 WREG32(CP_RB_WPTR, ring->wptr); in evergreen_cp_resume()
4964 u32 wptr, tmp; in evergreen_get_ih_wptr() local
4967 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); in evergreen_get_ih_wptr()
4969 wptr = RREG32(IH_RB_WPTR); in evergreen_get_ih_wptr()
4971 if (wptr & RB_OVERFLOW) { in evergreen_get_ih_wptr()
4972 wptr &= ~RB_OVERFLOW; in evergreen_get_ih_wptr()
4978 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); in evergreen_get_ih_wptr()
[all …]
Dr100.c1072 u32 wptr; in r100_gfx_get_wptr() local
1074 wptr = RREG32(RADEON_CP_RB_WPTR); in r100_gfx_get_wptr()
1076 return wptr; in r100_gfx_get_wptr()
1082 WREG32(RADEON_CP_RB_WPTR, ring->wptr); in r100_gfx_set_wptr()
1182 ring->wptr = 0; in r100_cp_init()
1183 WREG32(RADEON_CP_RB_WPTR, ring->wptr); in r100_cp_init()
3681 u32 next_rptr = ring->wptr + 2 + 3; in r100_ring_ib_execute()
Dradeon.h855 unsigned wptr; member
2864 ring->ring[ring->wptr++] = v; in radeon_ring_write()
2865 ring->wptr &= ring->ptr_mask; in radeon_ring_write()
/linux-4.1.27/drivers/net/ppp/
Dbsd_comp.c580 unsigned char *wptr; in bsd_compress() local
586 if (wptr) \ in bsd_compress()
588 *wptr++ = (unsigned char) (v); \ in bsd_compress()
591 wptr = NULL; \ in bsd_compress()
630 wptr = obuf; in bsd_compress()
639 if (wptr) in bsd_compress()
641 *wptr++ = PPP_ADDRESS(rptr); in bsd_compress()
642 *wptr++ = PPP_CONTROL(rptr); in bsd_compress()
643 *wptr++ = 0; in bsd_compress()
644 *wptr++ = PPP_COMP; in bsd_compress()
[all …]
Dppp_deflate.c193 unsigned char *wptr; in z_compress() local
207 wptr = obuf; in z_compress()
212 wptr[0] = PPP_ADDRESS(rptr); in z_compress()
213 wptr[1] = PPP_CONTROL(rptr); in z_compress()
214 put_unaligned_be16(PPP_COMP, wptr + 2); in z_compress()
215 wptr += PPP_HDRLEN; in z_compress()
216 put_unaligned_be16(state->seqno, wptr); in z_compress()
217 wptr += DEFLATE_OVHD; in z_compress()
219 state->strm.next_out = wptr; in z_compress()
/linux-4.1.27/drivers/gpu/drm/amd/amdkfd/
Dkfd_kernel_queue.c208 uint32_t wptr, rptr; in acquire_packet_buffer() local
214 wptr = *kq->wptr_kernel; in acquire_packet_buffer()
219 __func__, rptr, wptr, queue_address); in acquire_packet_buffer()
221 available_size = (rptr - 1 - wptr + queue_size_dwords) % in acquire_packet_buffer()
234 if (wptr + packet_size_in_dwords >= queue_size_dwords) { in acquire_packet_buffer()
235 while (wptr > 0) { in acquire_packet_buffer()
236 queue_address[wptr] = kq->nop_packet; in acquire_packet_buffer()
237 wptr = (wptr + 1) % queue_size_dwords; in acquire_packet_buffer()
241 *buffer_ptr = &queue_address[wptr]; in acquire_packet_buffer()
242 kq->pending_wptr = wptr + packet_size_in_dwords; in acquire_packet_buffer()
Dkfd_mqd_manager.h70 uint32_t __user *wptr);
Dkfd_mqd_manager_cik.c152 uint32_t queue_id, uint32_t __user *wptr) in load_mqd() argument
155 (mm->dev->kgd, mqd, pipe_id, queue_id, wptr); in load_mqd()
160 uint32_t __user *wptr) in load_mqd_sdma() argument
Dkfd_packet_manager.c32 static inline void inc_wptr(unsigned int *wptr, unsigned int increment_bytes, in inc_wptr() argument
35 unsigned int temp = *wptr + increment_bytes / sizeof(uint32_t); in inc_wptr()
38 *wptr = temp; in inc_wptr()
/linux-4.1.27/drivers/net/ethernet/tehuti/
Dtehuti.c172 f->wptr = 0; in bdx_fifo_init()
1116 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); in bdx_rx_alloc_skbs()
1124 f->m.wptr += sizeof(struct rxf_desc); in bdx_rx_alloc_skbs()
1125 delta = f->m.wptr - f->m.memsz; in bdx_rx_alloc_skbs()
1127 f->m.wptr = delta; in bdx_rx_alloc_skbs()
1136 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); in bdx_rx_alloc_skbs()
1173 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); in bdx_recycle_skb()
1181 f->m.wptr += sizeof(struct rxf_desc); in bdx_recycle_skb()
1182 delta = f->m.wptr - f->m.memsz; in bdx_recycle_skb()
1184 f->m.wptr = delta; in bdx_recycle_skb()
[all …]
Dtehuti.h146 u32 rptr, wptr; /* cached values of RPTR and WPTR registers, member
202 struct tx_map *wptr; /* points to the next element to write */ member
/linux-4.1.27/drivers/gpu/drm/msm/adreno/
Dadreno_gpu.c112 adreno_gpu->memptrs->wptr = 0; in adreno_recover()
196 uint32_t wptr = get_wptr(gpu->rb); in adreno_flush() local
201 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr); in adreno_flush()
207 uint32_t wptr = get_wptr(gpu->rb); in adreno_idle() local
210 if (spin_until(adreno_gpu->memptrs->rptr == wptr)) in adreno_idle()
230 seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr); in adreno_show()
266 printk("wptr: %d\n", adreno_gpu->memptrs->wptr); in adreno_dump()
287 uint32_t wptr = get_wptr(gpu->rb); in ring_freewords() local
289 return (rptr + (size - 1) - wptr) % size; in ring_freewords()
Dadreno_gpu.h132 volatile uint32_t wptr; member
/linux-4.1.27/drivers/video/fbdev/
Dmaxinefb.c67 unsigned char *wptr; in maxinefb_ims332_write_register() local
69 wptr = regs + 0xa0000 + (regno << 4); in maxinefb_ims332_write_register()
71 *((volatile unsigned short *) (wptr)) = val; in maxinefb_ims332_write_register()
/linux-4.1.27/drivers/infiniband/hw/cxgb3/
Dcxio_hal.c609 __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len, in cxio_hal_ctrl_qp_write_mem()
613 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr, in cxio_hal_ctrl_qp_write_mem()
617 rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i); in cxio_hal_ctrl_qp_write_mem()
620 rdev_p->ctrl_qp.wptr, in cxio_hal_ctrl_qp_write_mem()
629 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr % in cxio_hal_ctrl_qp_write_mem()
671 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr % in cxio_hal_ctrl_qp_write_mem()
675 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr; in cxio_hal_ctrl_qp_write_mem()
682 Q_GENBIT(rdev_p->ctrl_qp.wptr, in cxio_hal_ctrl_qp_write_mem()
688 rdev_p->ctrl_qp.wptr++; in cxio_hal_ctrl_qp_write_mem()
706 u32 wptr; in __cxio_tpt_op() local
[all …]
Dcxio_wr.h46 #define Q_EMPTY(rptr,wptr) ((rptr)==(wptr)) argument
47 #define Q_FULL(rptr,wptr,size_log2) ( (((wptr)-(rptr))>>(size_log2)) && \ argument
48 ((rptr)!=(wptr)) )
50 #define Q_FREECNT(rptr,wptr,size_log2) ((1UL<<size_log2)-((wptr)-(rptr))) argument
51 #define Q_COUNT(rptr,wptr) ((wptr)-(rptr)) argument
697 u32 wptr; /* idx to next available WR slot */ member
718 u32 wptr; member
Diwch_qp.c175 Q_PTR2IDX((wq->wptr+1), wq->size_log2)); in build_fastreg()
177 Q_GENBIT(wq->wptr + 1, wq->size_log2), in build_fastreg()
384 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2); in iwch_post_send()
443 Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2), in iwch_post_send()
452 qhp->wq.wptr += wr_cnt; in iwch_post_send()
494 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2); in iwch_post_receive()
508 Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2), in iwch_post_receive()
514 ++(qhp->wq.wptr); in iwch_post_receive()
561 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2); in iwch_bind_mw()
598 Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2), 0, in iwch_bind_mw()
[all …]
Dcxio_hal.h68 u32 wptr; member
Diwch_provider.c263 if (cqe < Q_COUNT(chp->cq.rptr, chp->cq.wptr)) { in iwch_resize_cq()
/linux-4.1.27/drivers/staging/media/lirc/
Dlirc_parallel.c85 static unsigned int wptr; variable
210 nwptr = (wptr + 1) & (RBUF_SIZE - 1); in rbuf_write()
217 rbuf[wptr] = signal; in rbuf_write()
218 wptr = nwptr; in rbuf_write()
338 if (rptr != wptr) { in lirc_read()
457 if (rptr != wptr) in lirc_poll()
524 wptr = 0; in lirc_open()
/linux-4.1.27/drivers/tty/serial/
Dmen_z135_uart.c302 u32 wptr; in men_z135_handle_tx() local
324 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); in men_z135_handle_tx()
325 txc = (wptr >> 16) & 0x3ff; in men_z135_handle_tx()
326 wptr &= 0x3ff; in men_z135_handle_tx()
342 if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr)) in men_z135_handle_tx()
343 n = 4 - BYTES_TO_ALIGN(wptr); in men_z135_handle_tx()
464 u32 wptr; in men_z135_tx_empty() local
467 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); in men_z135_tx_empty()
468 txc = (wptr >> 16) & 0x3ff; in men_z135_tx_empty()
/linux-4.1.27/drivers/scsi/qla2xxx/
Dqla_sup.c550 uint16_t cnt, chksum, *wptr; in qla2xxx_find_flt_start() local
611 wptr = (uint16_t *)req->ring; in qla2xxx_find_flt_start()
614 chksum += le16_to_cpu(*wptr++); in qla2xxx_find_flt_start()
668 uint16_t *wptr; in qla2xxx_get_flt_info() local
689 wptr = (uint16_t *)req->ring; in qla2xxx_get_flt_info()
694 if (*wptr == __constant_cpu_to_le16(0xffff)) in qla2xxx_get_flt_info()
706 chksum += le16_to_cpu(*wptr++); in qla2xxx_get_flt_info()
884 uint16_t *wptr; in qla2xxx_get_fdt_info() local
891 wptr = (uint16_t *)req->ring; in qla2xxx_get_fdt_info()
895 if (*wptr == __constant_cpu_to_le16(0xffff)) in qla2xxx_get_fdt_info()
[all …]
Dqla_isr.c266 uint16_t __iomem *wptr; in qla2x00_mbx_completion() local
281 wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1); in qla2x00_mbx_completion()
285 wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8); in qla2x00_mbx_completion()
287 ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr); in qla2x00_mbx_completion()
289 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); in qla2x00_mbx_completion()
291 wptr++; in qla2x00_mbx_completion()
304 uint16_t __iomem *wptr; in qla81xx_idc_event() local
309 wptr = (uint16_t __iomem *)&reg24->mailbox1; in qla81xx_idc_event()
311 wptr = (uint16_t __iomem *)&reg82->mailbox_out[1]; in qla81xx_idc_event()
315 for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++) in qla81xx_idc_event()
[all …]
Dqla_mr.c2869 uint32_t __iomem *wptr; in qlafx00_mbx_completion() local
2879 wptr = (uint32_t __iomem *)&reg->mailbox17; in qlafx00_mbx_completion()
2882 ha->mailbox_out32[cnt] = RD_REG_DWORD(wptr); in qlafx00_mbx_completion()
2883 wptr++; in qlafx00_mbx_completion()
Dqla_nx.c1986 uint16_t __iomem *wptr; in qla82xx_mbx_completion() local
1989 wptr = (uint16_t __iomem *)&reg->mailbox_out[1]; in qla82xx_mbx_completion()
1996 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); in qla82xx_mbx_completion()
1997 wptr++; in qla82xx_mbx_completion()
/linux-4.1.27/drivers/scsi/
Dqla1280.c608 uint16_t *wptr; in qla1280_read_nvram() local
620 wptr = (uint16_t *)&ha->nvram; in qla1280_read_nvram()
624 *wptr = qla1280_get_nvram_word(ha, cnt); in qla1280_read_nvram()
625 chksum += *wptr & 0xff; in qla1280_read_nvram()
626 chksum += (*wptr >> 8) & 0xff; in qla1280_read_nvram()
627 wptr++; in qla1280_read_nvram()
636 *wptr = qla1280_get_nvram_word(ha, cnt); in qla1280_read_nvram()
637 chksum += *wptr & 0xff; in qla1280_read_nvram()
638 chksum += (*wptr >> 8) & 0xff; in qla1280_read_nvram()
639 wptr++; in qla1280_read_nvram()
[all …]
/linux-4.1.27/drivers/tty/
Dmoxa.c275 u16 rptr, wptr, mask, len; in moxa_low_water_check() local
279 wptr = readw(ofsAddr + RXwptr); in moxa_low_water_check()
281 len = (wptr - rptr) & mask; in moxa_low_water_check()
1997 u16 rptr, wptr, mask; in MoxaPortTxQueue() local
2000 wptr = readw(ofsAddr + TXwptr); in MoxaPortTxQueue()
2002 return (wptr - rptr) & mask; in MoxaPortTxQueue()
2008 u16 rptr, wptr, mask; in MoxaPortTxFree() local
2011 wptr = readw(ofsAddr + TXwptr); in MoxaPortTxFree()
2013 return mask - ((wptr - rptr) & mask); in MoxaPortTxFree()
2019 u16 rptr, wptr, mask; in MoxaPortRxQueue() local
[all …]
/linux-4.1.27/drivers/gpu/drm/amd/include/
Dkgd_kfd_interface.h148 uint32_t queue_id, uint32_t __user *wptr);
/linux-4.1.27/drivers/scsi/qla4xxx/
Dql4_nx.c3721 uint16_t *wptr; in qla4_8xxx_get_flt_info() local
3729 wptr = (uint16_t *)ha->request_ring; in qla4_8xxx_get_flt_info()
3744 if (*wptr == __constant_cpu_to_le16(0xffff)) in qla4_8xxx_get_flt_info()
3756 chksum += le16_to_cpu(*wptr++); in qla4_8xxx_get_flt_info()
3835 uint16_t *wptr; in qla4_82xx_get_fdt_info() local
3844 wptr = (uint16_t *)ha->request_ring; in qla4_82xx_get_fdt_info()
3849 if (*wptr == __constant_cpu_to_le16(0xffff)) in qla4_82xx_get_fdt_info()
3858 chksum += le16_to_cpu(*wptr++); in qla4_82xx_get_fdt_info()
3898 uint32_t *wptr; in qla4_82xx_get_idc_param() local
3902 wptr = (uint32_t *)ha->request_ring; in qla4_82xx_get_idc_param()
[all …]
/linux-4.1.27/drivers/net/ethernet/micrel/
Dks8851_mll.c548 static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len) in ks_inblk() argument
552 *wptr++ = (u16)ioread16(ks->hw_addr); in ks_inblk()
562 static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len) in ks_outblk() argument
566 iowrite16(*wptr++, ks->hw_addr); in ks_outblk()
/linux-4.1.27/drivers/net/ethernet/sun/
Dcassini.c4163 u32 wptr, rptr; in cas_link_timer() local
4175 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR); in cas_link_timer()
4177 if ((val == 0) && (wptr != rptr)) { in cas_link_timer()
4180 val, wptr, rptr); in cas_link_timer()