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Searched refs:train_set (Results 1 – 4 of 4) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
Datombios_dp.c259 u8 train_set[4]) in dp_get_adjust_train()
291 train_set[lane] = v | p; in dp_get_adjust_train()
550 u8 train_set[4]; member
562 0, dp_info->train_set[0]); /* sets all lanes at once */ in radeon_dp_update_vs_emph()
566 dp_info->train_set, dp_info->dp_lane_count); in radeon_dp_update_vs_emph()
677 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()
701 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()
709 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in radeon_dp_link_train_cr()
718 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()
721 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); in radeon_dp_link_train_cr()
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/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_dp.c2977 uint8_t train_set = intel_dp->train_set[0]; in intel_vlv_signal_levels() local
2981 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in intel_vlv_signal_levels()
2984 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in intel_vlv_signal_levels()
3007 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in intel_vlv_signal_levels()
3026 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in intel_vlv_signal_levels()
3041 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in intel_vlv_signal_levels()
3075 uint8_t train_set = intel_dp->train_set[0]; in intel_chv_signal_levels() local
3080 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in intel_chv_signal_levels()
3082 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in intel_chv_signal_levels()
3105 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in intel_chv_signal_levels()
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Dintel_drv.h632 uint8_t train_set[4]; member
/linux-4.1.27/drivers/gpu/drm/gma500/
Dcdv_intel_dp.c270 uint8_t train_set[4]; member
1330 intel_dp->train_set[lane] = v | p; in cdv_intel_get_adjust_train()
1421 intel_dp->train_set, in cdv_intel_dplink_set_level()
1426 intel_dp->train_set[0], intel_dp->lane_count); in cdv_intel_dplink_set_level()
1526 memset(intel_dp->train_set, 0, 4); in cdv_intel_dp_start_link_train()
1538 intel_dp->train_set[0], in cdv_intel_dp_start_link_train()
1545 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); in cdv_intel_dp_start_link_train()
1566 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in cdv_intel_dp_start_link_train()
1572 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in cdv_intel_dp_start_link_train()
1578 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in cdv_intel_dp_start_link_train()
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