Searched refs:train_set (Results 1 - 4 of 4) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
H A Datombios_dp.c259 u8 train_set[4]) dp_get_adjust_train()
291 train_set[lane] = v | p; dp_get_adjust_train()
550 u8 train_set[4]; member in struct:radeon_dp_link_train_info
562 0, dp_info->train_set[0]); /* sets all lanes at once */ radeon_dp_update_vs_emph()
566 dp_info->train_set, dp_info->dp_lane_count); radeon_dp_update_vs_emph()
677 memset(dp_info->train_set, 0, 4); radeon_dp_link_train_cr()
701 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) radeon_dp_link_train_cr()
709 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { radeon_dp_link_train_cr()
718 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; radeon_dp_link_train_cr()
720 /* Compute new train_set as requested by sink */ radeon_dp_link_train_cr()
721 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); radeon_dp_link_train_cr()
730 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, radeon_dp_link_train_cr()
731 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> radeon_dp_link_train_cr()
769 /* Compute new train_set as requested by sink */ radeon_dp_link_train_ce()
770 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); radeon_dp_link_train_ce()
781 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, radeon_dp_link_train_ce()
782 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) radeon_dp_link_train_ce()
257 dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], int lane_count, u8 train_set[4]) dp_get_adjust_train() argument
/linux-4.1.27/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c270 uint8_t train_set[4]; member in struct:cdv_intel_dp
1330 intel_dp->train_set[lane] = v | p; cdv_intel_get_adjust_train()
1421 intel_dp->train_set, cdv_intel_dplink_set_level()
1426 intel_dp->train_set[0], intel_dp->lane_count); cdv_intel_dplink_set_level()
1526 memset(intel_dp->train_set, 0, 4); cdv_intel_dp_start_link_train()
1536 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ cdv_intel_dp_start_link_train()
1538 intel_dp->train_set[0], cdv_intel_dp_start_link_train()
1545 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); cdv_intel_dp_start_link_train()
1566 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) cdv_intel_dp_start_link_train()
1572 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { cdv_intel_dp_start_link_train()
1578 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; cdv_intel_dp_start_link_train()
1580 /* Compute new intel_dp->train_set as requested by target */ cdv_intel_dp_start_link_train()
1586 DRM_DEBUG_KMS("failure in DP patter 1 training, train set %x\n", intel_dp->train_set[0]); cdv_intel_dp_start_link_train()
1613 intel_dp->train_set[0], cdv_intel_dp_complete_link_train()
1622 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ cdv_intel_dp_complete_link_train()
1630 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); cdv_intel_dp_complete_link_train()
1664 /* Compute new intel_dp->train_set as requested by target */ cdv_intel_dp_complete_link_train()
/linux-4.1.27/drivers/gpu/drm/i915/
H A Dintel_dp.c2977 uint8_t train_set = intel_dp->train_set[0]; intel_vlv_signal_levels() local
2981 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { intel_vlv_signal_levels()
2984 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { intel_vlv_signal_levels()
3007 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { intel_vlv_signal_levels()
3026 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { intel_vlv_signal_levels()
3041 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { intel_vlv_signal_levels()
3075 uint8_t train_set = intel_dp->train_set[0]; intel_chv_signal_levels() local
3080 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { intel_chv_signal_levels()
3082 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { intel_chv_signal_levels()
3105 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { intel_chv_signal_levels()
3123 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { intel_chv_signal_levels()
3137 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { intel_chv_signal_levels()
3198 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK) intel_chv_signal_levels()
3200 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK) intel_chv_signal_levels()
3271 intel_dp->train_set[lane] = v | p; intel_get_adjust_train()
3275 intel_gen4_signal_levels(uint8_t train_set) intel_gen4_signal_levels() argument
3279 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { intel_gen4_signal_levels()
3294 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { intel_gen4_signal_levels()
3314 intel_gen6_edp_signal_levels(uint8_t train_set) intel_gen6_edp_signal_levels() argument
3316 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | intel_gen6_edp_signal_levels()
3342 intel_gen7_edp_signal_levels(uint8_t train_set) intel_gen7_edp_signal_levels() argument
3344 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | intel_gen7_edp_signal_levels()
3373 intel_hsw_signal_levels(uint8_t train_set) intel_hsw_signal_levels() argument
3375 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | intel_hsw_signal_levels()
3416 uint8_t train_set = intel_dp->train_set[0]; intel_dp_set_signal_levels() local
3419 signal_levels = intel_hsw_signal_levels(train_set); intel_dp_set_signal_levels()
3428 signal_levels = intel_gen7_edp_signal_levels(train_set); intel_dp_set_signal_levels()
3431 signal_levels = intel_gen6_edp_signal_levels(train_set); intel_dp_set_signal_levels()
3434 signal_levels = intel_gen4_signal_levels(train_set); intel_dp_set_signal_levels()
3451 uint8_t buf[sizeof(intel_dp->train_set) + 1]; intel_dp_set_link_train()
3466 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); intel_dp_set_link_train()
3480 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); intel_dp_reset_link_train()
3501 intel_dp->train_set, intel_dp->lane_count); intel_dp_update_link_train()
3595 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) intel_dp_start_link_train()
3611 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { intel_dp_start_link_train()
3619 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; intel_dp_start_link_train()
H A Dintel_drv.h632 uint8_t train_set[4]; member in struct:intel_dp

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