Searched refs:tiling (Results 1 – 12 of 12) sorted by relevance
65 struct tegra_bo_tiling tiling; member311 unsigned long height = window->tiling.value; in tegra_dc_setup_window()313 switch (window->tiling.mode) { in tegra_dc_setup_window()330 switch (window->tiling.mode) { in tegra_dc_setup_window()451 copy->tiling = state->tiling; in tegra_plane_atomic_duplicate_state()509 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_plane_atomic_check() local523 err = tegra_fb_get_tiling(state->fb, tiling); in tegra_plane_atomic_check()527 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_plane_atomic_check()579 window.tiling = state->tiling; in tegra_plane_atomic_update()
178 struct tegra_bo_tiling tiling; member258 struct tegra_bo_tiling *tiling);
50 struct tegra_bo_tiling *tiling) in tegra_fb_get_tiling() argument55 *tiling = fb->planes[0]->tiling; in tegra_fb_get_tiling()
47 struct tegra_bo_tiling tiling; member
674 bo->tiling.mode = mode; in tegra_gem_set_tiling()675 bo->tiling.value = value; in tegra_gem_set_tiling()696 switch (bo->tiling.mode) { in tegra_gem_get_tiling()709 args->value = bo->tiling.value; in tegra_gem_get_tiling()
279 bo->tiling.mode = TEGRA_BO_TILING_MODE_TILED; in tegra_bo_create()
60 static const char *tiling_flag(int tiling) in tiling_flag() argument62 switch (tiling) { in tiling_flag()205 err_puts(m, tiling_flag(err->tiling)); in print_error_buffers()694 err->tiling = obj->tiling_mode; in capture_bo()
2750 uint64_t tiling, uint32_t latency) in skl_wm_method2() argument2761 if (tiling == I915_FORMAT_MOD_Y_TILED || in skl_wm_method2()2762 tiling == I915_FORMAT_MOD_Yf_TILED) { in skl_wm_method2()2833 p->plane[0].tiling = fb->modifier[0]; in skl_compute_wm_pipe_parameters()2837 p->plane[0].tiling = DRM_FORMAT_MOD_NONE; in skl_compute_wm_pipe_parameters()2890 p_params->tiling, in skl_compute_plane_wm()2897 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || in skl_compute_plane_wm()2898 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) { in skl_compute_plane_wm()2926 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || in skl_compute_plane_wm()2927 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) in skl_compute_plane_wm()[all …]
260 unsigned int tiling; member502 u64 tiling; member
2563 obj->tiling_mode = plane_config->tiling; in intel_alloc_initial_plane_obj()6966 plane_config->tiling = I915_TILING_X; in i9xx_get_initial_plane_config()6977 if (plane_config->tiling) in i9xx_get_initial_plane_config()7998 u32 val, base, offset, stride_mult, tiling; in skylake_get_initial_plane_config() local8024 tiling = val & PLANE_CTL_TILED_MASK; in skylake_get_initial_plane_config()8025 switch (tiling) { in skylake_get_initial_plane_config()8030 plane_config->tiling = I915_TILING_X; in skylake_get_initial_plane_config()8040 MISSING_CASE(tiling); in skylake_get_initial_plane_config()8127 plane_config->tiling = I915_TILING_X; in ironlake_get_initial_plane_config()8141 if (plane_config->tiling) in ironlake_get_initial_plane_config()
509 u32 tiling:2; member
518 // to correctly handle tiling.