Lines Matching refs:tiling
2750 uint64_t tiling, uint32_t latency) in skl_wm_method2() argument
2761 if (tiling == I915_FORMAT_MOD_Y_TILED || in skl_wm_method2()
2762 tiling == I915_FORMAT_MOD_Yf_TILED) { in skl_wm_method2()
2833 p->plane[0].tiling = fb->modifier[0]; in skl_compute_wm_pipe_parameters()
2837 p->plane[0].tiling = DRM_FORMAT_MOD_NONE; in skl_compute_wm_pipe_parameters()
2890 p_params->tiling, in skl_compute_plane_wm()
2897 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || in skl_compute_plane_wm()
2898 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) { in skl_compute_plane_wm()
2926 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || in skl_compute_plane_wm()
2927 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) in skl_compute_plane_wm()
3366 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE; in skl_update_sprite_wm()
3372 intel_plane->wm.tiling = fb->modifier[0]; in skl_update_sprite_wm()