Searched refs:tiled (Results 1 - 36 of 36) sorted by relevance

/linux-4.1.27/include/uapi/drm/
H A Domap_drm.h38 #define OMAP_BO_TILED_MASK 0x00000f00 /* tiled mapping mask, see tiled modes */
45 /* tiled modes */
52 uint32_t bytes; /* (for non-tiled formats) */
56 } tiled; /* (for tiled formats) */ member in union:omap_gem_size
92 /* note: in case of tiled buffers, the user virtual size can be
H A Ddrm_fourcc.h137 * of the data in a plane of an FB. This can be used to express tiled/
169 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
183 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
198 * This is a tiled layout using 4Kb tiles in row-major layout.
H A Ddrm_mode.h361 * To accommodate tiled, compressed, etc formats, a per-plane
/linux-4.1.27/drivers/gpu/drm/omapdrm/
H A Domap_gem.c53 /** width/height for tiled formats (rounded up to slot boundaries) */
125 /* To deal with userspace mmap'ings of 2d tiled buffers, which (a) are
340 /* for tiled buffers, the virtual size has stride rounded up omap_gem_mmap_size()
353 /* get tiled size, returns -EINVAL if not tiled buffer */ omap_gem_tiled_size()
365 /* Normal handling for the case of faulting in non-tiled buffers */ fault_1d()
391 /* Special handling for the case of faulting in 2d tiled buffers */ fault_2d()
842 * (only valid for tiled 2d buffers)
860 /* Get tiler stride for the buffer (only valid for 2d tiled buffers) */ omap_gem_tiled_stride()
1357 /* tiled buffers are always shmem paged backed.. when they are omap_gem_new()
1370 &gsize.tiled.width, &gsize.tiled.height); omap_gem_new()
1374 gsize.tiled.width, gsize.tiled.height); omap_gem_new()
1403 omap_obj->width = gsize.tiled.width; omap_gem_new()
1404 omap_obj->height = gsize.tiled.height; omap_gem_new()
H A Domap_gem_dmabuf.c88 * get de-tiled view. For now just reject it. omap_gem_dmabuf_begin_cpu_access()
H A Domap_fbdev.c168 * (non-tiled buffer doesn't need to be pinned for fbcon to write omap_fbdev_create()
H A Domap_fb.c218 "rotation '%d' ignored for non-tiled fb\n", omap_framebuffer_update_scanout()
H A Domap_dmm_tiler.c442 * [28:27] = 0x0 for 8-bit tiled
443 * 0x1 for 16-bit tiled
444 * 0x2 for 32-bit tiled
/linux-4.1.27/drivers/gpu/drm/i915/
H A Di915_gem_tiling.c50 * memory, and it matches what the CPU does for non-tiled. However, when tiled
151 * the GPU's interleave is bit 9 and 10 for X tiled, and bit i915_gem_detect_bit_6_swizzle()
152 * 9 for Y tiled. The CPU's interleave is independent, and i915_gem_detect_bit_6_swizzle()
166 * tiled buffers. i915_gem_detect_bit_6_swizzle()
201 * swizzling for tiled objects from the CPU. i915_gem_detect_bit_6_swizzle()
H A Dintel_fbc.c585 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); intel_fbc_update()
H A Di915_gem.c1607 * is tiled) and inserting a new PTE into the faulting process.
1744 * It is vital that we remove the page mapping if we have mapped a tiled
3089 /* Adjust fence size to match tiled area */ i965_write_fence_reg()
3333 * to them without having to worry about swizzling if the object is tiled.
H A Dintel_overlay.c1109 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n"); intel_overlay_put_image()
H A Di915_drv.h841 FBC_NOT_TILED, /* buffer not tiled */
2000 /** Current tiling stride for the object, if it's tiled. */
H A Dintel_display.c2426 /* Install a fence for tiled scan-out. Pre-i965 always needs a intel_pin_and_fence_fb_obj()
2903 * chunks for linear buffers or in number of tiles for tiled intel_fb_stride_alignment()
9730 /* i965+ uses the linear or tiled offsets from the intel_gen4_queue_flip()
9928 * linear buffers or in number of tiles for tiled buffers. skl_do_mmio_flip()
12786 DRM_DEBUG_KMS("cursor cannot be tiled\n"); intel_check_cursor_plane()
13253 /* XXX DSPC is limited to 4k tiled */ intel_fb_pitch_limit()
13271 * X-tiled. This is needed for FBC. */ intel_framebuffer_init()
13317 "tiled" : "linear", intel_framebuffer_init()
H A Di915_debugfs.c1566 seq_puts(m, "scanout buffer not tiled"); i915_fbc_status()
/linux-4.1.27/drivers/media/platform/s5p-tv/
H A Dmixer_vp_layer.c62 .name = "NV12 tiled (mplane)",
H A Dmixer_reg.c243 /* TODO: fix tiled mode */ mxr_reg_vp_buffer()
/linux-4.1.27/drivers/gpu/drm/nouveau/
H A Dnouveau_drm.h17 * - added support for tiled system memory buffer objects
H A Dnouveau_bo.c1384 /* fallthrough, tiled memory */ nouveau_ttm_io_mem_reserve()
1428 /* as long as the bo isn't in vram, and isn't tiled, we've got nouveau_ttm_fault_reserve_notify()
/linux-4.1.27/drivers/gpu/drm/radeon/
H A Dradeon_fb.c96 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled) radeon_align_pitch() argument
99 int align_large = (ASIC_IS_AVIVO(rdev)) || tiled; radeon_align_pitch()
H A Dr600_cs.c2477 u32 header, cmd, count, tiled; r600_dma_cs_parse() local
2493 tiled = GET_DMA_T(header); r600_dma_cs_parse()
2502 if (tiled) { r600_dma_cs_parse()
2533 if (tiled) { r600_dma_cs_parse()
2537 /* tiled src, linear dst */ r600_dma_cs_parse()
2547 /* linear src, tiled dst */ r600_dma_cs_parse()
H A Devergreen_cs.c2785 /* tiled */ evergreen_dma_cs_parse()
2851 /* tiled src, linear dst */ evergreen_dma_cs_parse()
2861 /* linear src, tiled dst */ evergreen_dma_cs_parse()
3004 /* tiled src, linear dst */ evergreen_dma_cs_parse()
3010 /* linear src, tiled dst */ evergreen_dma_cs_parse()
3062 /* tiled src, linear dst */ evergreen_dma_cs_parse()
3072 /* linear src, tiled dst */ evergreen_dma_cs_parse()
3516 /* tiled */ evergreen_dma_ib_parse()
H A Dradeon_drv.c64 * 2.16.0 - fix evergreen 2D tiled surface calculation
H A Dradeon_mode.h995 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
H A Dradeon_state.c1769 /* we got tiled coordinates, untile them */ radeon_cp_dispatch_texture()
/linux-4.1.27/drivers/media/platform/s5p-mfc/
H A Dregs-mfc.h298 #define S5P_FIMV_ENC_MAP_FOR_CUR 0xc51c /* linear or tiled mode */
H A Ds5p_mfc_opr_v6.c694 /* 0: Linear, 1: 2D tiled*/ s5p_mfc_set_enc_params()
701 /* 0: Linear, 1: 2D tiled*/ s5p_mfc_set_enc_params()
708 /* 0: Linear, 1: 2D tiled*/ s5p_mfc_set_enc_params()
717 /* 0: Linear, 1: 2D tiled */ s5p_mfc_set_enc_params()
/linux-4.1.27/drivers/gpu/drm/savage/
H A Dsavage_drv.h227 #define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */
/linux-4.1.27/drivers/hid/
H A Dhid-picolcd_fb.c31 * This display area is tiled over 4 controllers with 8 tiles
/linux-4.1.27/drivers/media/platform/exynos4-is/
H A Dfimc-reg.c492 /* Input/output DMA linear/tiled mode. */ fimc_hw_set_in_dma()
H A Dfimc-core.c179 .name = "YUV 4:2:0 non-contig. 2p, tiled",
/linux-4.1.27/drivers/media/platform/exynos-gsc/
H A Dgsc-core.c189 .name = "YUV 4:2:0 n.c. 2p, Y/CbCr tiled",
/linux-4.1.27/drivers/video/fbdev/
H A Dgbefb.c698 The GBE hardware uses a tiled memory to screen mapping. Tiles are gbefb_set_par()
/linux-4.1.27/drivers/gpu/drm/
H A Ddrm_fb_helper.c1461 DRM_DEBUG_KMS("no modes for connector tiled %d %d\n", i, drm_get_tile_offsets()
H A Ddrm_crtc.c5549 * Tile groups are used to represent tiled monitors with a unique
/linux-4.1.27/include/drm/
H A Ddrm_crtc.h652 * @has_tile: is this connector connected to a tiled monitor

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