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Searched refs:reg_set (Results 1 – 25 of 25) sorted by relevance

/linux-4.1.27/drivers/scsi/mvsas/
Dmv_sas.h83 #define SATA_RECEIVED_FIS_LIST(reg_set) \ argument
84 ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set)
85 #define SATA_RECEIVED_SDB_FIS(reg_set) \ argument
86 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
87 #define SATA_RECEIVED_D2H_FIS(reg_set) \ argument
88 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
89 #define SATA_RECEIVED_PIO_FIS(reg_set) \ argument
90 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
91 #define SATA_RECEIVED_DMA_FIS(reg_set) \ argument
92 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)
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Dmv_94xx.c635 void mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all) in mvs_94xx_clear_srs_irq() argument
652 if (reg_set > 31) in mvs_94xx_clear_srs_irq()
657 if (tmp & (1 << (reg_set % 32))) { in mvs_94xx_clear_srs_irq()
658 mv_dprintk("register set 0x%x was stopped.\n", reg_set); in mvs_94xx_clear_srs_irq()
659 if (reg_set > 31) in mvs_94xx_clear_srs_irq()
660 mw32(MVS_INT_STAT_SRS_1, 1 << (reg_set % 32)); in mvs_94xx_clear_srs_irq()
662 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32)); in mvs_94xx_clear_srs_irq()
712 u8 reg_set = *tfs; in mvs_94xx_free_reg_set() local
717 mvi->sata_reg_set &= ~bit(reg_set); in mvs_94xx_free_reg_set()
718 if (reg_set < 32) in mvs_94xx_free_reg_set()
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Dmv_64xx.c139 void mvs_64xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all) in mvs_64xx_clear_srs_irq() argument
151 if (tmp & (1 << (reg_set % 32))) { in mvs_64xx_clear_srs_irq()
153 reg_set); in mvs_64xx_clear_srs_irq()
154 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32)); in mvs_64xx_clear_srs_irq()
Dmv_sas.c136 u8 reg_set) in mvs_find_dev_by_reg_set() argument
143 if (mvi->devices[dev_no].taskfileset == reg_set) in mvs_find_dev_by_reg_set()
/linux-4.1.27/drivers/scsi/megaraid/
Dmegaraid_sas_fusion.c104 regs = instance->reg_set; in megasas_enable_intr_fusion()
127 regs = instance->reg_set; in megasas_disable_intr_fusion()
716 if (readl(&instance->reg_set->doorbell) & 1) in megasas_ioc_init_fusion()
723 req_desc.u.high, instance->reg_set); in megasas_ioc_init_fusion()
1000 struct megasas_register_set __iomem *reg_set; in megasas_init_adapter_fusion() local
1007 reg_set = instance->reg_set; in megasas_init_adapter_fusion()
1013 instance->instancet->read_fw_status_reg(reg_set) & 0x00FFFF; in megasas_init_adapter_fusion()
1953 instance->reg_set); in megasas_build_and_issue_cmd_fusion()
2170 mfiStatus = instance->instancet->clear_intr(instance->reg_set); in megasas_isr_fusion()
2177 instance->instancet->clear_intr(instance->reg_set); in megasas_isr_fusion()
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Dmegaraid_sas_base.c164 struct megasas_register_set __iomem *reg_set);
197 cmd->frame_phys_addr, 0, instance->reg_set); in megasas_issue_dcmd()
288 regs = instance->reg_set; in megasas_enable_intr_xscale()
304 regs = instance->reg_set; in megasas_disable_intr_xscale()
459 regs = instance->reg_set; in megasas_enable_intr_ppc()
477 regs = instance->reg_set; in megasas_disable_intr_ppc()
581 regs = instance->reg_set; in megasas_enable_intr_skinny()
599 regs = instance->reg_set; in megasas_disable_intr_skinny()
721 regs = instance->reg_set; in megasas_enable_intr_gen2()
740 regs = instance->reg_set; in megasas_disable_intr_gen2()
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Dmegaraid_sas.h1683 struct megasas_register_set __iomem *reg_set; member
/linux-4.1.27/drivers/pinctrl/mediatek/
Dpinctrl-mt8173.c122 unsigned int reg_pupd, reg_set, reg_rst; in spec_pull_set() local
138 reg_set = spec_pupd_pin->offset + align; in spec_pull_set()
144 reg_pupd = reg_set; in spec_pull_set()
158 regmap_write(regmap, reg_set, bit_r0); in spec_pull_set()
163 regmap_write(regmap, reg_set, bit_r1); in spec_pull_set()
166 regmap_write(regmap, reg_set, bit_r0); in spec_pull_set()
167 regmap_write(regmap, reg_set, bit_r1); in spec_pull_set()
/linux-4.1.27/drivers/media/i2c/soc_camera/
Drj54n1cb0c.c462 static int reg_set(struct i2c_client *client, const u16 reg, in reg_set() function
503 return reg_set(client, RJ54N1_STILL_CONTROL, (!enable) << 7, 0x80); in rj54n1_s_stream()
882 ret = reg_set(client, RJ54N1_OCLK_DSP, 1, 1); in rj54n1_set_clock()
1031 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); in rj54n1_s_fmt()
1036 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8); in rj54n1_s_fmt()
1041 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); in rj54n1_s_fmt()
1046 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8); in rj54n1_s_fmt()
1051 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); in rj54n1_s_fmt()
1058 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); in rj54n1_s_fmt()
1065 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8); in rj54n1_s_fmt()
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Dmt9t031.c102 static int reg_set(struct i2c_client *client, const u8 reg, in reg_set() function
171 ret = reg_set(client, MT9T031_OUTPUT_CONTROL, 2); in mt9t031_s_stream()
244 ret = reg_set(client, MT9T031_OUTPUT_CONTROL, 1); in mt9t031_set_params()
458 data = reg_set(client, MT9T031_READ_MODE_2, 0x8000); in mt9t031_s_ctrl()
466 data = reg_set(client, MT9T031_READ_MODE_2, 0x4000); in mt9t031_s_ctrl()
710 return reg_set(client, MT9T031_PIXEL_CLOCK_CONTROL, 0x8000); in mt9t031_s_mbus_config()
Dmt9v022.c184 static int reg_set(struct i2c_client *client, const u8 reg, in reg_set() function
224 ret = reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x3); in mt9v022_init()
269 if (reg_set(client, MT9V022_REG32, 0x204)) in mt9v022_s_stream()
563 data = reg_set(client, MT9V022_READ_MODE, 0x10); in mt9v022_s_ctrl()
571 data = reg_set(client, MT9V022_READ_MODE, 0x20); in mt9v022_s_ctrl()
579 if (reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x2) < 0) in mt9v022_s_ctrl()
607 data = reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x1); in mt9v022_s_ctrl()
Dmt9m111.c133 #define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val)) macro
376 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); in mt9m111_reset()
378 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC); in mt9m111_reset()
685 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN); in mt9m111_set_autoexposure()
694 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN); in mt9m111_set_autowhitebalance()
728 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); in mt9m111_suspend()
730 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC | in mt9m111_suspend()
Dmt9m001.c121 static int reg_set(struct i2c_client *client, const u8 reg, in reg_set() function
394 data = reg_set(client, MT9M001_READ_OPTIONS2, 0x8000); in mt9m001_s_ctrl()
/linux-4.1.27/arch/powerpc/boot/
Dmpsc.c128 int n, reg_set; in mpsc_console_init() local
147 reg_set = (int)v; in mpsc_console_init()
149 mpscintr_base += (reg_set == 0) ? 0x4 : 0xc; in mpsc_console_init()
/linux-4.1.27/drivers/gpio/
Dgpio-generic.c170 bgc->write_reg(bgc->reg_set, mask); in bgpio_set_with_clear()
188 bgc->write_reg(bgc->reg_set, bgc->data); in bgpio_set_set()
248 bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_set); in bgpio_set_multiple_set()
261 bgc->write_reg(bgc->reg_set, set_mask); in bgpio_set_multiple_with_clear()
427 bgc->reg_set = set; in bgpio_setup_io()
432 bgc->reg_set = set; in bgpio_setup_io()
519 bgc->data = bgc->read_reg(bgc->reg_set); in bgpio_init()
Dgpio-moxart.c48 return !!(bgc->read_reg(bgc->reg_set) & BIT(offset)); in moxart_gpio_get()
82 bgc->data = bgc->read_reg(bgc->reg_set); in moxart_gpio_probe()
/linux-4.1.27/arch/arm/net/
Dbpf_jit_32.c175 u16 reg_set = saved_regs(ctx); in build_prologue() local
180 emit(ARM_PUSH(reg_set), ctx); in build_prologue()
183 if (reg_set) in build_prologue()
184 emit(ARM_PUSH(reg_set), ctx); in build_prologue()
215 u16 reg_set = saved_regs(ctx); in build_epilogue() local
220 reg_set &= ~(1 << ARM_LR); in build_epilogue()
224 reg_set &= ~(1 << ARM_IP); in build_epilogue()
225 reg_set |= (1 << ARM_SP); in build_epilogue()
226 emit(ARM_LDM(ARM_SP, reg_set), ctx); in build_epilogue()
228 if (reg_set) { in build_epilogue()
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/linux-4.1.27/drivers/leds/
Dleds-tca6507.c165 int reg_set; /* One bit per register where member
283 tca->reg_set |= (1 << bit); in set_select()
304 tca->reg_set |= 1 << reg; in set_code()
363 set = tca->reg_set; in tca6507_work()
365 tca->reg_set = 0; in tca6507_work()
549 if (tca->reg_set) in led_assign()
617 if (tca->reg_set) in tca6507_gpio_set_value()
802 tca->reg_set = 0x7f; in tca6507_probe()
/linux-4.1.27/drivers/gpu/drm/i2c/
Dtda998x_drv.c503 reg_set(struct tda998x_priv *priv, uint16_t reg, uint8_t val) in reg_set() function
532 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); in tda998x_reset()
613 reg_set(priv, REG_DIP_IF_FLAGS, bit); in tda998x_write_if()
655 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO); in tda998x_audio_mute()
657 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); in tda998x_audio_mute()
736 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); in tda998x_configure_audio()
922 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); in tda998x_encoder_mode_set()
1020 reg_set(priv, REG_TX33, TX33_HDMI); in tda998x_encoder_mode_set()
1108 reg_set(priv, REG_TX4, TX4_PD_RAM); in tda998x_encoder_get_modes()
1299 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM); in tda998x_create()
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/linux-4.1.27/include/linux/
Dbasic_mmio_gpio.h36 void __iomem *reg_set; member
/linux-4.1.27/drivers/media/i2c/
Dak881x.c49 static int reg_set(struct i2c_client *client, const u8 reg, in reg_set() function
174 reg_set(client, AK881X_VIDEO_PROCESS1, vp1, 0xf); in ak881x_s_std_output()
/linux-4.1.27/arch/ia64/include/uapi/asm/
Dperfmon.h86 unsigned short reg_set; /* event set for this register */ member
/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_uncore.c76 WARN_ON(d->reg_set == 0); in fw_domain_reset()
77 __raw_i915_write32(d->i915, d->reg_set, d->val_reset); in fw_domain_reset()
99 __raw_i915_write32(d->i915, d->reg_set, d->val_set); in fw_domain_get()
115 __raw_i915_write32(d->i915, d->reg_set, d->val_clear); in fw_domain_put()
1002 u32 reg_set, u32 reg_ack) in fw_domain_init() argument
1014 d->reg_set = reg_set; in fw_domain_init()
Di915_drv.h650 u32 reg_set; member
/linux-4.1.27/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_link.c3619 static struct bnx2x_reg_set reg_set[] = { in bnx2x_warpcore_enable_AN_KR2() local
3643 for (i = 0; i < ARRAY_SIZE(reg_set); i++) in bnx2x_warpcore_enable_AN_KR2()
3644 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_enable_AN_KR2()
3645 reg_set[i].val); in bnx2x_warpcore_enable_AN_KR2()
3658 static struct bnx2x_reg_set reg_set[] = { in bnx2x_disable_kr2() local
3678 for (i = 0; i < ARRAY_SIZE(reg_set); i++) in bnx2x_disable_kr2()
3679 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_disable_kr2()
3680 reg_set[i].val); in bnx2x_disable_kr2()
3720 static struct bnx2x_reg_set reg_set[] = { in bnx2x_warpcore_enable_AN_KR() local
3732 for (i = 0; i < ARRAY_SIZE(reg_set); i++) in bnx2x_warpcore_enable_AN_KR()
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