1/* 2 * Marvell 88SE64xx/88SE94xx main function head file 3 * 4 * Copyright 2007 Red Hat, Inc. 5 * Copyright 2008 Marvell. <kewei@marvell.com> 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 7 * 8 * This file is licensed under GPLv2. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; version 2 of the 13 * License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 23 * USA 24*/ 25 26#ifndef _MV_SAS_H_ 27#define _MV_SAS_H_ 28 29#include <linux/kernel.h> 30#include <linux/module.h> 31#include <linux/spinlock.h> 32#include <linux/delay.h> 33#include <linux/types.h> 34#include <linux/ctype.h> 35#include <linux/dma-mapping.h> 36#include <linux/pci.h> 37#include <linux/platform_device.h> 38#include <linux/interrupt.h> 39#include <linux/irq.h> 40#include <linux/slab.h> 41#include <linux/vmalloc.h> 42#include <asm/unaligned.h> 43#include <scsi/libsas.h> 44#include <scsi/scsi.h> 45#include <scsi/scsi_tcq.h> 46#include <scsi/sas_ata.h> 47#include "mv_defs.h" 48 49#define DRV_NAME "mvsas" 50#define DRV_VERSION "0.8.16" 51#define MVS_ID_NOT_MAPPED 0x7f 52#define WIDE_PORT_MAX_PHY 4 53#define mv_printk(fmt, arg ...) \ 54 printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg) 55#ifdef MV_DEBUG 56#define mv_dprintk(format, arg...) \ 57 printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg) 58#else 59#define mv_dprintk(format, arg...) 60#endif 61#define MV_MAX_U32 0xffffffff 62 63extern int interrupt_coalescing; 64extern struct mvs_tgt_initiator mvs_tgt; 65extern struct mvs_info *tgt_mvi; 66extern const struct mvs_dispatch mvs_64xx_dispatch; 67extern const struct mvs_dispatch mvs_94xx_dispatch; 68 69#define DEV_IS_EXPANDER(type) \ 70 ((type == SAS_EDGE_EXPANDER_DEVICE) || (type == SAS_FANOUT_EXPANDER_DEVICE)) 71 72#define bit(n) ((u64)1 << n) 73 74#define for_each_phy(__lseq_mask, __mc, __lseq) \ 75 for ((__mc) = (__lseq_mask), (__lseq) = 0; \ 76 (__mc) != 0 ; \ 77 (++__lseq), (__mc) >>= 1) 78 79#define MVS_PHY_ID (1U << sas_phy->id) 80#define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f) 81#define UNASSOC_D2H_FIS(id) \ 82 ((void *) mvi->rx_fis + 0x100 * id) 83#define SATA_RECEIVED_FIS_LIST(reg_set) \ 84 ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set) 85#define SATA_RECEIVED_SDB_FIS(reg_set) \ 86 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58) 87#define SATA_RECEIVED_D2H_FIS(reg_set) \ 88 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40) 89#define SATA_RECEIVED_PIO_FIS(reg_set) \ 90 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20) 91#define SATA_RECEIVED_DMA_FIS(reg_set) \ 92 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00) 93 94enum dev_status { 95 MVS_DEV_NORMAL = 0x0, 96 MVS_DEV_EH = 0x1, 97}; 98 99enum dev_reset { 100 MVS_SOFT_RESET = 0, 101 MVS_HARD_RESET = 1, 102 MVS_PHY_TUNE = 2, 103}; 104 105struct mvs_info; 106 107struct mvs_dispatch { 108 char *name; 109 int (*chip_init)(struct mvs_info *mvi); 110 int (*spi_init)(struct mvs_info *mvi); 111 int (*chip_ioremap)(struct mvs_info *mvi); 112 void (*chip_iounmap)(struct mvs_info *mvi); 113 irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat); 114 u32 (*isr_status)(struct mvs_info *mvi, int irq); 115 void (*interrupt_enable)(struct mvs_info *mvi); 116 void (*interrupt_disable)(struct mvs_info *mvi); 117 118 u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port); 119 void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val); 120 121 u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port); 122 void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val); 123 void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr); 124 125 u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port); 126 void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val); 127 void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr); 128 129 u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port); 130 void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val); 131 132 u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port); 133 void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val); 134 135 void (*command_active)(struct mvs_info *mvi, u32 slot_idx); 136 void (*clear_srs_irq)(struct mvs_info *mvi, u8 reg_set, u8 clear_all); 137 void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type, 138 u32 tfs); 139 void (*start_delivery)(struct mvs_info *mvi, u32 tx); 140 u32 (*rx_update)(struct mvs_info *mvi); 141 void (*int_full)(struct mvs_info *mvi); 142 u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs); 143 void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs); 144 u32 (*prd_size)(void); 145 u32 (*prd_count)(void); 146 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd); 147 void (*detect_porttype)(struct mvs_info *mvi, int i); 148 int (*oob_done)(struct mvs_info *mvi, int i); 149 void (*fix_phy_info)(struct mvs_info *mvi, int i, 150 struct sas_identify_frame *id); 151 void (*phy_work_around)(struct mvs_info *mvi, int i); 152 void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id, 153 struct sas_phy_linkrates *rates); 154 u32 (*phy_max_link_rate)(void); 155 void (*phy_disable)(struct mvs_info *mvi, u32 phy_id); 156 void (*phy_enable)(struct mvs_info *mvi, u32 phy_id); 157 void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard); 158 void (*stp_reset)(struct mvs_info *mvi, u32 phy_id); 159 void (*clear_active_cmds)(struct mvs_info *mvi); 160 u32 (*spi_read_data)(struct mvs_info *mvi); 161 void (*spi_write_data)(struct mvs_info *mvi, u32 data); 162 int (*spi_buildcmd)(struct mvs_info *mvi, 163 u32 *dwCmd, 164 u8 cmd, 165 u8 read, 166 u8 length, 167 u32 addr 168 ); 169 int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd); 170 int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout); 171 void (*dma_fix)(struct mvs_info *mvi, u32 phy_mask, 172 int buf_len, int from, void *prd); 173 void (*tune_interrupt)(struct mvs_info *mvi, u32 time); 174 void (*non_spec_ncq_error)(struct mvs_info *mvi); 175 176}; 177 178struct mvs_chip_info { 179 u32 n_host; 180 u32 n_phy; 181 u32 fis_offs; 182 u32 fis_count; 183 u32 srs_sz; 184 u32 sg_width; 185 u32 slot_width; 186 const struct mvs_dispatch *dispatch; 187}; 188#define MVS_MAX_SG (1U << mvi->chip->sg_width) 189#define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width) 190#define MVS_RX_FISL_SZ \ 191 (mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100)) 192#define MVS_CHIP_DISP (mvi->chip->dispatch) 193 194struct mvs_err_info { 195 __le32 flags; 196 __le32 flags2; 197}; 198 199struct mvs_cmd_hdr { 200 __le32 flags; /* PRD tbl len; SAS, SATA ctl */ 201 __le32 lens; /* cmd, max resp frame len */ 202 __le32 tags; /* targ port xfer tag; tag */ 203 __le32 data_len; /* data xfer len */ 204 __le64 cmd_tbl; /* command table address */ 205 __le64 open_frame; /* open addr frame address */ 206 __le64 status_buf; /* status buffer address */ 207 __le64 prd_tbl; /* PRD tbl address */ 208 __le32 reserved[4]; 209}; 210 211struct mvs_port { 212 struct asd_sas_port sas_port; 213 u8 port_attached; 214 u8 wide_port_phymap; 215 struct list_head list; 216}; 217 218struct mvs_phy { 219 struct mvs_info *mvi; 220 struct mvs_port *port; 221 struct asd_sas_phy sas_phy; 222 struct sas_identify identify; 223 struct scsi_device *sdev; 224 struct timer_list timer; 225 u64 dev_sas_addr; 226 u64 att_dev_sas_addr; 227 u32 att_dev_info; 228 u32 dev_info; 229 u32 phy_type; 230 u32 phy_status; 231 u32 irq_status; 232 u32 frame_rcvd_size; 233 u8 frame_rcvd[32]; 234 u8 phy_attached; 235 u8 phy_mode; 236 u8 reserved[2]; 237 u32 phy_event; 238 enum sas_linkrate minimum_linkrate; 239 enum sas_linkrate maximum_linkrate; 240}; 241 242struct mvs_device { 243 struct list_head dev_entry; 244 enum sas_device_type dev_type; 245 struct mvs_info *mvi_info; 246 struct domain_device *sas_device; 247 struct timer_list timer; 248 u32 attached_phy; 249 u32 device_id; 250 u32 running_req; 251 u8 taskfileset; 252 u8 dev_status; 253 u16 reserved; 254}; 255 256/* Generate PHY tunning parameters */ 257struct phy_tuning { 258 /* 1 bit, transmitter emphasis enable */ 259 u8 trans_emp_en:1; 260 /* 4 bits, transmitter emphasis amplitude */ 261 u8 trans_emp_amp:4; 262 /* 3 bits, reserved space */ 263 u8 Reserved_2bit_1:3; 264 /* 5 bits, transmitter amplitude */ 265 u8 trans_amp:5; 266 /* 2 bits, transmitter amplitude adjust */ 267 u8 trans_amp_adj:2; 268 /* 1 bit, reserved space */ 269 u8 resv_2bit_2:1; 270 /* 2 bytes, reserved space */ 271 u8 reserved[2]; 272}; 273 274struct ffe_control { 275 /* 4 bits, FFE Capacitor Select (value range 0~F) */ 276 u8 ffe_cap_sel:4; 277 /* 3 bits, FFE Resistor Select (value range 0~7) */ 278 u8 ffe_rss_sel:3; 279 /* 1 bit reserve*/ 280 u8 reserved:1; 281}; 282 283/* 284 * HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes. 285 * The data area is valid only Signature="MRVL". 286 * If any member fills with 0xFF, the member is invalid. 287 */ 288struct hba_info_page { 289 /* Dword 0 */ 290 /* 4 bytes, structure signature,should be "MRVL" at first initial */ 291 u8 signature[4]; 292 293 /* Dword 1-13 */ 294 u32 reserved1[13]; 295 296 /* Dword 14-29 */ 297 /* 64 bytes, SAS address for each port */ 298 u64 sas_addr[8]; 299 300 /* Dword 30-31 */ 301 /* 8 bytes for vanir 8 port PHY FFE seeting 302 * BIT 0~3 : FFE Capacitor select(value range 0~F) 303 * BIT 4~6 : FFE Resistor select(value range 0~7) 304 * BIT 7: reserve. 305 */ 306 307 struct ffe_control ffe_ctl[8]; 308 /* Dword 32 -43 */ 309 u32 reserved2[12]; 310 311 /* Dword 44-45 */ 312 /* 8 bytes, 0: 1.5G, 1: 3.0G, should be 0x01 at first initial */ 313 u8 phy_rate[8]; 314 315 /* Dword 46-53 */ 316 /* 32 bytes, PHY tuning parameters for each PHY*/ 317 struct phy_tuning phy_tuning[8]; 318 319 /* Dword 54-63 */ 320 u32 reserved3[10]; 321}; /* total 256 bytes */ 322 323struct mvs_slot_info { 324 struct list_head entry; 325 union { 326 struct sas_task *task; 327 void *tdata; 328 }; 329 u32 n_elem; 330 u32 tx; 331 u32 slot_tag; 332 333 /* DMA buffer for storing cmd tbl, open addr frame, status buffer, 334 * and PRD table 335 */ 336 void *buf; 337 dma_addr_t buf_dma; 338 void *response; 339 struct mvs_port *port; 340 struct mvs_device *device; 341 void *open_frame; 342}; 343 344struct mvs_info { 345 unsigned long flags; 346 347 /* host-wide lock */ 348 spinlock_t lock; 349 350 /* our device */ 351 struct pci_dev *pdev; 352 struct device *dev; 353 354 /* enhanced mode registers */ 355 void __iomem *regs; 356 357 /* peripheral or soc registers */ 358 void __iomem *regs_ex; 359 u8 sas_addr[SAS_ADDR_SIZE]; 360 361 /* SCSI/SAS glue */ 362 struct sas_ha_struct *sas; 363 struct Scsi_Host *shost; 364 365 /* TX (delivery) DMA ring */ 366 __le32 *tx; 367 dma_addr_t tx_dma; 368 369 /* cached next-producer idx */ 370 u32 tx_prod; 371 372 /* RX (completion) DMA ring */ 373 __le32 *rx; 374 dma_addr_t rx_dma; 375 376 /* RX consumer idx */ 377 u32 rx_cons; 378 379 /* RX'd FIS area */ 380 __le32 *rx_fis; 381 dma_addr_t rx_fis_dma; 382 383 /* DMA command header slots */ 384 struct mvs_cmd_hdr *slot; 385 dma_addr_t slot_dma; 386 387 u32 chip_id; 388 const struct mvs_chip_info *chip; 389 390 int tags_num; 391 unsigned long *tags; 392 /* further per-slot information */ 393 struct mvs_phy phy[MVS_MAX_PHYS]; 394 struct mvs_port port[MVS_MAX_PHYS]; 395 u32 id; 396 u64 sata_reg_set; 397 struct list_head *hba_list; 398 struct list_head soc_entry; 399 struct list_head wq_list; 400 unsigned long instance; 401 u16 flashid; 402 u32 flashsize; 403 u32 flashsectSize; 404 405 void *addon; 406 struct hba_info_page hba_info_param; 407 struct mvs_device devices[MVS_MAX_DEVICES]; 408 void *bulk_buffer; 409 dma_addr_t bulk_buffer_dma; 410 void *bulk_buffer1; 411 dma_addr_t bulk_buffer_dma1; 412#define TRASH_BUCKET_SIZE 0x20000 413 void *dma_pool; 414 struct mvs_slot_info slot_info[0]; 415}; 416 417struct mvs_prv_info{ 418 u8 n_host; 419 u8 n_phy; 420 u8 scan_finished; 421 u8 reserve; 422 struct mvs_info *mvi[2]; 423 struct tasklet_struct mv_tasklet; 424}; 425 426struct mvs_wq { 427 struct delayed_work work_q; 428 struct mvs_info *mvi; 429 void *data; 430 int handler; 431 struct list_head entry; 432}; 433 434struct mvs_task_exec_info { 435 struct sas_task *task; 436 struct mvs_cmd_hdr *hdr; 437 struct mvs_port *port; 438 u32 tag; 439 int n_elem; 440}; 441 442/******************** function prototype *********************/ 443void mvs_get_sas_addr(void *buf, u32 buflen); 444void mvs_tag_clear(struct mvs_info *mvi, u32 tag); 445void mvs_tag_free(struct mvs_info *mvi, u32 tag); 446void mvs_tag_set(struct mvs_info *mvi, unsigned int tag); 447int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out); 448void mvs_tag_init(struct mvs_info *mvi); 449void mvs_iounmap(void __iomem *regs); 450int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex); 451void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard); 452int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func, 453 void *funcdata); 454void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo, 455 u32 off_hi, u64 sas_addr); 456void mvs_scan_start(struct Scsi_Host *shost); 457int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time); 458int mvs_queue_command(struct sas_task *task, gfp_t gfp_flags); 459int mvs_abort_task(struct sas_task *task); 460int mvs_abort_task_set(struct domain_device *dev, u8 *lun); 461int mvs_clear_aca(struct domain_device *dev, u8 *lun); 462int mvs_clear_task_set(struct domain_device *dev, u8 * lun); 463void mvs_port_formed(struct asd_sas_phy *sas_phy); 464void mvs_port_deformed(struct asd_sas_phy *sas_phy); 465int mvs_dev_found(struct domain_device *dev); 466void mvs_dev_gone(struct domain_device *dev); 467int mvs_lu_reset(struct domain_device *dev, u8 *lun); 468int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags); 469int mvs_I_T_nexus_reset(struct domain_device *dev); 470int mvs_query_task(struct sas_task *task); 471void mvs_release_task(struct mvs_info *mvi, 472 struct domain_device *dev); 473void mvs_do_release_task(struct mvs_info *mvi, int phy_no, 474 struct domain_device *dev); 475void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events); 476void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st); 477int mvs_int_rx(struct mvs_info *mvi, bool self_clear); 478struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi, u8 reg_set); 479#endif 480 481