| H A D | intel_display.c | 81 struct intel_crtc_state *pipe_config);
83 struct intel_crtc_state *pipe_config);
101 const struct intel_crtc_state *pipe_config);
103 const struct intel_crtc_state *pipe_config);
1584 const struct intel_crtc_state *pipe_config) vlv_enable_pll()
1589 u32 dpll = pipe_config->dpll_hw_state.dpll; vlv_enable_pll()
1607 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); vlv_enable_pll()
1623 const struct intel_crtc_state *pipe_config) chv_enable_pll()
1648 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); chv_enable_pll()
1655 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); chv_enable_pll()
4870 struct intel_crtc_state *pipe_config = crtc->config; i9xx_pfit_enable() local
4872 if (!pipe_config->gmch_pfit.control) i9xx_pfit_enable()
4882 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); i9xx_pfit_enable()
4883 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); i9xx_pfit_enable()
5709 struct intel_crtc_state *pipe_config) ironlake_check_fdi_lanes()
5712 pipe_name(pipe), pipe_config->fdi_lanes); ironlake_check_fdi_lanes()
5713 if (pipe_config->fdi_lanes > 4) { ironlake_check_fdi_lanes()
5715 pipe_name(pipe), pipe_config->fdi_lanes); ironlake_check_fdi_lanes()
5720 if (pipe_config->fdi_lanes > 2) { ironlake_check_fdi_lanes()
5722 pipe_config->fdi_lanes); ironlake_check_fdi_lanes()
5737 if (pipe_config->fdi_lanes > 2 && ironlake_check_fdi_lanes()
5740 pipe_name(pipe), pipe_config->fdi_lanes); ironlake_check_fdi_lanes()
5745 if (pipe_config->fdi_lanes > 2) { ironlake_check_fdi_lanes()
5747 pipe_name(pipe), pipe_config->fdi_lanes); ironlake_check_fdi_lanes()
5762 struct intel_crtc_state *pipe_config) ironlake_fdi_compute_config()
5765 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; ironlake_fdi_compute_config()
5782 pipe_config->pipe_bpp); ironlake_fdi_compute_config()
5784 pipe_config->fdi_lanes = lane; ironlake_fdi_compute_config()
5786 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, ironlake_fdi_compute_config()
5787 link_bw, &pipe_config->fdi_m_n); ironlake_fdi_compute_config()
5790 intel_crtc->pipe, pipe_config); ironlake_fdi_compute_config()
5791 if (!setup_ok && pipe_config->pipe_bpp > 6*3) { ironlake_fdi_compute_config()
5792 pipe_config->pipe_bpp -= 2*3; ironlake_fdi_compute_config()
5794 pipe_config->pipe_bpp); ironlake_fdi_compute_config()
5796 pipe_config->bw_constrained = true; ironlake_fdi_compute_config()
5808 struct intel_crtc_state *pipe_config) hsw_compute_ips_config()
5810 pipe_config->ips_enabled = i915.enable_ips && hsw_compute_ips_config()
5812 pipe_config->pipe_bpp <= 24; hsw_compute_ips_config()
5816 struct intel_crtc_state *pipe_config) intel_crtc_compute_config()
5820 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; intel_crtc_compute_config()
5837 pipe_config->double_wide = true; intel_crtc_compute_config()
5850 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && intel_crtc_compute_config()
5851 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) intel_crtc_compute_config()
5852 pipe_config->pipe_src_w &= ~1; intel_crtc_compute_config()
5861 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { intel_crtc_compute_config()
5862 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ intel_crtc_compute_config()
5863 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { intel_crtc_compute_config()
5866 pipe_config->pipe_bpp = 8*3; intel_crtc_compute_config()
5870 hsw_compute_ips_config(crtc, pipe_config); intel_crtc_compute_config()
5872 if (pipe_config->has_pch_encoder) intel_crtc_compute_config()
5873 return ironlake_fdi_compute_config(crtc, pipe_config); intel_crtc_compute_config()
6194 struct intel_crtc_state *pipe_config) vlv_update_pll()
6209 pipe_config->dpll_hw_state.dpll = dpll; vlv_update_pll()
6211 dpll_md = (pipe_config->pixel_multiplier - 1) vlv_update_pll()
6213 pipe_config->dpll_hw_state.dpll_md = dpll_md; vlv_update_pll()
6217 const struct intel_crtc_state *pipe_config) vlv_prepare_pll()
6228 bestn = pipe_config->dpll.n; vlv_prepare_pll()
6229 bestm1 = pipe_config->dpll.m1; vlv_prepare_pll()
6230 bestm2 = pipe_config->dpll.m2; vlv_prepare_pll()
6231 bestp1 = pipe_config->dpll.p1; vlv_prepare_pll()
6232 bestp2 = pipe_config->dpll.p2; vlv_prepare_pll()
6269 if (pipe_config->port_clock == 162000 || vlv_prepare_pll()
6278 if (pipe_config->has_dp_encoder) { vlv_prepare_pll()
6308 struct intel_crtc_state *pipe_config) chv_update_pll()
6310 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | chv_update_pll()
6314 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; chv_update_pll()
6316 pipe_config->dpll_hw_state.dpll_md = chv_update_pll()
6317 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; chv_update_pll()
6321 const struct intel_crtc_state *pipe_config) chv_prepare_pll()
6333 bestn = pipe_config->dpll.n; chv_prepare_pll()
6334 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; chv_prepare_pll()
6335 bestm1 = pipe_config->dpll.m1; chv_prepare_pll()
6336 bestm2 = pipe_config->dpll.m2 >> 22; chv_prepare_pll()
6337 bestp1 = pipe_config->dpll.p1; chv_prepare_pll()
6338 bestp2 = pipe_config->dpll.p2; chv_prepare_pll()
6339 vco = pipe_config->dpll.vco; chv_prepare_pll()
6347 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); chv_prepare_pll()
6440 struct intel_crtc_state pipe_config = { vlv_force_pll_on() local
6447 chv_update_pll(crtc, &pipe_config); vlv_force_pll_on()
6448 chv_prepare_pll(crtc, &pipe_config); vlv_force_pll_on()
6449 chv_enable_pll(crtc, &pipe_config); vlv_force_pll_on()
6451 vlv_update_pll(crtc, &pipe_config); vlv_force_pll_on()
6452 vlv_prepare_pll(crtc, &pipe_config); vlv_force_pll_on()
6453 vlv_enable_pll(crtc, &pipe_config); vlv_force_pll_on()
6658 struct intel_crtc_state *pipe_config) intel_get_pipe_timings()
6662 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; intel_get_pipe_timings()
6666 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; intel_get_pipe_timings()
6667 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; intel_get_pipe_timings()
6669 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; intel_get_pipe_timings()
6670 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; intel_get_pipe_timings()
6672 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; intel_get_pipe_timings()
6673 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; intel_get_pipe_timings()
6676 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; intel_get_pipe_timings()
6677 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; intel_get_pipe_timings()
6679 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; intel_get_pipe_timings()
6680 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; intel_get_pipe_timings()
6682 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; intel_get_pipe_timings()
6683 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; intel_get_pipe_timings()
6686 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; intel_get_pipe_timings()
6687 pipe_config->base.adjusted_mode.crtc_vtotal += 1; intel_get_pipe_timings()
6688 pipe_config->base.adjusted_mode.crtc_vblank_end += 1; intel_get_pipe_timings()
6692 pipe_config->pipe_src_h = (tmp & 0xffff) + 1; intel_get_pipe_timings()
6693 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; intel_get_pipe_timings()
6695 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; intel_get_pipe_timings()
6696 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; intel_get_pipe_timings()
6700 struct intel_crtc_state *pipe_config) intel_mode_from_pipe_config()
6702 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; intel_mode_from_pipe_config()
6703 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; intel_mode_from_pipe_config()
6704 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; intel_mode_from_pipe_config()
6705 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; intel_mode_from_pipe_config()
6707 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; intel_mode_from_pipe_config()
6708 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; intel_mode_from_pipe_config()
6709 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; intel_mode_from_pipe_config()
6710 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; intel_mode_from_pipe_config()
6712 mode->flags = pipe_config->base.adjusted_mode.flags; intel_mode_from_pipe_config()
6714 mode->clock = pipe_config->base.adjusted_mode.crtc_clock; intel_mode_from_pipe_config()
6715 mode->flags |= pipe_config->base.adjusted_mode.flags; intel_mode_from_pipe_config()
6880 struct intel_crtc_state *pipe_config) i9xx_get_pfit_config()
6902 pipe_config->gmch_pfit.control = tmp; i9xx_get_pfit_config()
6903 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); i9xx_get_pfit_config()
6905 pipe_config->gmch_pfit.lvds_border_bits = i9xx_get_pfit_config()
6910 struct intel_crtc_state *pipe_config) vlv_crtc_clock_get()
6914 int pipe = pipe_config->cpu_transcoder; vlv_crtc_clock_get()
6920 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) vlv_crtc_clock_get()
6936 pipe_config->port_clock = clock.dot / 5; vlv_crtc_clock_get()
7009 struct intel_crtc_state *pipe_config) chv_crtc_clock_get()
7013 int pipe = pipe_config->cpu_transcoder; chv_crtc_clock_get()
7035 pipe_config->port_clock = clock.dot / 5; chv_crtc_clock_get()
7039 struct intel_crtc_state *pipe_config) i9xx_get_pipe_config()
7049 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; i9xx_get_pipe_config()
7050 pipe_config->shared_dpll = DPLL_ID_PRIVATE; i9xx_get_pipe_config()
7059 pipe_config->pipe_bpp = 18; i9xx_get_pipe_config()
7062 pipe_config->pipe_bpp = 24; i9xx_get_pipe_config()
7065 pipe_config->pipe_bpp = 30; i9xx_get_pipe_config()
7073 pipe_config->limited_color_range = true; i9xx_get_pipe_config()
7076 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; i9xx_get_pipe_config()
7078 intel_get_pipe_timings(crtc, pipe_config); i9xx_get_pipe_config()
7080 i9xx_get_pfit_config(crtc, pipe_config); i9xx_get_pipe_config()
7084 pipe_config->pixel_multiplier = i9xx_get_pipe_config()
7087 pipe_config->dpll_hw_state.dpll_md = tmp; i9xx_get_pipe_config()
7090 pipe_config->pixel_multiplier = i9xx_get_pipe_config()
7097 pipe_config->pixel_multiplier = 1; i9xx_get_pipe_config()
7099 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); i9xx_get_pipe_config()
7107 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; i9xx_get_pipe_config()
7109 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); i9xx_get_pipe_config()
7110 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); i9xx_get_pipe_config()
7113 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | i9xx_get_pipe_config()
7119 chv_crtc_clock_get(crtc, pipe_config); i9xx_get_pipe_config()
7121 vlv_crtc_clock_get(crtc, pipe_config); i9xx_get_pipe_config()
7123 i9xx_crtc_clock_get(crtc, pipe_config); i9xx_get_pipe_config()
7959 struct intel_crtc_state *pipe_config) intel_dp_get_m_n()
7961 if (pipe_config->has_pch_encoder) intel_dp_get_m_n()
7962 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); intel_dp_get_m_n()
7964 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, intel_dp_get_m_n()
7965 &pipe_config->dp_m_n, intel_dp_get_m_n()
7966 &pipe_config->dp_m2_n2); intel_dp_get_m_n()
7970 struct intel_crtc_state *pipe_config) ironlake_get_fdi_m_n_config()
7972 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, ironlake_get_fdi_m_n_config()
7973 &pipe_config->fdi_m_n, NULL); ironlake_get_fdi_m_n_config()
7977 struct intel_crtc_state *pipe_config) skylake_get_pfit_config()
7986 pipe_config->pch_pfit.enabled = true; skylake_get_pfit_config()
7987 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe)); skylake_get_pfit_config()
7988 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe)); skylake_get_pfit_config()
8077 struct intel_crtc_state *pipe_config) ironlake_get_pfit_config()
8086 pipe_config->pch_pfit.enabled = true; ironlake_get_pfit_config()
8087 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); ironlake_get_pfit_config()
8088 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); ironlake_get_pfit_config()
8170 struct intel_crtc_state *pipe_config) ironlake_get_pipe_config()
8180 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; ironlake_get_pipe_config()
8181 pipe_config->shared_dpll = DPLL_ID_PRIVATE; ironlake_get_pipe_config()
8189 pipe_config->pipe_bpp = 18; ironlake_get_pipe_config()
8192 pipe_config->pipe_bpp = 24; ironlake_get_pipe_config()
8195 pipe_config->pipe_bpp = 30; ironlake_get_pipe_config()
8198 pipe_config->pipe_bpp = 36; ironlake_get_pipe_config()
8205 pipe_config->limited_color_range = true; ironlake_get_pipe_config()
8210 pipe_config->has_pch_encoder = true; ironlake_get_pipe_config()
8213 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> ironlake_get_pipe_config()
8216 ironlake_get_fdi_m_n_config(crtc, pipe_config); ironlake_get_pipe_config()
8219 pipe_config->shared_dpll = ironlake_get_pipe_config()
8224 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; ironlake_get_pipe_config()
8226 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; ironlake_get_pipe_config()
8229 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; ironlake_get_pipe_config()
8232 &pipe_config->dpll_hw_state)); ironlake_get_pipe_config()
8234 tmp = pipe_config->dpll_hw_state.dpll; ironlake_get_pipe_config()
8235 pipe_config->pixel_multiplier = ironlake_get_pipe_config()
8239 ironlake_pch_clock_get(crtc, pipe_config); ironlake_get_pipe_config()
8241 pipe_config->pixel_multiplier = 1; ironlake_get_pipe_config()
8244 intel_get_pipe_timings(crtc, pipe_config); ironlake_get_pipe_config()
8246 ironlake_get_pfit_config(crtc, pipe_config); ironlake_get_pipe_config()
8486 struct intel_crtc_state *pipe_config) skylake_get_ddi_pll()
8491 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); skylake_get_ddi_pll()
8493 switch (pipe_config->ddi_pll_sel) { skylake_get_ddi_pll()
8501 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; skylake_get_ddi_pll()
8504 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; skylake_get_ddi_pll()
8507 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; skylake_get_ddi_pll()
8510 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; skylake_get_ddi_pll()
8517 struct intel_crtc_state *pipe_config) haswell_get_ddi_pll()
8519 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); haswell_get_ddi_pll()
8521 switch (pipe_config->ddi_pll_sel) { haswell_get_ddi_pll()
8523 pipe_config->shared_dpll = DPLL_ID_WRPLL1; haswell_get_ddi_pll()
8526 pipe_config->shared_dpll = DPLL_ID_WRPLL2; haswell_get_ddi_pll()
8532 struct intel_crtc_state *pipe_config) haswell_get_ddi_port_state()
8540 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); haswell_get_ddi_port_state()
8545 skylake_get_ddi_pll(dev_priv, port, pipe_config); haswell_get_ddi_port_state()
8547 haswell_get_ddi_pll(dev_priv, port, pipe_config); haswell_get_ddi_port_state()
8549 if (pipe_config->shared_dpll >= 0) { haswell_get_ddi_port_state()
8550 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; haswell_get_ddi_port_state()
8553 &pipe_config->dpll_hw_state)); haswell_get_ddi_port_state()
8563 pipe_config->has_pch_encoder = true; haswell_get_ddi_port_state()
8566 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> haswell_get_ddi_port_state()
8569 ironlake_get_fdi_m_n_config(crtc, pipe_config); haswell_get_ddi_port_state()
8574 struct intel_crtc_state *pipe_config) haswell_get_pipe_config()
8585 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; haswell_get_pipe_config()
8586 pipe_config->shared_dpll = DPLL_ID_PRIVATE; haswell_get_pipe_config()
8607 pipe_config->cpu_transcoder = TRANSCODER_EDP; haswell_get_pipe_config()
8611 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) haswell_get_pipe_config()
8614 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); haswell_get_pipe_config()
8618 haswell_get_ddi_port_state(crtc, pipe_config); haswell_get_pipe_config()
8620 intel_get_pipe_timings(crtc, pipe_config); haswell_get_pipe_config()
8625 skylake_get_pfit_config(crtc, pipe_config); haswell_get_pipe_config()
8627 ironlake_get_pfit_config(crtc, pipe_config); haswell_get_pipe_config()
8631 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && haswell_get_pipe_config()
8634 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { haswell_get_pipe_config()
8635 pipe_config->pixel_multiplier = haswell_get_pipe_config()
8636 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; haswell_get_pipe_config()
8638 pipe_config->pixel_multiplier = 1; haswell_get_pipe_config()
9204 const struct intel_crtc_state *pipe_config) i9xx_pll_refclk()
9207 u32 dpll = pipe_config->dpll_hw_state.dpll; i9xx_pll_refclk()
9221 struct intel_crtc_state *pipe_config) i9xx_crtc_clock_get()
9225 int pipe = pipe_config->cpu_transcoder; i9xx_crtc_clock_get()
9226 u32 dpll = pipe_config->dpll_hw_state.dpll; i9xx_crtc_clock_get()
9229 int refclk = i9xx_pll_refclk(dev, pipe_config); i9xx_crtc_clock_get()
9232 fp = pipe_config->dpll_hw_state.fp0; i9xx_crtc_clock_get()
9234 fp = pipe_config->dpll_hw_state.fp1; i9xx_crtc_clock_get()
9305 pipe_config->port_clock = clock.dot; i9xx_crtc_clock_get()
9328 struct intel_crtc_state *pipe_config) ironlake_pch_clock_get()
9333 i9xx_crtc_clock_get(crtc, pipe_config); ironlake_pch_clock_get()
9341 pipe_config->base.adjusted_mode.crtc_clock = ironlake_pch_clock_get()
9343 &pipe_config->fdi_m_n); ironlake_pch_clock_get()
9354 struct intel_crtc_state pipe_config; intel_crtc_mode_get() local
9366 * Construct a pipe_config sufficient for getting the clock info intel_crtc_mode_get()
9372 pipe_config.cpu_transcoder = (enum transcoder) pipe; intel_crtc_mode_get()
9373 pipe_config.pixel_multiplier = 1; intel_crtc_mode_get()
9374 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); intel_crtc_mode_get()
9375 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); intel_crtc_mode_get()
9376 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); intel_crtc_mode_get()
9377 i9xx_crtc_clock_get(intel_crtc, &pipe_config); intel_crtc_mode_get()
9379 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; intel_crtc_mode_get()
10374 struct intel_crtc_state *pipe_config) connected_sink_compute_bpp()
10376 int bpp = pipe_config->pipe_bpp; connected_sink_compute_bpp()
10387 pipe_config->pipe_bpp = connector->base.display_info.bpc*3; connected_sink_compute_bpp()
10403 pipe_config->pipe_bpp = clamp_bpp; connected_sink_compute_bpp()
10411 struct intel_crtc_state *pipe_config) compute_baseline_pipe_bpp()
10454 pipe_config->pipe_bpp = bpp; compute_baseline_pipe_bpp()
10456 state = pipe_config->base.state; compute_baseline_pipe_bpp()
10467 connected_sink_compute_bpp(connector, pipe_config); compute_baseline_pipe_bpp()
10485 struct intel_crtc_state *pipe_config, intel_dump_pipe_config()
10491 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); intel_dump_pipe_config()
10493 pipe_config->pipe_bpp, pipe_config->dither); intel_dump_pipe_config()
10495 pipe_config->has_pch_encoder, intel_dump_pipe_config()
10496 pipe_config->fdi_lanes, intel_dump_pipe_config()
10497 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, intel_dump_pipe_config()
10498 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, intel_dump_pipe_config()
10499 pipe_config->fdi_m_n.tu); intel_dump_pipe_config()
10501 pipe_config->has_dp_encoder, intel_dump_pipe_config()
10502 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, intel_dump_pipe_config()
10503 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, intel_dump_pipe_config()
10504 pipe_config->dp_m_n.tu); intel_dump_pipe_config()
10507 pipe_config->has_dp_encoder, intel_dump_pipe_config()
10508 pipe_config->dp_m2_n2.gmch_m, intel_dump_pipe_config()
10509 pipe_config->dp_m2_n2.gmch_n, intel_dump_pipe_config()
10510 pipe_config->dp_m2_n2.link_m, intel_dump_pipe_config()
10511 pipe_config->dp_m2_n2.link_n, intel_dump_pipe_config()
10512 pipe_config->dp_m2_n2.tu); intel_dump_pipe_config()
10515 pipe_config->has_audio, intel_dump_pipe_config()
10516 pipe_config->has_infoframe); intel_dump_pipe_config()
10519 drm_mode_debug_printmodeline(&pipe_config->base.mode); intel_dump_pipe_config()
10521 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); intel_dump_pipe_config()
10522 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); intel_dump_pipe_config()
10523 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); intel_dump_pipe_config()
10525 pipe_config->pipe_src_w, pipe_config->pipe_src_h); intel_dump_pipe_config()
10527 pipe_config->gmch_pfit.control, intel_dump_pipe_config()
10528 pipe_config->gmch_pfit.pgm_ratios, intel_dump_pipe_config()
10529 pipe_config->gmch_pfit.lvds_border_bits); intel_dump_pipe_config()
10531 pipe_config->pch_pfit.pos, intel_dump_pipe_config()
10532 pipe_config->pch_pfit.size, intel_dump_pipe_config()
10533 pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); intel_dump_pipe_config()
10534 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); intel_dump_pipe_config()
10535 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); intel_dump_pipe_config()
10641 struct intel_crtc_state *pipe_config; intel_modeset_pipe_config() local
10656 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc)); intel_modeset_pipe_config()
10657 if (IS_ERR(pipe_config)) intel_modeset_pipe_config()
10658 return pipe_config; intel_modeset_pipe_config()
10660 clear_intel_crtc_state(pipe_config); intel_modeset_pipe_config()
10662 pipe_config->base.crtc = crtc; intel_modeset_pipe_config()
10663 drm_mode_copy(&pipe_config->base.adjusted_mode, mode); intel_modeset_pipe_config()
10664 drm_mode_copy(&pipe_config->base.mode, mode); intel_modeset_pipe_config()
10666 pipe_config->cpu_transcoder = intel_modeset_pipe_config()
10668 pipe_config->shared_dpll = DPLL_ID_PRIVATE; intel_modeset_pipe_config()
10675 if (!(pipe_config->base.adjusted_mode.flags & intel_modeset_pipe_config()
10677 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; intel_modeset_pipe_config()
10679 if (!(pipe_config->base.adjusted_mode.flags & intel_modeset_pipe_config()
10681 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; intel_modeset_pipe_config()
10683 /* Compute a starting value for pipe_config->pipe_bpp taking the source intel_modeset_pipe_config()
10688 fb, pipe_config); intel_modeset_pipe_config()
10700 drm_crtc_get_hv_timing(&pipe_config->base.mode, intel_modeset_pipe_config()
10701 &pipe_config->pipe_src_w, intel_modeset_pipe_config()
10702 &pipe_config->pipe_src_h); intel_modeset_pipe_config()
10706 pipe_config->port_clock = 0; intel_modeset_pipe_config()
10707 pipe_config->pixel_multiplier = 1; intel_modeset_pipe_config()
10710 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, intel_modeset_pipe_config()
10728 if (!(encoder->compute_config(encoder, pipe_config))) { intel_modeset_pipe_config()
10736 if (!pipe_config->port_clock) intel_modeset_pipe_config()
10737 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock intel_modeset_pipe_config()
10738 * pipe_config->pixel_multiplier; intel_modeset_pipe_config()
10740 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); intel_modeset_pipe_config()
10757 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; intel_modeset_pipe_config()
10759 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); intel_modeset_pipe_config()
10761 return pipe_config; intel_modeset_pipe_config()
10945 struct intel_crtc_state *pipe_config) intel_pipe_config_compare()
10948 if (current_config->name != pipe_config->name) { \ intel_pipe_config_compare()
10952 pipe_config->name); \ intel_pipe_config_compare()
10957 if (current_config->name != pipe_config->name) { \ intel_pipe_config_compare()
10961 pipe_config->name); \ intel_pipe_config_compare()
10971 if ((current_config->name != pipe_config->name) && \ intel_pipe_config_compare()
10972 (current_config->alt_name != pipe_config->name)) { \ intel_pipe_config_compare()
10977 pipe_config->name); \ intel_pipe_config_compare()
10982 if ((current_config->name ^ pipe_config->name) & (mask)) { \ intel_pipe_config_compare()
10986 pipe_config->name & (mask)); \ intel_pipe_config_compare()
10991 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ intel_pipe_config_compare()
10995 pipe_config->name); \ intel_pipe_config_compare()
11000 ((current_config->quirks | pipe_config->quirks) & (quirk)) intel_pipe_config_compare()
11260 struct intel_crtc_state pipe_config; check_crtc_state() local
11266 memset(&pipe_config, 0, sizeof(pipe_config)); for_each_intel_crtc()
11291 &pipe_config);
11303 encoder->get_config(encoder, &pipe_config); for_each_intel_encoder()
11311 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11313 intel_dump_pipe_config(crtc, &pipe_config,
11380 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, ironlake_check_encoder_dotclock() argument
11387 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), ironlake_check_encoder_dotclock()
11389 pipe_config->base.adjusted_mode.crtc_clock, dotclock); ironlake_check_encoder_dotclock()
11440 struct intel_crtc_state *pipe_config = NULL; intel_modeset_compute_config() local
11452 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); intel_modeset_compute_config()
11453 if (IS_ERR(pipe_config)) intel_modeset_compute_config()
11454 return pipe_config; intel_modeset_compute_config()
11456 pipe_config->base.enable = false; intel_modeset_compute_config()
11462 * (i.e. one pipe_config for each crtc) rather than just the one intel_modeset_compute_config()
11471 pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state); intel_modeset_compute_config()
11472 if (IS_ERR(pipe_config)) intel_modeset_compute_config()
11473 return pipe_config; intel_modeset_compute_config()
11475 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, intel_modeset_compute_config()
11515 struct intel_crtc_state *pipe_config, __intel_set_mode()
11540 to_intel_crtc(crtc)->new_config = pipe_config; __intel_set_mode()
11579 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config); local
11587 &pipe_config->base.adjusted_mode);
11594 modeset_update_crtc_power_domains(pipe_config->base.state);
11623 if (ret == 0 && pipe_config) {
11626 /* The pipe_config will be freed with the atomic state, so
11646 struct intel_crtc_state *pipe_config, intel_set_mode_pipes()
11653 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes, intel_set_mode_pipes()
11667 struct intel_crtc_state *pipe_config; intel_set_mode() local
11671 pipe_config = intel_modeset_compute_config(crtc, mode, fb, state, intel_set_mode()
11676 if (IS_ERR(pipe_config)) { intel_set_mode()
11677 ret = PTR_ERR(pipe_config); intel_set_mode()
11681 ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config, intel_set_mode()
12083 struct intel_crtc_state *pipe_config; intel_crtc_set_config() local
12138 pipe_config = intel_modeset_compute_config(set->crtc, set->mode, intel_crtc_set_config()
12143 if (IS_ERR(pipe_config)) { intel_crtc_set_config()
12144 ret = PTR_ERR(pipe_config); intel_crtc_set_config()
12146 } else if (pipe_config) { intel_crtc_set_config()
12147 if (pipe_config->has_audio != intel_crtc_set_config()
12163 set->x, set->y, set->fb, pipe_config, intel_crtc_set_config()
1583 vlv_enable_pll(struct intel_crtc *crtc, const struct intel_crtc_state *pipe_config) vlv_enable_pll() argument
1622 chv_enable_pll(struct intel_crtc *crtc, const struct intel_crtc_state *pipe_config) chv_enable_pll() argument
5708 ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, struct intel_crtc_state *pipe_config) ironlake_check_fdi_lanes() argument
5761 ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, struct intel_crtc_state *pipe_config) ironlake_fdi_compute_config() argument
5807 hsw_compute_ips_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) hsw_compute_ips_config() argument
5815 intel_crtc_compute_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) intel_crtc_compute_config() argument
6193 vlv_update_pll(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) vlv_update_pll() argument
6216 vlv_prepare_pll(struct intel_crtc *crtc, const struct intel_crtc_state *pipe_config) vlv_prepare_pll() argument
6307 chv_update_pll(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) chv_update_pll() argument
6320 chv_prepare_pll(struct intel_crtc *crtc, const struct intel_crtc_state *pipe_config) chv_prepare_pll() argument
6657 intel_get_pipe_timings(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) intel_get_pipe_timings() argument
6699 intel_mode_from_pipe_config(struct drm_display_mode *mode, struct intel_crtc_state *pipe_config) intel_mode_from_pipe_config() argument
6879 i9xx_get_pfit_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) i9xx_get_pfit_config() argument
6909 vlv_crtc_clock_get(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) vlv_crtc_clock_get() argument
7008 chv_crtc_clock_get(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) chv_crtc_clock_get() argument
7038 i9xx_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) i9xx_get_pipe_config() argument
7958 intel_dp_get_m_n(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) intel_dp_get_m_n() argument
7969 ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) ironlake_get_fdi_m_n_config() argument
7976 skylake_get_pfit_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) skylake_get_pfit_config() argument
8076 ironlake_get_pfit_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) ironlake_get_pfit_config() argument
8169 ironlake_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) ironlake_get_pipe_config() argument
8484 skylake_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, struct intel_crtc_state *pipe_config) skylake_get_ddi_pll() argument
8515 haswell_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, struct intel_crtc_state *pipe_config) haswell_get_ddi_pll() argument
8531 haswell_get_ddi_port_state(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) haswell_get_ddi_port_state() argument
8573 haswell_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) haswell_get_pipe_config() argument
9203 i9xx_pll_refclk(struct drm_device *dev, const struct intel_crtc_state *pipe_config) i9xx_pll_refclk() argument
9220 i9xx_crtc_clock_get(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) i9xx_crtc_clock_get() argument
9327 ironlake_pch_clock_get(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) ironlake_pch_clock_get() argument
10373 connected_sink_compute_bpp(struct intel_connector *connector, struct intel_crtc_state *pipe_config) connected_sink_compute_bpp() argument
10409 compute_baseline_pipe_bpp(struct intel_crtc *crtc, struct drm_framebuffer *fb, struct intel_crtc_state *pipe_config) compute_baseline_pipe_bpp() argument
10484 intel_dump_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config, const char *context) intel_dump_pipe_config() argument
10943 intel_pipe_config_compare(struct drm_device *dev, struct intel_crtc_state *current_config, struct intel_crtc_state *pipe_config) intel_pipe_config_compare() argument
11512 __intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, int x, int y, struct drm_framebuffer *fb, struct intel_crtc_state *pipe_config, unsigned modeset_pipes, unsigned prepare_pipes, unsigned disable_pipes) __intel_set_mode() argument
11643 intel_set_mode_pipes(struct drm_crtc *crtc, struct drm_display_mode *mode, int x, int y, struct drm_framebuffer *fb, struct intel_crtc_state *pipe_config, unsigned modeset_pipes, unsigned prepare_pipes, unsigned disable_pipes) intel_set_mode_pipes() argument
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