| /linux-4.1.27/drivers/gpu/drm/i915/ |
| D | intel_dp_mst.c | 34 struct intel_crtc_state *pipe_config) in intel_dp_mst_compute_config() argument
42 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_dp_mst_compute_config()
46 pipe_config->dp_encoder_is_mst = true; in intel_dp_mst_compute_config()
47 pipe_config->has_pch_encoder = false; in intel_dp_mst_compute_config()
48 pipe_config->has_dp_encoder = true; in intel_dp_mst_compute_config()
68 pipe_config->pipe_bpp = 24; in intel_dp_mst_compute_config()
69 pipe_config->port_clock = rate; in intel_dp_mst_compute_config()
71 state = pipe_config->base.state; in intel_dp_mst_compute_config()
90 pipe_config->pbn = mst_pbn; in intel_dp_mst_compute_config()
95 pipe_config->port_clock, in intel_dp_mst_compute_config()
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| D | intel_display.c | 81 struct intel_crtc_state *pipe_config);
83 struct intel_crtc_state *pipe_config);
101 const struct intel_crtc_state *pipe_config);
103 const struct intel_crtc_state *pipe_config);
1584 const struct intel_crtc_state *pipe_config) in vlv_enable_pll() argument
1589 u32 dpll = pipe_config->dpll_hw_state.dpll; in vlv_enable_pll()
1607 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1623 const struct intel_crtc_state *pipe_config) in chv_enable_pll() argument
1648 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in chv_enable_pll()
1655 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
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| D | intel_panel.c | 102 struct intel_crtc_state *pipe_config, in intel_pch_panel_fitting() argument
108 adjusted_mode = &pipe_config->base.adjusted_mode; in intel_pch_panel_fitting()
113 if (adjusted_mode->hdisplay == pipe_config->pipe_src_w && in intel_pch_panel_fitting()
114 adjusted_mode->vdisplay == pipe_config->pipe_src_h) in intel_pch_panel_fitting()
119 width = pipe_config->pipe_src_w; in intel_pch_panel_fitting()
120 height = pipe_config->pipe_src_h; in intel_pch_panel_fitting()
129 * pipe_config->pipe_src_h; in intel_pch_panel_fitting()
130 u32 scaled_height = pipe_config->pipe_src_w in intel_pch_panel_fitting()
133 width = scaled_height / pipe_config->pipe_src_h; in intel_pch_panel_fitting()
140 height = scaled_width / pipe_config->pipe_src_w; in intel_pch_panel_fitting()
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| D | intel_ddi.c | 773 struct intel_crtc_state *pipe_config) in skl_ddi_clock_get() argument
779 dpll = pipe_config->ddi_pll_sel; in skl_ddi_clock_get()
815 pipe_config->port_clock = link_clock; in skl_ddi_clock_get()
817 if (pipe_config->has_dp_encoder) in skl_ddi_clock_get()
818 pipe_config->base.adjusted_mode.crtc_clock = in skl_ddi_clock_get()
819 intel_dotclock_calculate(pipe_config->port_clock, in skl_ddi_clock_get()
820 &pipe_config->dp_m_n); in skl_ddi_clock_get()
822 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; in skl_ddi_clock_get()
826 struct intel_crtc_state *pipe_config) in hsw_ddi_clock_get() argument
832 val = pipe_config->ddi_pll_sel; in hsw_ddi_clock_get()
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| D | intel_lvds.c | 97 struct intel_crtc_state *pipe_config) in intel_lvds_get_config() argument
119 pipe_config->base.adjusted_mode.flags |= flags; in intel_lvds_get_config()
125 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; in intel_lvds_get_config()
128 dotclock = pipe_config->port_clock; in intel_lvds_get_config()
131 ironlake_check_encoder_dotclock(pipe_config, dotclock); in intel_lvds_get_config()
133 pipe_config->base.adjusted_mode.crtc_clock = dotclock; in intel_lvds_get_config()
281 struct intel_crtc_state *pipe_config) in intel_lvds_compute_config() argument
288 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_lvds_compute_config()
289 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); in intel_lvds_compute_config()
303 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { in intel_lvds_compute_config()
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| D | intel_crt.c | 114 struct intel_crtc_state *pipe_config) in intel_crt_get_config() argument
119 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); in intel_crt_get_config()
121 dotclock = pipe_config->port_clock; in intel_crt_get_config()
124 ironlake_check_encoder_dotclock(pipe_config, dotclock); in intel_crt_get_config()
126 pipe_config->base.adjusted_mode.crtc_clock = dotclock; in intel_crt_get_config()
130 struct intel_crtc_state *pipe_config) in hsw_crt_get_config() argument
132 intel_ddi_get_config(encoder, pipe_config); in hsw_crt_get_config()
134 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | in hsw_crt_get_config()
138 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); in hsw_crt_get_config()
307 struct intel_crtc_state *pipe_config) in intel_crt_compute_config() argument
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| D | intel_hdmi.c | 763 struct intel_crtc_state *pipe_config) in intel_hdmi_get_config() argument
784 pipe_config->has_hdmi_sink = true; in intel_hdmi_get_config()
787 pipe_config->has_infoframe = true; in intel_hdmi_get_config()
790 pipe_config->has_audio = true; in intel_hdmi_get_config()
794 pipe_config->limited_color_range = true; in intel_hdmi_get_config()
796 pipe_config->base.adjusted_mode.flags |= flags; in intel_hdmi_get_config()
799 dotclock = pipe_config->port_clock * 2 / 3; in intel_hdmi_get_config()
801 dotclock = pipe_config->port_clock; in intel_hdmi_get_config()
804 ironlake_check_encoder_dotclock(pipe_config, dotclock); in intel_hdmi_get_config()
806 pipe_config->base.adjusted_mode.crtc_clock = dotclock; in intel_hdmi_get_config()
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| D | intel_sdvo.c | 1089 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) in i9xx_adjust_sdvo_tv_clock() argument
1091 unsigned dotclock = pipe_config->port_clock; in i9xx_adjust_sdvo_tv_clock()
1092 struct dpll *clock = &pipe_config->dpll; in i9xx_adjust_sdvo_tv_clock()
1112 pipe_config->clock_set = true; in i9xx_adjust_sdvo_tv_clock()
1116 struct intel_crtc_state *pipe_config) in intel_sdvo_compute_config() argument
1119 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_sdvo_compute_config()
1120 struct drm_display_mode *mode = &pipe_config->base.mode; in intel_sdvo_compute_config()
1123 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()
1126 pipe_config->has_pch_encoder = true; in intel_sdvo_compute_config()
1140 pipe_config->sdvo_tv_clock = true; in intel_sdvo_compute_config()
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| D | intel_dvo.c | 148 struct intel_crtc_state *pipe_config) in intel_dvo_get_config() argument
164 pipe_config->base.adjusted_mode.flags |= flags; in intel_dvo_get_config()
166 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
265 struct intel_crtc_state *pipe_config) in intel_dvo_compute_config() argument
268 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_dvo_compute_config()
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| D | intel_dp.c | 1082 skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock) in skl_edp_set_pll_config() argument
1086 pipe_config->ddi_pll_sel = SKL_DPLL0; in skl_edp_set_pll_config()
1087 pipe_config->dpll_hw_state.cfgcr1 = 0; in skl_edp_set_pll_config()
1088 pipe_config->dpll_hw_state.cfgcr2 = 0; in skl_edp_set_pll_config()
1121 pipe_config->dpll_hw_state.ctrl1 = ctrl1; in skl_edp_set_pll_config()
1125 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw) in hsw_dp_set_ddi_pll_sel() argument
1129 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; in hsw_dp_set_ddi_pll_sel()
1132 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; in hsw_dp_set_ddi_pll_sel()
1135 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; in hsw_dp_set_ddi_pll_sel()
1188 struct intel_crtc_state *pipe_config, int link_bw) in intel_dp_set_clock() argument
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| D | intel_drv.h | 160 struct intel_crtc_state *pipe_config);
870 struct intel_crtc_state *pipe_config);
874 struct intel_crtc_state *pipe_config);
1042 struct intel_crtc_state *pipe_config);
1046 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1054 struct intel_crtc_state *pipe_config);
1074 struct intel_crtc_state *pipe_config);
1157 struct intel_crtc_state *pipe_config);
1192 struct intel_crtc_state *pipe_config,
1195 struct intel_crtc_state *pipe_config,
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| D | intel_tv.c | 912 struct intel_crtc_state *pipe_config) in intel_tv_get_config() argument
914 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_tv_get_config()
919 struct intel_crtc_state *pipe_config) in intel_tv_compute_config() argument
927 pipe_config->base.adjusted_mode.crtc_clock = tv_mode->clock; in intel_tv_compute_config()
929 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
932 pipe_config->base.adjusted_mode.flags = 0; in intel_tv_compute_config()
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| D | intel_dsi.c | 624 struct intel_crtc_state *pipe_config) in intel_dsi_get_config() argument
633 pipe_config->dpll_hw_state.dpll_md = 0; in intel_dsi_get_config()
635 pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); in intel_dsi_get_config()
639 pipe_config->base.adjusted_mode.crtc_clock = pclk; in intel_dsi_get_config()
640 pipe_config->port_clock = pclk; in intel_dsi_get_config()
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| /linux-4.1.27/drivers/gpu/drm/radeon/ |
| D | atombios_crtc.c | 1341 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; in dce4_crtc_do_set_base() local
1343 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config); in dce4_crtc_do_set_base()
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